NXP KW2xD Reference guide

MKW2xD Reference Manual

Supports: MKW24D512, MKW22D512, MKW21D512, and

MKW21D256

Document Number: MKW2xDRM

Rev. 3, 05/2016

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Contents

Section number Title Page

Chapter 1

About This Document

1.1 Overview.......................................................................................................................................................................53

1.1.1 Purpose...........................................................................................................................................................53

1.1.2 Audience........................................................................................................................................................ 53

1.2 Conventions.................................................................................................................................................................. 53

1.2.1 Numbering systems........................................................................................................................................53

1.2.2 Typographic notation..................................................................................................................................... 54

1.2.3 Special terms..................................................................................................................................................54

Chapter 2

SiP: Introduction to the MKW2xD SiP

2.1 Introduction...................................................................................................................................................................55

2.2 Block Diagrams............................................................................................................................................................ 57

2.3 Modem Features Summary...........................................................................................................................................59

2.4 RF Interface and Usage.................................................................................................................................................61

2.5 Radio Architecture........................................................................................................................................................61

2.5.1 Packet Structure............................................................................................................................................. 61

2.5.2 Receive Path Description...............................................................................................................................61

2.5.3 Transmit Path Description............................................................................................................................. 62

2.6 IEEE 802.15.4 Acceleration Hardware.........................................................................................................................62

2.7 MCU Interface with SPI Overview...............................................................................................................................62

2.7.1 Transceiver Control Overview.......................................................................................................................64

2.8 Clock Output, RF Control, and GPIO Summary..........................................................................................................65

2.8.1 CLK_OUT Reference.................................................................................................................................... 65

2.8.2 RF Control Signals.........................................................................................................................................65

2.8.3 Antenna Diversity.......................................................................................................................................... 66

2.8.4 General Purpose Input Output (GPIO)...........................................................................................................66

2.9 Modem Operational Modes.......................................................................................................................................... 66

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2.10 Modem Features............................................................................................................................................................67

2.10.1 Memory and package options........................................................................................................................ 69

2.10.2 FlexMemory for the MWK21D256............................................................................................................... 69

2.10.3 External PA and LNA....................................................................................................................................71

2.11 MCU Introduction.........................................................................................................................................................71

2.11.1 Module Functional Categories.......................................................................................................................71

Chapter 3

SiP: Signal Multiplexing and Signal Descriptions

3.1 MKW22/24D512V Pin Assignment.............................................................................................................................79

3.2 MKW21D256/MKW21D512 Pin Assignment.............................................................................................................80

3.3 MKW2xD Pins............................................................................................................................................................. 80

3.4 Modem: Digital Signal Properties Summary ...............................................................................................................84

Chapter 4

SiP: System Considerations

4.1 Introduction...................................................................................................................................................................87

4.2 Power Connections....................................................................................................................................................... 87

4.3 Internal Functional Interconnects and System Reset....................................................................................................89

4.3.1 System Reset..................................................................................................................................................90

4.3.2 Modem Interrupt Request to MCU................................................................................................................ 92

4.3.3 SPI Command Channel..................................................................................................................................93

4.4 Clock Sources............................................................................................................................................................... 94

4.4.1 Modem Oscillator.......................................................................................................................................... 94

4.4.2 Modem CLK_OUT Clock Source Output..................................................................................................... 95

4.4.3 MCU Clock Sources...................................................................................................................................... 96

4.4.4 System Clock Configurations........................................................................................................................ 97

4.5 GPIO for Modem and MCU......................................................................................................................................... 100

4.5.1 MCU GPIO Characteristics........................................................................................................................... 100

4.5.2 Modem GPIO Characteristics........................................................................................................................ 101

4.6 Transceiver RF Configurations and External Connections.......................................................................................... 101

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4.6.1 RF Interface Pins............................................................................................................................................102

4.6.2 RF Output Power Distribution....................................................................................................................... 107

4.6.3 LQI ED RSSI................................................................................................................................................. 108

4.7 Timer Resources........................................................................................................................................................... 110

4.7.1 MCU Timers.................................................................................................................................................. 110

4.7.2 Modem Event Timer...................................................................................................................................... 110

4.8 Low Power Considerations...........................................................................................................................................111

4.8.1 Low-Power Preamble Search (LPPS)............................................................................................................112

4.8.2 Modem Low Power States............................................................................................................................. 114

4.8.3 MCU Low Power Modes............................................................................................................................... 115

4.8.4 Recovery Times from Low Power Modes..................................................................................................... 115

4.8.5 Run Time Current.......................................................................................................................................... 116

4.8.6 Configuration of Interconnected GPIO for Low Power Operation................................................................117

4.8.7 General System Considerations for Low Power............................................................................................118

Chapter 5

Modem: Modes of Operation

5.1 Power Management Overview......................................................................................................................................121

5.1.1 Features.......................................................................................................................................................... 122

5.1.2 Power and Regulation Topology....................................................................................................................123

5.1.3 Digital Regulator and POR............................................................................................................................ 123

5.1.4 Analog Regulator (AREG).............................................................................................................................124

5.2 Modem Operational Modes Summary..........................................................................................................................124

5.2.1 Power modes..................................................................................................................................................124

5.3 Sequence Manager........................................................................................................................................................126

5.3.1 Modes of Operation....................................................................................................................................... 127

5.3.2 Functional Description...................................................................................................................................128

5.4 Dual PAN ID introduction............................................................................................................................................140

5.4.1 Manual and Automatic Modes.......................................................................................................................140

5.4.2 Source Address Matching.............................................................................................................................. 145

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5.4.3 Programming interface...................................................................................................................................146

5.5 Active Promiscuous Mode............................................................................................................................................148

5.5.1 Functional Description...................................................................................................................................149

5.5.2 Special Handling for Broadcast Packets........................................................................................................ 149

5.5.3 Special Handling of Rx Acknowledgement Frames......................................................................................150

5.5.4 Programming Interface.................................................................................................................................. 151

5.6 Clock System................................................................................................................................................................ 151

5.6.1 32MHz Crystal Oscillator.............................................................................................................................. 151

5.6.2 Clock output feature overview.......................................................................................................................152

Chapter 6

Modem: Interrupts

6.1 Introduction...................................................................................................................................................................155

6.2 Modem Interrupt Sources............................................................................................................................................. 155

6.3 Additional Interrupt Mask and Source Descriptions.................................................................................................... 157

6.4 Functional Description..................................................................................................................................................158

6.4.1 Interrupt Status Bit Structure......................................................................................................................... 158

6.4.2 Clearing Interrupts......................................................................................................................................... 159

6.4.3 Timer Interrupts............................................................................................................................................. 159

6.4.4 PLL Unlock Interrupt.....................................................................................................................................160

6.4.5 Filterfail Interrupt...........................................................................................................................................160

6.4.6 RX Watermark Interrupt................................................................................................................................ 161

6.4.7 CCA Interrupt................................................................................................................................................ 161

6.4.8 RX Interrupt................................................................................................................................................... 162

6.4.9 TX Interrupt................................................................................................................................................... 162

6.4.10 Sequencer Interrupt........................................................................................................................................162

6.4.11 Interrupts from Exiting Low Power Modes................................................................................................... 163

6.4.12 Packet Buffer Error Interrupt ........................................................................................................................ 164

Chapter 7

Modem: Timer Information

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7.1 Event Timer Block........................................................................................................................................................165

7.2 Event Timer Time Base................................................................................................................................................ 165

7.3 Setting Current Time.....................................................................................................................................................166

7.4 Reading Current Time...................................................................................................................................................167

7.5 Latching the Timestamp............................................................................................................................................... 167

7.6 Event Timer Comparators.............................................................................................................................................168

7.6.1 Timer Compare Fields................................................................................................................................... 168

7.6.2 Timer Compare-Enable Bits.......................................................................................................................... 168

7.6.3 Timer Interrupt Status Bits.............................................................................................................................169

7.6.4 Timer Interrupt Masks................................................................................................................................... 169

7.6.5 Setting Compare Values.................................................................................................................................170

7.7 Intended Event Timer Usage........................................................................................................................................ 170

7.7.1 Generating Time-Based Interrupts.................................................................................................................171

7.7.2 Using T3CMP to Abort an RX operation...................................................................................................... 171

7.7.3 Using T2CMP or T2PRIMECMP to Trigger Transceiver Operations.......................................................... 172

Chapter 8

MCU-Modem SPI Interface

8.1 SiP Level SPI Pin Connections.....................................................................................................................................175

8.2 Features.........................................................................................................................................................................175

8.3 SPI System Operation...................................................................................................................................................176

8.4 Modem SPI Overview...................................................................................................................................................176

8.4.1 Features.......................................................................................................................................................... 177

8.5 Modem SPI Basic Operation........................................................................................................................................ 177

8.5.1 Modem SPI Pin Definition.............................................................................................................................177

8.5.2 Modem SPI Timing........................................................................................................................................178

8.6 Modem SPI Transactions..............................................................................................................................................180

8.6.1 SPI Control Word...........................................................................................................................................180

8.6.2 Direct Register Write Access (single byte)....................................................................................................181

8.6.3 Direct Register Read Access (single byte).....................................................................................................181

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8.6.4 Direct Register Write Access (multi byte).....................................................................................................182

8.6.5 Direct Register Read Access (multi byte)......................................................................................................183

8.6.6 Indirect Register Write Access (multi byte).................................................................................................. 183

8.6.7 Indirect Register Read Access (multi byte)................................................................................................... 184

8.6.8 Synchronous and Asynchronous Operating Modes.......................................................................................185

8.6.9 Shifting Out IRQSTS1 During Control Word............................................................................................... 186

8.6.10 Packet Buffer..................................................................................................................................................187

8.7 Configuring MCU for Proper SPI Operation................................................................................................................194

8.7.1 DSPI Mode Configuration............................................................................................................................. 195

8.7.2 DSPI Baud Rate ............................................................................................................................................ 195

8.7.3 DSPI Timing Control.....................................................................................................................................196

Chapter 9

Modem: SPI Register Descriptions

9.1 Introduction...................................................................................................................................................................199

9.2 Modem Memory map and register definition............................................................................................................... 200

9.2.1 Interrupt Request Status 1 (Modem_IRQSTS1)............................................................................................ 202

9.2.2 Interrupt Request Status 2 (Modem_IRQSTS2)............................................................................................ 204

9.2.3 Interrupt Request Status 3 (Modem_IRQSTS3)............................................................................................ 205

9.2.4 PHY Control 1 (Modem_PHY_CTRL1)....................................................................................................... 207

9.2.5 PHY Control 2 (Modem_PHY_CTRL2)....................................................................................................... 208

9.2.6 PHY Control 3 (Modem_PHY_CTRL3)....................................................................................................... 209

9.2.7 Receive Frame Length (Modem_RX_FRM_LEN)....................................................................................... 210

9.2.8 PHY Control 4 (Modem_PHY_CTRL4)....................................................................................................... 211

9.2.9 SRC Control (Modem_SRC_CTRL).............................................................................................................212

9.2.10 SRC Address SUM LSB (Modem_SRC_ADDRS_SUM_LSB)...................................................................213

9.2.11 SRC Address SUM MSB (Modem_SRC_ADDRS_SUM_MSB).................................................................213

9.2.12 CCA1 ED FNL (Modem_CCA1_ED_FNL)................................................................................................. 214

9.2.13 Event Timer LSB (Modem_EVENT_TIMER_LSB).................................................................................... 214

9.2.14 Event Timer MSB (Modem_EVENT_TIMER_MSB)..................................................................................215

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9.2.15 Event Timer USB (Modem_EVENT_TIMER_USB)................................................................................... 215

9.2.16 Timestamp LSB (Modem_TIMESTAMP_LSB)...........................................................................................215

9.2.17 Timestamp MSB (Modem_TIMESTAMP_MSB).........................................................................................216

9.2.18 Timestamp USB (Modem_TIMESTAMP_USB)..........................................................................................216

9.2.19 Timer 3 Compare Value LSB (Modem_T3CMP_LSB)................................................................................217

9.2.20 Timer 3 Compare Value MSB (Modem_T3CMP_MSB)..............................................................................217

9.2.21 Timer 3 Compare Value USB (Modem_T3CMP_USB)............................................................................... 217

9.2.22 Timer 2-Prime Compare Value LSB (Modem_T2PRIMECMP_LSB).........................................................218

9.2.23 Timer 2-Prime Compare Value MSB (Modem_T2PRIMECMP_MSB).......................................................218

9.2.24 Timer 1 Compare Value LSB (Modem_T1CMP_LSB)................................................................................218

9.2.25 Timer 1 Compare Value MSB (Modem_T1CMP_MSB)..............................................................................219

9.2.26 Timer 1 Compare Value USB (Modem_T1CMP_USB)............................................................................... 219

9.2.27 Timer 2 Compare Value LSB (Modem_T2CMP_LSB)................................................................................219

9.2.28 Timer 2 Compare Value MSB (Modem_T2CMP_MSB)..............................................................................220

9.2.29 Timer 2 Compare Value USB (Modem_T2CMP_USB)............................................................................... 220

9.2.30 Timer 4 Compare Value LSB (Modem_T4CMP_LSB)................................................................................220

9.2.31 Timer 4 Compare Value MSB (Modem_T4CMP_MSB)..............................................................................221

9.2.32 Timer 4 Compare Value USB (Modem_T4CMP_USB)............................................................................... 221

9.2.33 PLL Integer Value for PAN0 (Modem_PLL_INT0)..................................................................................... 221

9.2.34 PLL Frequency Fractional Value for PAN0 (Modem_PLL_FRAC0_LSB)................................................. 222

9.2.35 PLL Frequency Fractional Value for PAN0 (Modem_PLL_FRAC0_MSB)................................................ 222

9.2.36 PA Power Control (Modem_PA_PWR) (Modem_PA_PWR)...................................................................... 223

9.2.37 Sequence Manager State (Modem_SEQ_STATE)........................................................................................223

9.2.38 Link Quality Indicator (Modem_LQI_VALUE)........................................................................................... 223

9.2.39 RSSI CCA CNT (Modem_RSSI_CCA_CNT).............................................................................................. 224

9.2.40 ASM Control 1 (Modem_ASM_CTRL1)......................................................................................................224

9.2.41 ASM Control 2 (Modem_ASM_CTRL2)......................................................................................................225

9.2.42

ASM Data (Modem_ASM_DATAn).............................................................................................................226

9.2.43 Overwrite Version Number (Modem_OVERWRITE_VER)........................................................................226

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9.2.44 CLK_OUT Control (Modem_CLK_OUT_CTRL)........................................................................................227

9.2.45 Power Modes (Modem_PWR_MODES).......................................................................................................228

9.2.46 IAR Index (Modem_IAR_INDEX)............................................................................................................... 229

9.2.47 IAR Data (Modem_IAR_DATA).................................................................................................................. 230

9.3 Indirect registers memory map and register definition.................................................................................................230

9.3.1 Part Identification (Indirect_Modem_PART_ID)..........................................................................................233

9.3.2 XTAL 32 MHz Trim (Indirect_Modem_XTAL_TRIM)...............................................................................233

9.3.3

MAC PAN ID for PAN0 (Indirect_Modem_MACPANID0n)......................................................................234

9.3.4

MAC Short Address for PAN0 (Indirect_Modem_MACSHORTADDRS0n)..............................................234

9.3.5

MAC Long Address for PAN0 (Indirect_Modem_MACLONGADDRS0n)................................................235

9.3.6 Receive Frame Filter (Indirect_Modem_RX_FRAME_FILTER)................................................................ 235

9.3.7 Frequency Integer for PAN1 (Indirect_Modem_PLL_INT1)........................................................................236

9.3.8

Frequency Fractional Value for PAN1 (Indirect_Modem_PLL_FRAC1n).................................................. 237

9.3.9

Frequency Fractional Value for PAN1 (Indirect_Modem_MACPANID1n).................................................237

9.3.10

MAC Short Address for PAN1 (Indirect_Modem_MACSHORTADDRS1n)..............................................238

9.3.11

MAC Long Address for PAN1 (Indirect_Modem_MACLONGADDRS1n)................................................238

9.3.12 Dual PAN Control (Indirect_Modem_DUAL_PAN_CTRL)........................................................................239

9.3.13 Channel Frequency Dwell Time (Indirect_Modem_DUAL_PAN_DWELL)...............................................240

9.3.14 Dual PAN Status (Indirect_Modem_DUAL_PAN_STS)..............................................................................240

9.3.15 Clear Channel Assessment 1 Threshold (Indirect_Modem_CCA1_THRESH)............................................ 241

9.3.16 Clear Channel Assessment / ED Offset Computation (Indirect_Modem_CCA1_ED_OFFSET_COMP)....242

9.3.17 LQI Offset Computation (Indirect_Modem_LQI_OFFSET_COMP)........................................................... 242

9.3.18 CCA Control (Indirect_Modem_CCA_CTRL)............................................................................................. 242

9.3.19 Clear Channel Assessment 2 Threshold Peak Compare (Indirect_Modem_CCA2_CORR_PEAKS)..........243

9.3.20 Clear Channel Assessment 2 Threshold (Indirect_Modem_CCA2_THRESH)............................................ 244

9.3.21 TMR PRESCALE (Indirect_Modem_TMR_PRESCALE)...........................................................................244

9.3.22 GPIO Data (Indirect_Modem_GPIO_DATA)...............................................................................................245

9.3.23 GPIO Direction Control (Indirect_Modem_GPIO_DIR).............................................................................. 246

9.3.24 GPIO Pullup Enable (Indirect_Modem_GPIO_PUL_EN)............................................................................247

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9.3.25 GPIO Pullup Select (Indirect_Modem_GPIO_SEL)..................................................................................... 249

9.3.26 GPIO Drive Strength (Indirect_Modem_GPIO_DS).....................................................................................250

9.3.27 Antenna Control (Indirect_Modem_ANT_PAD_CTRL)..............................................................................251

9.3.28 Miscellaneous Pad Control (Indirect_Modem_MISC_PAD_CTRL)............................................................253

9.3.29 RX_BYTE_COUNT (Indirect_Modem_RX_BYTE_COUNT)....................................................................253

9.3.30 RX_WTR_MARK (Indirect_Modem_RX_WTR_MARK).......................................................................... 254

9.3.31 TXDELAY (Indirect_Modem_TXDELAY)................................................................................................. 254

9.3.32 ACKDELAY (Indirect_Modem_ACKDELAY)........................................................................................... 255

9.3.33 Antenna AGC and FAD Control (Indirect_Modem_ANT_AGC_CTRL).................................................... 255

9.3.34 LPPS_CTRL (Indirect_Modem_LPPS_CTRL)............................................................................................ 256

9.3.35 RSSI (Indirect_Modem_RSSI)...................................................................................................................... 257

9.3.36 XTAL Control (Indirect_Modem_XTAL_CTRL)........................................................................................ 258

Chapter 10

MCU: Chip Configuration

10.1 Introduction...................................................................................................................................................................259

10.2 Core modules................................................................................................................................................................ 259

10.2.1 ARM Cortex-M4 Core Configuration............................................................................................................259

10.2.2 Nested Vectored Interrupt Controller (NVIC) Configuration........................................................................261

10.2.3 Asynchronous Wake-up Interrupt Controller (AWIC) Configuration...........................................................266

10.2.4 JTAG Controller Configuration.....................................................................................................................268

10.3 System modules............................................................................................................................................................ 268

10.3.1 SIM Configuration......................................................................................................................................... 268

10.3.2 System Mode Controller (SMC) Configuration.............................................................................................269

10.3.3 PMC Configuration........................................................................................................................................270

10.3.4 Low-Leakage Wake-up Unit (LLWU) Configuration...................................................................................270

10.3.5 MCM Configuration...................................................................................................................................... 272

10.3.6 Crossbar-Light Switch Configuration............................................................................................................273

10.3.7 Peripheral Bridge Configuration....................................................................................................................274

10.3.8 DMA request multiplexer configuration........................................................................................................275

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10.3.9 DMA Controller Configuration..................................................................................................................... 278

10.3.10 External Watchdog Monitor (EWM) Configuration......................................................................................279

10.3.11 Watchdog Configuration................................................................................................................................281

10.4 Clock modules.............................................................................................................................................................. 282

10.4.1 MCG Configuration....................................................................................................................................... 282

10.4.2 OSC Configuration........................................................................................................................................ 283

10.4.3 RTC OSC configuration.................................................................................................................................284

10.5 Memories and memory interfaces.................................................................................................................................284

10.5.1 Flash Memory Configuration.........................................................................................................................284

10.5.2 Flash Memory Controller Configuration....................................................................................................... 287

10.5.3 SRAM Configuration.....................................................................................................................................289

10.5.4 System Register File Configuration...............................................................................................................291

10.5.5 VBAT Register File Configuration................................................................................................................292

10.5.6 EzPort Configuration..................................................................................................................................... 293

10.6 Security......................................................................................................................................................................... 294

10.6.1 CRC Configuration........................................................................................................................................ 294

10.6.2 MMCAU Configuration.................................................................................................................................295

10.6.3 RNG Configuration........................................................................................................................................296

10.6.4 DryIce (tamper detect and secure storage) configuration.............................................................................. 296

10.7 Analog...........................................................................................................................................................................296

10.7.1 16-bit SAR ADC Configuration.................................................................................................................... 296

10.7.2 CMP Configuration........................................................................................................................................301

10.8 Timers........................................................................................................................................................................... 302

10.8.1 PDB Configuration........................................................................................................................................ 302

10.8.2 FlexTimer Configuration............................................................................................................................... 304

10.8.3 PIT Configuration.......................................................................................................................................... 308

10.8.4 Low-power timer configuration.....................................................................................................................309

10.8.5 CMT Configuration........................................................................................................................................310

10.8.6 RTC configuration......................................................................................................................................... 311

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10.9 Communication interfaces............................................................................................................................................ 313

10.9.1 Universal Serial Bus (USB) FS Subsystem................................................................................................... 313

10.9.2 SPI configuration........................................................................................................................................... 319

10.9.3 I2C Configuration.......................................................................................................................................... 322

10.9.4 UART Configuration..................................................................................................................................... 322

10.9.5 I2S configuration............................................................................................................................................324

10.10 Human-machine interfaces........................................................................................................................................... 328

10.10.1 GPIO configuration........................................................................................................................................328

Chapter 11

MCU: Memory Map

11.1 Introduction...................................................................................................................................................................329

11.2 System memory map.....................................................................................................................................................329

11.2.1 Aliased bit-band regions................................................................................................................................ 330

11.3 System memory map.....................................................................................................................................................331

11.3.1 Alternate Non-Volatile IRC User Trim Description......................................................................................332

11.4 SRAM memory map.....................................................................................................................................................333

11.5 Peripheral bridge (AIPS-Lite) memory map.................................................................................................................333

11.5.1 Read-after-write sequence and required serialization of memory operations................................................333

11.5.2 Peripheral Bridge 0 (AIPS-Lite 0) Memory Map.......................................................................................... 334

11.6 Private Peripheral Bus (PPB) memory map..................................................................................................................337

Chapter 12

MCU: Clock Distribution

12.1 Introduction...................................................................................................................................................................339

12.2 Programming model......................................................................................................................................................339

12.3 High-Level device clocking diagram............................................................................................................................339

12.4 Clock definitions...........................................................................................................................................................340

12.4.1 Device clock summary...................................................................................................................................341

12.5 Internal clocking requirements..................................................................................................................................... 342

12.5.1 Clock divider values after reset......................................................................................................................343

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12.5.2 VLPR mode clocking.....................................................................................................................................343

12.6 Clock Gating.................................................................................................................................................................344

12.7 Module clocks...............................................................................................................................................................344

12.7.1 PMC 1-kHz LPO clock..................................................................................................................................346

12.7.2 WDOG clocking............................................................................................................................................ 346

12.7.3 Debug trace clock...........................................................................................................................................346

12.7.4 PORT digital filter clocking...........................................................................................................................347

12.7.5 LPTMR clocking............................................................................................................................................347

12.7.6 USB FS OTG Controller clocking.................................................................................................................348

12.7.7 UART clocking..............................................................................................................................................348

12.7.8 I2S/SAI clocking............................................................................................................................................349

Chapter 13

MCU: Reset and Boot

13.1 Introduction...................................................................................................................................................................351

13.2 Reset..............................................................................................................................................................................352

13.2.1 Power-on reset (POR).................................................................................................................................... 352

13.2.2 System reset sources...................................................................................................................................... 352

13.2.3 MCU Resets................................................................................................................................................... 356

13.2.4 Reset Pin ....................................................................................................................................................... 358

13.2.5 Debug resets...................................................................................................................................................358

13.3 Boot...............................................................................................................................................................................359

13.3.1 Boot sources...................................................................................................................................................359

13.3.2 Boot options................................................................................................................................................... 360

13.3.3 FOPT boot options.........................................................................................................................................360

13.3.4 Boot sequence................................................................................................................................................ 361

Chapter 14

MCU: Power Management

14.1 Introduction...................................................................................................................................................................363

14.2 Power Modes Description.............................................................................................................................................363

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14.3 Entering and exiting power modes............................................................................................................................... 365

14.4 Power mode transitions.................................................................................................................................................366

14.5 Power modes shutdown sequencing............................................................................................................................. 367

14.6 Module Operation in Low Power Modes......................................................................................................................368

14.7 Clock Gating.................................................................................................................................................................371

Chapter 15

MCU: Security

15.1 Introduction...................................................................................................................................................................373

15.2 Flash Security............................................................................................................................................................... 373

15.3 Security Interactions with other Modules.....................................................................................................................374

15.3.1 Security Interactions with EzPort.................................................................................................................. 374

15.3.2 Security Interactions with Debug...................................................................................................................374

Chapter 16

MCU: Debug

16.1 Introduction...................................................................................................................................................................375

16.1.1 References......................................................................................................................................................377

16.2 The Debug Port.............................................................................................................................................................377

16.2.1 JTAG-to-SWD change sequence................................................................................................................... 378

16.2.2 JTAG-to-cJTAG change sequence.................................................................................................................378

16.3 Debug Port Pin Descriptions.........................................................................................................................................379

16.4 System TAP connection................................................................................................................................................379

16.4.1 IR Codes.........................................................................................................................................................379

16.5 JTAG status and control registers.................................................................................................................................380

16.5.1 MDM-AP Control Register............................................................................................................................381

16.5.2 MDM-AP Status Register.............................................................................................................................. 383

16.6 Debug Resets................................................................................................................................................................ 384

16.7 AHB-AP........................................................................................................................................................................385

16.8 ITM............................................................................................................................................................................... 385

16.9 Core Trace Connectivity...............................................................................................................................................386

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16.10 Embedded Trace Macrocell v3.5 (ETM)......................................................................................................................387

16.11 TPIU..............................................................................................................................................................................387

16.12 DWT............................................................................................................................................................................. 387

16.13 Debug in Low Power Modes........................................................................................................................................ 388

16.13.1 Debug Module State in Low Power Modes...................................................................................................389

16.14 Debug & Security......................................................................................................................................................... 389

Chapter 17

MCU: Signal Multiplexing and Signal Descriptions

17.1 Introduction...................................................................................................................................................................391

17.2 Signal Multiplexing Integration....................................................................................................................................391

17.2.1 Port control and interrupt module features.................................................................................................... 392

17.2.2 PCRn reset values for port A......................................................................................................................... 392

17.2.3 Clock gating................................................................................................................................................... 392

17.2.4 Signal multiplexing constraints......................................................................................................................392

17.3 Module Signal Description Tables................................................................................................................................393

17.3.1 Core Modules.................................................................................................................................................393

17.3.2 System Modules.............................................................................................................................................394

17.3.3 Clock Modules............................................................................................................................................... 394

17.3.4 Memories and Memory Interfaces................................................................................................................. 394

17.3.5 Security Modules........................................................................................................................................... 395

17.3.6 Analog............................................................................................................................................................395

17.3.7 Timer Modules...............................................................................................................................................396

17.3.8 Communication Interfaces............................................................................................................................. 397

17.3.9 Human-Machine Interfaces (HMI)................................................................................................................ 399

Chapter 18

MCU: Port control and interrupts (PORT)

18.1 Introduction...................................................................................................................................................................401

18.2 Overview.......................................................................................................................................................................401

18.2.1 Features.......................................................................................................................................................... 401

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18.2.2 Modes of operation........................................................................................................................................ 402

18.3 External signal description............................................................................................................................................403

18.4 Detailed signal description............................................................................................................................................403

18.5 Memory map and register definition.............................................................................................................................403

18.5.1

Pin Control Register n (PORTx_PCRn).........................................................................................................410

18.5.2

Global Pin Control Low Register (PORTx_GPCLR)....................................................................................413

18.5.3

Global Pin Control High Register (PORTx_GPCHR)...................................................................................413

18.5.4

Interrupt Status Flag Register (PORTx_ISFR).............................................................................................. 414

18.5.5

Digital Filter Enable Register (PORTx_DFER).............................................................................................414

18.5.6

Digital Filter Clock Register (PORTx_DFCR)..............................................................................................415

18.5.7

Digital Filter Width Register (PORTx_DFWR)............................................................................................ 415

18.6 Functional description...................................................................................................................................................416

18.6.1 Pin control......................................................................................................................................................416

18.6.2 Global pin control.......................................................................................................................................... 417

18.6.3 External interrupts..........................................................................................................................................417

18.6.4 Digital filter....................................................................................................................................................418

Chapter 19

MCU: System Integration Module (SIM)

19.1 Introduction...................................................................................................................................................................421

19.1.1 Features.......................................................................................................................................................... 421

19.2 Memory map and register definition.............................................................................................................................422

19.2.1 System Options Register 1 (SIM_SOPT1).................................................................................................... 423

19.2.2 SOPT1 Configuration Register (SIM_SOPT1CFG)......................................................................................425

19.2.3 System Options Register 2 (SIM_SOPT2).................................................................................................... 426

19.2.4 System Options Register 4 (SIM_SOPT4).................................................................................................... 428

19.2.5 System Options Register 5 (SIM_SOPT5).................................................................................................... 431

19.2.6 System Options Register 7 (SIM_SOPT7).................................................................................................... 432

19.2.7 System Device Identification Register (SIM_SDID).....................................................................................433

19.2.8 System Clock Gating Control Register 4 (SIM_SCGC4)..............................................................................435

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19.2.9 System Clock Gating Control Register 5 (SIM_SCGC5)..............................................................................437

19.2.10 System Clock Gating Control Register 6 (SIM_SCGC6)..............................................................................438

19.2.11 System Clock Gating Control Register 7 (SIM_SCGC7)..............................................................................441

19.2.12 System Clock Divider Register 1 (SIM_CLKDIV1).....................................................................................442

19.2.13 System Clock Divider Register 2 (SIM_CLKDIV2).....................................................................................444

19.2.14 Flash Configuration Register 1 (SIM_FCFG1)............................................................................................. 444

19.2.15 Flash Configuration Register 2 (SIM_FCFG2)............................................................................................. 447

19.2.16 Unique Identification Register High (SIM_UIDH)....................................................................................... 448

19.2.17 Unique Identification Register Mid-High (SIM_UIDMH)............................................................................448

19.2.18 Unique Identification Register Mid Low (SIM_UIDML)............................................................................. 449

19.2.19 Unique Identification Register Low (SIM_UIDL)........................................................................................ 449

19.3 Functional description...................................................................................................................................................449

Chapter 20

MCU: Reset Control Module (RCM)

20.1 Introduction...................................................................................................................................................................451

20.2 Reset memory map and register descriptions............................................................................................................... 451

20.2.1 System Reset Status Register 0 (RCM_SRS0).............................................................................................. 452

20.2.2 System Reset Status Register 1 (RCM_SRS1).............................................................................................. 453

20.2.3 Reset Pin Filter Control register (RCM_RPFC)............................................................................................ 455

20.2.4 Reset Pin Filter Width register (RCM_RPFW)............................................................................................. 456

20.2.5 Mode Register (RCM_MR)........................................................................................................................... 457

Chapter 21

MCU: System Mode Controller (SMC)

21.1 Introduction...................................................................................................................................................................459

21.2 Modes of operation....................................................................................................................................................... 459

21.3 Memory map and register descriptions.........................................................................................................................461

21.3.1 Power Mode Protection register (SMC_PMPROT).......................................................................................462

21.3.2 Power Mode Control register (SMC_PMCTRL)...........................................................................................463

21.3.3 VLLS Control Register (SMC_VLLSCTRL)................................................................................................465

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21.3.4 Power Mode Status register (SMC_PMSTAT)............................................................................................. 466

21.4 Functional description...................................................................................................................................................466

21.4.1 Power mode transitions..................................................................................................................................467

21.4.2 Power mode entry/exit sequencing................................................................................................................ 469

21.4.3 Run modes......................................................................................................................................................470

21.4.4 Wait modes.................................................................................................................................................... 472

21.4.5 Stop modes.....................................................................................................................................................473

21.4.6 Debug in low power modes........................................................................................................................... 476

Chapter 22

MCU: Power Management Controller (PMC)

22.1 Introduction...................................................................................................................................................................479

22.2 Features.........................................................................................................................................................................479

22.3 Low-voltage detect (LVD) system................................................................................................................................479

22.3.1 LVD reset operation.......................................................................................................................................480

22.3.2 LVD interrupt operation.................................................................................................................................480

22.3.3 Low-voltage warning (LVW) interrupt operation......................................................................................... 480

22.4 I/O retention..................................................................................................................................................................481

22.5 Memory map and register descriptions.........................................................................................................................481

22.5.1 Low Voltage Detect Status And Control 1 register (PMC_LVDSC1).......................................................... 482

22.5.2 Low Voltage Detect Status And Control 2 register (PMC_LVDSC2).......................................................... 483

22.5.3 Regulator Status And Control register (PMC_REGSC)................................................................................484

Chapter 23

MCU: Low-Leakage Wakeup Unit (LLWU)

23.1 Introduction...................................................................................................................................................................487

23.1.1 Features.......................................................................................................................................................... 487

23.1.2 Modes of operation........................................................................................................................................ 488

23.1.3 Block diagram................................................................................................................................................489

23.2 LLWU signal descriptions............................................................................................................................................ 490

23.3 Memory map/register definition................................................................................................................................... 491

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23.3.1 LLWU Pin Enable 1 register (LLWU_PE1)..................................................................................................492

23.3.2 LLWU Pin Enable 2 register (LLWU_PE2)..................................................................................................493

23.3.3 LLWU Pin Enable 3 register (LLWU_PE3)..................................................................................................494

23.3.4 LLWU Pin Enable 4 register (LLWU_PE4)..................................................................................................495

23.3.5 LLWU Module Enable register (LLWU_ME).............................................................................................. 496

23.3.6 LLWU Flag 1 register (LLWU_F1)...............................................................................................................498

23.3.7 LLWU Flag 2 register (LLWU_F2)...............................................................................................................499

23.3.8 LLWU Flag 3 register (LLWU_F3)...............................................................................................................501

23.3.9 LLWU Pin Filter 1 register (LLWU_FILT1)................................................................................................ 503

23.3.10 LLWU Pin Filter 2 register (LLWU_FILT2)................................................................................................ 504

23.3.11 LLWU Reset Enable register (LLWU_RST).................................................................................................505

23.4 Functional description...................................................................................................................................................506

23.4.1 LLS mode.......................................................................................................................................................506

23.4.2 VLLS modes.................................................................................................................................................. 506

23.4.3 Initialization................................................................................................................................................... 507

Chapter 24

MCU: Miscellaneous Control Module (MCM)

24.1 Introduction...................................................................................................................................................................509

24.1.1 Features.......................................................................................................................................................... 509

24.2 Memory map/register descriptions............................................................................................................................... 509

24.2.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)..................................................................510

24.2.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC).............................................................. 510

24.2.3 Crossbar Switch (AXBS) Control Register (MCM_PLACR)....................................................................... 511

Chapter 25

MCU: Crossbar Switch Lite (AXBS-Lite)

25.1 Introduction...................................................................................................................................................................513

25.1.1 Features.......................................................................................................................................................... 513

25.2 Memory Map / Register Definition...............................................................................................................................514

25.3 Functional Description..................................................................................................................................................514

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