Broadcom PEX 8696 Silicon Revisions and Errata List User guide

PEX8696

Silicon Revisions and Errata List

CONFIDENTIAL PROPRIETARY INFORMATION

NDA REQUIRED

Version 1.5

April 2013

Website:

www.plxtech.com

Technical Support:

www.plxtech.com/support

April 26, 2013

PEX 8696 Errata v1.5

A. Affected Silicon Revision

This document details Errata for the following silicon:

Product

Revision

Description

Status

PEX 8696

AA

96-Lane; 24-Port PCIe Switch

Production

B. Device Documentation Version

The following documentation is the baseline functional description of the silicon:

Document

Version

Description

Publication Date

PEX 8696 Data Book

1.0

Data Book

November 2009

C. Errata Documentation Revision History

Revision

Publication Date

Description

0.1

July 2009

 Initial publication of the Errata list

0.2

July 2009

 Added Errata 2 and 3

0.3

September 2009

 Added Errata 4, 5, and 6

0.4

October 2009

 Added Errata 7, 8, 9, 10 and 11

 Added Caution Section with items i, Error!

Reference source not found., iii, iv, v and vi

1.0

December 2009

 Added Errata 12

 Added clarification to Caution ii

1.1

October 2010

 Added Errata E.13

1.2

May 2011

 Added Errata 14, 15, and 16

1.3

March 2012

 Added Errata 17

 Added Caution vii

1.4

March 2012

 Added Errata 18

1.5

April 2013

 Modified register in workaround #3 for errata E.18 - from

236h[3:0] to 234h[19:16]

 Added “and the lanes are not reversed” to caution i

D. Errata Summary

#

Description

Risk

Category

Silicon Rev

Affected

1

Sticky Registers for a Given Virtual Switch, are not Reset with

VS_PERST#

Low

AA

2

Incorrect Value on Register 0xC8 on the NT Virtual Side When NT

P2P Mode is Enabled

Low

AA

3

EEPROM Does Not Load on De-assertion of VS_PERST#

Low

AA

4

Incorrect GPIO control in virtual switch mode

Low

AA

PEX 8696 Errata v1.5

#

Description

Risk

Category

Silicon Rev

Affected

5

Uninhibited Memory mapped access to Port 0 registers from the

redundant management port

Low

AA

6

Logs for Replay timeout, replay number rollover and DLLP errors are

not logged for the Legacy NT connection

Low

AA

7

NT P2P Bridge Command Register and NT P2P Virtual Endpoint

BAR3 Issue

Low

AA

8

Device Status and Control 2 Register ARI Forwarding Enable bit is

read as “0”

Low

AA

9

NT Port Virtual-to-Link Doorbell MSI Errata

Low

AA

10

Analog Loopback Master Mode PRBS Support

Low

AA

11

Analog Loopback Slave Mode Support

Low

AA

12

SHP_GPIO[42:33] Pins are Input Only When Virtual Switch Mode is

Enabled

Low

AA

13

LTSSM doesn’t transition to Gen1 speed for PLX device specific port

disable condition

Low

AA

14

AC JTAG Functionality Does not Work

Low

AA

15

RAM ECC Error Generates Continuous Error Message

Low

AA

16

Does Not Clear the ECC Error Status Register Properly

Low

AA

17

Memory Read TLPs with Relax Ordering (RO) attribute gets

completion timeout under extreme completion credit starvation

condition

Low

AA

18

Incorrect TCB Capture of Training Sets

Low

AA

E. Caution Summary

#

Description

Risk

Category

Silicon Rev

Affected

i

A link will not come up if receivers are detected on a few lanes that

do not exit Electrical Idle in polling

Low

AA

ii

The Default Value of the Class Code Register (0x08) in the NT-

Virtual Port is Incorrect Under Certain Conditions

Low

AA

iii

The MSI Mask register (0x58h) is implemented according to the

Multiple Message Enable field (0x48h[22:20]) rather than the Multiple

Low

AA

PEX 8696 Errata v1.5

#

Description

Risk

Category

Silicon Rev

Affected

Message Capable field 0x48h[22:20])

iv

Incorrect Completer ID on ACS Source Validation Error

Low

AA

v

The NT-Link Port MSI Mask and MSI Pending registers (0x58h,

0x5Ch) cannot be disabled EEPROM/I2C

Low

AA

vi

If Serial Hot Plug is implemented with MRL disabled (MRL Present

bit (0x7Ch[2]) is cleared by EEPROM/I2C), after Fundamental Reset

the PEX 8696 Serial Hot Plug controller unconditionally initiates the

slot power-up sequence (by asserting the I/O Expander PWREN,

PWRLED#, CLKEN# outputs and de-asserting I/O Expander

PERST# output)

Low

AA

vii

When Virtual Switch Mode is Enabled, VS_PERST# Does Not

Initialize the Serial Hot-Plug Register

Low

AA

PEX 8696 Errata v1.5

1. Sticky Registers for a Given Virtual Switch, are not Reset with

VS_PERST#

Risk Category: Low

Silicon Revisions Affected: AA

Description

VS_PERST# pins do not clear advanced error capability sticky registers. All registers in

the advanced error capability are sticky registers

Solution/Workaround

Sofware will need to write to the advanced error capability registers to clear them if

VS_PERST# is given to the device.

Impact

Customers planning to use the Multi-root function of the Switch and use VS_PERST# to

reset the device will need to write to Error handler registers to clear the values after

VS_PERST# is asserted.

2. Incorrect Value on Register 0xC8 on the NT Virtual Side When NT

P2P Mode is Enabled

Risk Category: Low

Silicon Revisions Affected: AA

Description

In the NT P2P mode, the default value on register 0xC8 on the NT virtual side is

incorrect (0001_0009h).

Solution/Workaround

EEPROM can load the correct value of 0038_0009h to register 0xC8. The correct value

can also be loaded using the I

2

C interface.

Impact

When using the NT P2P mode, the default value on register 0xC8 is incorrect.

PEX 8696 Errata v1.5

3. EEPROM Does Not Load on De-assertion of VS_PERST#

Risk Category: Low

Silicon Revisions Affected: AA

Description

Serial EEPROM load on VS_PERST# deassertion does not work

Solution/Workaround

The EEPROM can be loaded at PEX_PERST# deassertion but not at VS_PERST#

deassertion. The EEPROM can also be loaded using hot reset to the Virtual Switch.

Impact

Serial EEPROM load does not work with VS_PERST#. Because the EEPROM loads

properly for the whole device after PEX_PERST# deasssertion, the EEPROM should

load the Virtual Switch registers after VS_PERST# is deasserted.

4. Incorrect GPIO control in virtual switch mode

Risk Category: Low

Silicon Revisions Affected: AA

Description

When the following conditions are true in the Switch:

 Virtual Switch mode is enabled

 Three or more virtual switches are configured (VS0, VS1 and VS2)

 Three or more GPIOs are assigned to Virtual Switch 2 (VS2)

The direction for the third GPIO is controlled by the second GPIO output enable.

Solution/Workaround

1. Program both the second and third GPIOs to be the same type (either inputs or

outputs)

2. Do not assign more than two GPIOs to VS2. If more than two GPIOs are

required, select a different VS

Impact

The third GPIO assigned to VS2 may not be usable since they are both controlled by the

second GPIO output enable

PEX 8696 Errata v1.5

5. Uninhibited Memory mapped access to Port 0 registers from the

redundant management port

Risk Category: Low

Silicon Revisions Affected: AA

Description

When Virtual Switch Mode (VS) is enabled, there can be an active (primary)

management port as well as a redundant management port. The primary management

port has access privileges to ALL configuration registers in the device, including registers

for ports in other hierarchies, through memory mapped accesses. The redundant

management port only has access privileges for those ports within its own VS hierarchy

including the management register for upgrading itself to the primary management port.

However, the switch erroneously provides unrestricted access to the first 4KB of memory

mapped register configuration space (Port 0 CSRs) to the redundant management port.

Solution/Workaround

1. Include Port 0 as part of the redundant management port hierarchy

2. Unless management port failover is needed, do not enable a redundant

management port

Impact

Unauthorized access to Port 0 CSR space could be enabled to the redundant

management port.

6. Logs for Replay timeout, replay number rollover and DLLP errors

are not logged for the Legacy NT connection

Risk Category: Low

Silicon Revisions Affected: AA

Description

The switch supports the Non-Transparency (NT) function in two modes:

1. Legacy NT

2. NT P2P

When Legacy NT mode is enabled, the following conditions are not logged internally on

the NT Link side:

 Replay timeout

 Replay number rollover

PEX 8696 Errata v1.5

 DLLP errors

The NT P2P mode is not affected; that is, the NT P2P mode logs the above error

conditions properly.

Solution/Workaround

Monitor the Bad TLP, Bad DLLP and Receiver Error logs instead; these are logged

correctly on the switch.

Impact

Error logs which can assist in monitoring the link stability for the Legacy NT link

connection are not updated. Although DLLP and Link errors rarely occur in a stable link

connection, they can cause Replay timeouts and replay-number rollover in unstable links

which can result in a link retrain.

The error conditions described above are properly logged on the NT Link side when the

NT P2P mode is used.

7. NT P2P Bridge Command Register and NT P2P Virtual Endpoint

BAR3 Issue

Risk Category: Low

Silicon Revisions Affected: AA

Description

When the Non-Transparent function is enabled and NT P2P mode is used, the NT Virtual

endpoint’s BAR 3 Register (0x1Ch) cannot be read when Port 0, 4, 8, 12, 16 or 20 are

made the NT Port. Instead, a read to that register incorrectly returns the value of the

P2P Bridge Secondary Status I/O Base and Limit Register (also mapped as 0x1Ch) in

front of the NT endpoint. Furthermore, writes to the NT endpoint Virtual Command

register (0x04h) are also mirrored to the P2P Bridge Command Register (0x04h).

Solution/Workaround

1. Use the NT Legacy mode instead and do not enable NT P2P mode if using x16

ports an BAR3

2. If not using x16 wide ports, do not use Ports 0, 4, 8, 12, 16 or 20 as the NT port

Impact

BIOS and/or OS Read requests directed to BAR3 will return incorrect values during

enumeration, which can potentially result in BIOS enumeration issues. A write to the NT

Virtual endpoint’s Command Register (0x04h) results in a write to offset 0x04h of both

the NT Virtual endpoint and it corresponding P2P bridge.

PEX 8696 Errata v1.5

8. Device Status and Control 2 Register ARI Forwarding Enable bit

is read as “0”

Risk Category: Low

Silicon Revisions Affected: AA

Description

Device Status and Control 2 Register (0x90[5]) ARI enable bit is software writeable but it

will always read back as 0.

Solution/Workaround

Device Capability 2 Register (0x8C[21]) can be alternatively used to determine if the ARI

is enabled.

Impact

ARI is fully functional, if enabled, the limitation is that the software cannot read the ARI

enable bit to determine if it was successful in setting the bit.

9. NT Port Virtual-to-Link Doorbell MSI Errata

Risk Category: Low

Silicon Revisions Affected: AA

Description

The NT-Link port MSI Mask register bit [2] should be writeable; however, it is not

writeable in the PEX 8696.

If the NT-Link host enables two MSI vectors (by writing value 001b to the Multiple

Message Enable field (0x48h[22:20])), rather than enabling all 4 of the requested vectors

(as defined by the value of the Multiple Message Capable field (0x48h[22:20])), the MSI

Data within the MSI Virtual-to-Link Doorbell packet is incorrect.

Solution/Workaround

The MSI host must either enable all 4 MSI vectors (one for each interrupt source), or

enable 1 MSI vector for all interrupt sources.

PEX 8696 Errata v1.5

Impact

If the host enables 2 MSI vectors, the NT-Link port side is supposed to modify only the

least significant bit (0) of the MSI Data within the MSI Message TLP. However the PEX

8696 changes the two least significant bits. Therefore MSI TLPs for NT Port Virtual-to-

Link Doorbell interrupts will contain incorrect MSI Data in bits [1] of the payload.

10. Analog Loopback Master Mode PRBS Support

Risk Category: Low

Silicon Revisions Affected: AA

Description

If the PEX8696 is configured to be Analog Loop Back Master then PRBS pattern cannot

be used for checking the data path integrity unless the following bit is set on the Physical

Layer Safety Bits register (0x22C[1]=1).

Solution/Workaround

1. Use UTP pattern in the Analog Loop Back Master Mode

2. If PRBS is to be used, set the following bit is set on the Physical Layer Safety Bits

register (0x22C[1]=1)

Impact

None

11. Analog Loopback Slave Mode Support

Risk Category: Low

Silicon Revisions Affected: AA

Description

Analog Loop Back Slave Mode is non-functional for asynchronous systems. For

synchronous systems, analog loop back slave mode is functional when the following bit

is set on the Physical Layer Safety Bits (0x22C[1]=1).

Solution/Workaround

1. For Asynchronous systems, use Line Loop Back instead

2. For Synchronous systems, set the following bit is set on the Physical Layer Safety

Bits register (0x22C[1]=1)

PEX 8696 Errata v1.5

Impact

Analog Loop Back Slave Mode cannot be used in Asynchronous Systems

12. SHP_GPIO[42:33] Pins are Input Only When Virtual Switch Mode

is Enabled

Risk Category: Low

Silicon Revisions Affected: AA

Description

The SHP_GPIO[42:33] pins can be programmed as either input or output when the

Switch is configured in Base Mode. However, when the Switch is configured in Virtual

Switch Mode, the SHP_GPIO[42:33] pins can only be used as input pins.

Solution/Workaround

Do not use the SHP_GPIO[42:33] pins as output pins in Virtual Switch Mode. Instead,

use any of the other 33 available GPIO pins as output pins.

Impact

Only 33 GPIO pins can be used as outputs when Virtual Switch Mode is enabled. This

does not affect the functionality of the SHP_PERST# pins.

13. LTSSM doesn’t transition to Gen1 speed for PLX device specific

port disable condition

Risk Category: Low

Silicon Revisions Affected: AA

Description

PLX device specific port disable conditions are

1. Egress credit timeout

2. Fencing mode bringing down the upstream port

3. NT Link Down condition when transparent domain gets hot-reset (non default

mode)

If a Port is in Gen2 Link up state and any of the above events happens, the link is

brought down immediately by transitioning the port LTSSM from L0 to Detect.Quiet state

without going through the Recovery state. These PLX specific port disable events don’t

PEX 8696 Errata v1.5

hold the LTSSM in Detect.Quiet state long enough for the Speed change from Gen2 to

Gen1 to occur. LTSSM stays in Gen2 speed during Polling state when the link is re-

trained.

Solution/Workaround

1. Program Port CSR offset 224h, bit[11:10] to non-zero value. This holds the

LTSSM in Detect.Quiet state for at least 4ms.

2. The port operates in Gen1 speed.

Impact

The Port doesn’t link-up.

14. AC JTAG Functionality Does not Work

Risk Category: Low

Silicon Revisions Affected: AA

Description

The level output on the RX pins used by the AC JTAG instructions is not stable and

consequently it is not latched by the boundary scan chain. The TX pins does not toggle

at the right cycle in AC JTAG mode.

Solution/Workaround

1. Bring up the links and check the widths using the PEX_PORT_GOOD# pins. The

link width and speed can also be checked using I2C.

2. The external device can put the switch into loopback mode and then check the

integrity of the link. The external device connected to the switch can also be put in

loopback mode using the switch and the link integrity can be checked using PRBS

or other user-programmable test patterns.

Impact

The RX/TX pins of the switch cannot be used with AC JTAG instructions.

15. RAM ECC Error Generates Continuous Error Message

Risk Category: Low

Silicon Revisions Affected: AA

PEX 8696 Errata v1.5

Description

If the RAM 1-bit ECC error counter overflows and correctable error message signaling is

enabled, the switch generates continuous correctable error messages after the overflow

event. If the RAM detects 2-bit ECC error and uncorrectable error message signaling is

enabled, the switch generates continuous uncorrectable error messages if the error

detection happens in downstream station(s).

Solution/Workaround

1. Use interrupt signaling for RMA ECC error detection.

Impact

Unwanted error message signaling

16. Does Not Clear the ECC Error Status Register Properly

Risk Category: Low

Silicon Revisions Affected: AA

Description

The switch should clear the ECC error status register as defined in the datasheet.

Writing 1 to a bit position should clear the corresponding error status bit. A design bug

clears unrelated ECC error status bit in the same register offset and does not clear the

intended ECC error status bit.

Solution/Workaround

1. Use the following table to clear the intended ECC error status bit. The first column

shows the bit which is written 1 into, the second column shows which bit in the

register is actually cleared.

700h

WrOneClearBit

PLX Error Status Register 1

[1]

2

Debug triggered interrupt assertion

[2]

0

Station0 Packet Link List RAM soft error counter overflow detected

[3]

1

Station1 Packet Link List RAM soft error counter overflow detected

[4]

2

Station2 Packet Link List RAM soft error counter overflow detected

[5]

2

Station3 Packet Link List RAM soft error counter overflow detected

[6]

2

Station4 Packet Link List RAM soft error counter overflow detected

[7]

2

Station5 Packet Link List RAM soft error counter overflow detected

[8]

24

Station0 Header RAM soft error counter overflow detected

PEX 8696 Errata v1.5

[9]

25

Station1 Header RAM soft error counter overflow detected

[10]

26

Station2 Header RAM soft error counter overflow detected

[11]

26

Station3 Header RAM soft error counter overflow detected

[12]

26

Station4 Header RAM soft error counter overflow detected

[13]

26

Station5 Header RAM soft error counter overflow detected

[14]

6

Destination Queue link list ram soft error counter overflow detected

[15]

8

Source Queue link list ram soft error error counter overflow detected

[16]

10

Retry buffer soft error counter overflow detected

[17]

6

TIC link list RAM soft error counter overflow detected

[18]

18

Source Queue link list ram2 soft error error counter overflow detected

[19]

19

Destination Queue Data ram soft error counter overflow detected

708h

WrOneClearBit

PLX Error Status Register 2

[2]

3

Station0 Packet Link List RAM 2-bit ecc error detected

[3]

4

Station1 Packet Link List RAM 2-bit ecc error detected

[4]

5

Station2 Packet Link List RAM 2-bit ecc error detected

[5]

5

Station3 Packet Link List RAM 2-bit ecc error detected

[6]

5

Station4 Packet Link List RAM 2-bit ecc error detected

[7]

5

Station5 Packet Link List RAM 2-bit ecc error detected

[8]

20

Station0 Header RAM 2-bit ecc error detected

[9]

21

Station1 Header RAM 2-bit ecc error detected

[10]

22

Station2 Header RAM 2-bit ecc error detected

[11]

22

Station3 Header RAM 2-bit ecc error detected

[12]

22

Station4 Header RAM 2-bit ecc error detected

[13]

22

Station5 Header RAM 2-bit ecc error detected

[14]

4

Destination Queue link list ram 2-bit ecc error detected

[15]

9

Source Queue link list ram 2-bit ecc error detected

[16]

11

Retry buffer 2-bit ecc error detected

[17]

7

TIC link list RAM 2-bit ecc error detected

[18]

18

Source Queue link list ram2 2-bit ecc error detected

[19]

19

Destination Queue Data ram 2-bit ecc error detected

710h

WrOneClearBit

PLX Error Status Register 3

[0]

8

Station0 Packet RAM0 Instance0 soft error counter overflow detected

[1]

9

Station1 Packet RAM0 Instance0 soft error counter overflow detected

[2]

10

Station2 Packet RAM0 Instance0 soft error counter overflow detected

[3]

10

Station3 Packet RAM0 Instance0 soft error counter overflow detected

[4]

10

Station4 Packet RAM0 Instance0 soft error counter overflow detected

[5]

10

Station5 Packet RAM0 Instance0 soft error counter overflow detected

[12]

20

Station0 Packet RAM1 Instance0 soft error counter overflow detected

PEX 8696 Errata v1.5

[13]

21

Station1 Packet RAM1 Instance0 soft error counter overflow detected

[14]

22

Station2 Packet RAM1 Instance0 soft error counter overflow detected

[15]

22

Station3 Packet RAM1 Instance0 soft error counter overflow detected

[16]

22

Station4 Packet RAM1 Instance0 soft error counter overflow detected

[17]

22

Station5 Packet RAM1 Instance0 soft error counter overflow detected

718h

WrOneClearBit

PLX Error Status Regiter 4

[0]

14

Station0 Packet RAM0 Instance0 2-bit ecc error detected

[1]

15

Station1 Packet RAM0 Instance0 2-bit ecc error detected

[2]

16

Station2 Packet RAM0 Instance0 2-bit ecc error detected

[3]

16

Station3 Packet RAM0 Instance0 2-bit ecc error detected

[4]

16

Station4 Packet RAM0 Instance0 2-bit ecc error detected

[5]

16

Station5 Packet RAM0 Instance0 2-bit ecc error detected

[12]

26

Station0 Packet RAM1 Instance0 2-bit ecc error detected

[13]

27

Station1 Packet RAM1 Instance0 2-bit ecc error detected

[14]

28

Station2 Packet RAM1 Instance0 2-bit ecc error detected

[15]

28

Station3 Packet RAM1 Instance0 2-bit ecc error detected

[16]

28

Station4 Packet RAM1 Instance0 2-bit ecc error detected

[17]

28

Station5 Packet RAM1 Instance0 2-bit ecc error detected

Impact

Software writes to clear a status clears unexpected ECC error status and does not clear

the intended ECC error status bit.

17. Memory Read TLPs with Relax Ordering (RO) attribute gets

completion timeout under extreme completion credit starvation

condition

Risk Category: Low

Silicon Revisions Affected: AA

Description

Completion without RO can block Completion with RO in a corner case scenario.

Errata is not applicable in the following conditions:

1. If a switch port is ‘only’ transmitting RO completions or ‘only’ transmitting non-

RO completions

2. Devices connected to switch advertise infinite credits for completions (Usually

the case for End Points and Root Complex)

PEX 8696 Errata v1.5

The Memory read TLP with RO gets completion timeout if the switch destination port hits

all the following conditions.

1. Switch destination port gets both completion with RO and without RO TLPs

2. The device on the other end of the link advertises non-infinite completion credit

(It is not an endpoint)

3. Completion credit is throttled to the extreme (one completion TLP progress

every few micro seconds)

Solution/Workaround

1. Disable “Completion special handling for RO” by programming the register in

the first port of each station, offset 760h Bit[29] to 1’b1

Impact

Completion timeout for Memory Read TLP with RO

18. Incorrect TCB Capture of Training Sets

Risk Category: Low

Silicon Revisions Affected: AA

Description

In the case where excess noise exists on a link, the combination of a “COM” symbol

followed by noise can result in the incorrect misinterpretation of Ordered Sets. The

misinterpretation of said sequence might cause the LTSSM to remain in Loopback State,

Compliance State or other improper states until an assertion of a Hot Reset or a

Fundamental Reset is detected.

Solution/Workaround

There are 3 possible workarounds for this erratum:

1. Assert a Hot Reset or Fundamental Reset to the device.

2. Disable TCB capturing by setting register 228h[5], 22Ch[23:20]. There are totally 5

bits in TCB field, they can put the LTSSM into Loopback, Compliance, Disable, Hot

Reset, and Disable Scrambling. Register 228h[5] controls Compliance, Register

22Ch[23] controls Disable Scrambling. Register 22Ch[22] controls Loopback. Register

22C[21] controls Link Disable and register 22Ch[20] controls Hot Reset.

3. Disable and then enable the failing port using register 234h[19:16]

Impact

The link might fail to achieve link-up status.

PEX 8696 Errata v1.5

i. A link will not come up if receivers are detected on a few lanes that

do not exit Electrical Idle in polling

Risk Category: Low

Silicon Revisions Affected: AA

Description

If unused lanes of a multilane link are terminated, the link will not come up. If a PEX8696

detects a receiver on some lanes but these lanes do not detect an exit from electrical idle

in the Polling State, the link is supposed to negotiate out these non functioning lanes and

still link up to a reduced link width. In case of PEX8696, the link will not come up. The

inability of the PEX8696 to negotiate out these terminated but unused lanes is limited to

LTSSM Polling State only. If lanes are found be terminated in Configuration or Recovery

State, PEX8696 will negotiate out these lanes and will link up successfully to a reduced

link width.

Solution/Workaround

1. Do not terminate unused lanes.

2. Use the “Never Detect Electrical Idle” bit if unused lanes are terminated

and the lanes are not reversed.

Impact

Failure to link up in case of terminated unused lanes.

ii. The Default Value of the Class Code Register (0x08) in the NT-

Virtual Port is Incorrect Under Certain Conditions

Risk Category: Low

Silicon Revisions Affected: AA

Description

If NT Mode is disabled by STRAP_NT_EN# =1 and then enabled by EEPROM/I

2

C, or, in

Legacy NT mode if the NT Port Number is to be changed by the EEPPROM/I2C from the

value of STRAP_NT_PORTSEL[4:0], then the default valut of the Class Code Register

(0x08) in the NT-Virtual Port is incorrect as follows:

1. If STRAP_NT_ENABLE# is high (NT disabled) but is overwritten to enable NT

Mode by EEPROM/I

2

C setting the VS0 NT Enable bit (Port 0 offset 0x360h[13]),

then the NT-Virtual Class Code (offset 0x3E008h) value is, incorrectly, 060400h

whereas it should be 068000h.

2. For Legacy NT mode, if EEPROM/I2C changes the NT Port number (in Port 0

offset 0x360h[12:8]) from the value set by STRAP_NT_UPSTRM_PORTSEL[4:0],

PEX 8696 Errata v1.5

then the NT-Virtual Class Code (offset 0x3E008h) value is, incorrectly, 060400h

whereas it should be 068000h.

Solution/Workaround

1. If NT mode is disabled by STRAP_NT_ENABLE# = 1 and EEPROM/I

2

C enables

NT mode by setting the VS0 NT Enable bit (Port 0 offset 0x360h[13), then prior to

programming the VS Upstream Register (Port 0 offset 0x360h), EEPROM/I

2

C

must first load the NT Virtual Class Code register (3E008h) with the correct value

of 0x68000h.

2. In Legacy NT Mode, if EEPROM/I

2

C changes the NT Port number (in Port 0 offset

0x360h[12:8]) from the value set by STRAP_NT_UPSTRM_PORTSEL[4:0], then

prior to changing the NT Port number, EEPROM/I

2

C must first program:

a. The Class Code of the Port selected by

STRAP_NT_UPSTRM_PORTSEL[4:0] to value 060400AAh (PCI-to-PCI

Bridge), and,

b. The Class Code of the NT-Virtual port (offset 0x3E008h) to value

0x068000AAh (Other Bridge).

Impact

BIOS enumeration issues are possible.

iii. The MSI Mask register (0x58h) is implemented according to the

Multiple Message Enable field (0x48h[22:20]) rather than the

Multiple Message Capable field 0x48h[22:20])

Risk Category: Low

Silicon Revisions Affected: AA

Description

The MSI Mask register (0x58h) should be implemented according to the number of MSI

Messages that are implemented (as defined by the value of the Multiple Message

Capable field (0x48h[22:20])), however it is implemented according to the number of MSI

vectors that the host enables (in the Multiple Message Capable field (0x48h[22:20])). In

the PEX 8696, if the host allocates fewer than the requested number of MSI vectors, the

most significant bits of the MSI Mask register that correspond to unallocated vectors are

not writable and those bit values are Set (masked).

Solution/Workaround

All MSI vectors will need to be enabled by the host, to avoid seeing this issue.

PEX 8696 Errata v1.5

Impact

Low impact, no impact to normal functionality. Normally software doesn’t write to

disabled MSI mask register.

iv. Incorrect Completer ID on ACS Source Validation Error

Risk Category: Low

Silicon Revisions Affected: AA

Description

If a downstream Port detects an ACS source validation Error on a Memory Read that is

directed upstream, the downstream Port is to return a Completion having status of CA

(Cpl Abort) with the Completer ID of the Downstream port. Instead, PEX8696 returns the

CA (Cpl Abort) status but with the Completer ID of the Upstream port.

Solution/Workaround

Monitor the Secondary Status Register Signal Target Abort bit (0x1Ch[27]) and/or

Uncorrectable Error Status Register ACS violation (0xFB8h[21])

Impact

Incorrect Completer ID for Memory Read ACS source validation error

v. The NT-Link Port MSI Mask and MSI Pending registers (0x58h,

0x5Ch) cannot be disabled EEPROM/I2C

Risk Category: Low

Silicon Revisions Affected: AA

Description

If the NT-Link Port MSI Per-Vector Mask Capable bit (0x48h[24]) is cleared by

EEPROM/I2C, the MSI Mask and MSI Pending registers should be implemented as

Reserved; they are not.

Solution/Workaround

Do not disable NT-Link port MSI Per-Vector Mask capability

Impact

If a customer wants to disable MSI Per Vector Masking on the NT-Link Port, the MSI

Mask and MSI Pending registers will not be disabled.

PEX 8696 Errata v1.5

vi. If Serial Hot Plug is implemented with MRL disabled (MRL Present

bit (0x7Ch[2]) is cleared by EEPROM/I2C), after Fundamental Reset

the PEX 8696 Serial Hot Plug controller unconditionally initiates the

slot power-up sequence (by asserting the I/O Expander PWREN,

PWRLED#, CLKEN# outputs and de-asserting I/O Expander PERST#

output)

Risk Category: Low

Silicon Revisions Affected: AA

Description

If MRL is disabled, the Serial Hot Plug Controller should not initiate the slot power-up

sequence, but it does. This could be a potential hazard and can also result in

malfunction if a card is inserted into a powered slot.

Solution/Workaround

1. If the Serial Hot Plug MRL input is disabled (by EEPROM clearing the MRL

Sensor Present bit 0x7Ch[2]), additionally disable the power controller by

clearing the Power Controller Present bit (7Ch[1]) in EEPROM. This will

guarantee that the slot is not powered on until software turns on power.

2. The LED connected to the I/O Expander PWRLED# output will correctly

illuminate to indicate that the slot is powered “ON”, therefore rely on it

before inserting a card in the slot.

3. If a Serial Hot Plug MRL sensor is not implemented and automatic slot

power-up sequencing is needed (rather than only using software control),

enable MRL anyway, and connect the I/O Expander Presence Detect input

to the I/O Expander MRL input.

Impact

Low

vii. When Virtual Switch Mode is Enabled, VS_PERST# Does Not

Initialize the Serial Hot-Plug Register

Risk Category: Low

Silicon Revisions Affected: AA

Description

In virtual switch mode, the switch scans IO expander and its values when PEX_PERST#

deasserts. The switch does not re-scan the IO expander again when VS_PERST#

Page is loading ...

Broadcom PEX 8696 Silicon Revisions and Errata List User guide

Broadcom PEX 8696 Silicon Revisions and Errata List User guide

Related papers

Other documents