NXP S08QB Reference guide

HCS08

Microcontrollers

freescale.com

MC9S08QB8

MC9S08QB4

Reference Manual

MC9S08QB8RM

Rev. 1

10/2008

Related Documentation:

• MC9S08QB8 (Data Sheet)

Contains pin assignments and diagrams, all electrical

specifications, and mechanical drawing outlines.

Find the most current versions of all documents at:

http://www.freescale.com

MC9S08QB8 MCU Series Reference Manual, Rev. 1

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8-Bit HCS08 Central Processor Unit (CPU)

• Up to 20 MHz CPU at 3.6 V to 1.8 V across

temperature range of –40 °C to 85 °C

• HC08 instruction set with added BGND

instruction

• Support for up to 32 interrupt/reset sources

On-Chip Memory

• Up to 8 KB flash memory read/program/erase

over full operating voltage and temperature

• Up to 512 bytes random-access memory (RAM)

• Security circuitry to prevent unauthorized

access to RAM and flash contents

Power-Saving Modes

• Two very low power stop modes

• Low power run and low power wait modes

• Peripheral clock enable register can disable

clocks to unused modules, thereby reducing

currents

• Very low power external oscillator that can be

used in stop2 or stop3 modes to provide accurate

clock source to real time counter

•6 μs typical wakeup time from stop3 mode

Clock Source Options

• Oscillator (XOSC) — Loop-control Pierce

oscillator; crystal or ceramic resonator range of

31.25 kHz to 38.4 kHz or 1 MHz to 16 MHz

• Internal Clock Source (ICS) — Internal clock

source module containing a

frequency-locked-loop (FLL) controlled by

internal reference; precision trimming of

internal reference allows 0.2% resolution and

2% deviation over temperature and voltage;

supports bus frequencies from 1 MHz to

10 MHz

System Protection

• Watchdog computer operating properly (COP)

reset with option to run from dedicated 1 kHz

internal clock source or bus clock

• Low-voltage detection with reset or interrupt;

selectable trip points

• Illegal opcode detection with reset

• Illegal address detection with reset

• Flash block protection

Development Support

• Single-wire background debug interface

• Breakpoint capability to allow single breakpoint

setting during in-circuit debugging

Peripherals

• ADC — 8-channel, 12-bit resolution; 2.5 μs

conversion time; automatic compare function;

1.7 mV/°C temperature sensor; internal bandgap

reference channel; operation in stop3; fully

functional from 3.6 V to 1.8 V.

• ACMP — Analog comparator with selectable

interrupt on rising, falling, or either edge of

comparator output; compare option to fixed

internal bandgap reference voltage; output can

be tied internally to TPM input capture;

operation in stop3

• TPM — One 1-channel timer/pulse-width

modulator (TPM) module; selectable input

capture, output compare, or buffered edge- or

center-aligned PWM on each channel; ACMP

output can be tied internally to input capture

• MTIM — 8-bit modulo timer module with

optional prescaler

• RTC — (Real-time counter) 8-bit modulo

counter with binary or decimal based prescaler;

external clock source for precise time base,

time-of-day, calendar or task scheduling

functions; free running on-chip low power

oscillator (1 kHz) for cyclic wakeup without

external components; runs in all MCU modes

• SCI — Full duplex non-return to zero (NRZ);

LIN master extended break generation; LIN

slave extended break detection; wakeup on

active edge

• KBI — 8-pin keyboard interrupt with selectable

edge and level detection modes

Input/Output

• 22 GPIOs and one input-only and one

output-only pins.

• Hysteresis and configurable pullup device on all

input pins; configurable slew rate and drive

strength on all output pins except PTA5.

Package Options

• 28-pin SOIC, 24-pin QFN, 16-pin TSSOP

MC9S08QB8 Features

MC9S08QB8 MCU Series Reference Manual, Rev. 1

4 Freescale Semiconductor

MC9S08QB8 MCU Series Reference Manual, Rev. 1

Freescale Semiconductor 5

MC9S08QB8 MCU Series Reference Manual

Covers: MC9S08QB8

MC9S08QB4

MC9S08QB8

Rev. 1

10/2008

MC9S08QB8 MCU Series Reference Manual, Rev. 1

6 Freescale Semiconductor

Revision History

To provide the most up-to-date information, the revision of our documents on the World Wide Web will

be the most current. Your printed copy may be an earlier revision. To verify you have the latest information

available, refer to:

http://freescale.com

The following revision history table summarizes changes contained in this document.

Revision

Number

Revision

Date

Description of Changes

1 10/17/2008 Initial public released.

Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc.

MC9S08QB8 MCU Series Reference Manual, Rev. 1

Freescale Semiconductor 7

List of Chapters

Chapter Number Title Page

Chapter 1 Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Chapter 2 Pins and Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Chapter 3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Chapter 4 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Chapter 5 Resets, Interrupts, and General System Control . . . . . . . . . . . . . 63

Chapter 6 Parallel Input/Output Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Chapter 7 Keyboard Interrupt (S08KBIV2) . . . . . . . . . . . . . . . . . . . . . . . . . . .95

Chapter 8 Central Processor Unit (S08CPUV5) . . . . . . . . . . . . . . . . . . . . . . 103

Chapter 9 Analog Comparator (S08ACMPVLPV1) . . . . . . . . . . . . . . . . . . . . 123

Chapter 10 Analog-to-Digital Converter (S08ADC12V1) . . . . . . . . . . . . . . .129

Chapter 11 Internal Clock Source (S08ICSV3) . . . . . . . . . . . . . . . . . . . . . . . 155

Chapter 12 Modulo Timer (S08MTIMV1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Chapter 13 Real-Time Counter (S08RTCV1) . . . . . . . . . . . . . . . . . . . . . . . . . 179

Chapter 14 Serial Communications Interface (S08SCIV4). . . . . . . . . . . . . . 189

Chapter 15 Timer/Pulse-Width Modulator (S08TPMV3) . . . . . . . . . . . . . . . . 209

Chapter 16 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

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Contents

Section Number Title Page

Chapter 1

Device Overview

1.1 Devices in the MC9S08QB8 Series ................................................................................................19

1.2 MCU Block Diagram ......................................................................................................................20

1.3 System Clock Distribution ..............................................................................................................21

Chapter 2

Pins and Connections

2.1 Introduction .....................................................................................................................................23

2.2 Device Pin Assignment ...................................................................................................................23

2.3 Recommended System Connections ...............................................................................................25

2.4 Pin Detail .........................................................................................................................................26

2.4.1 Power Pins ........................................................................................................................26

2.4.2 Oscillator ...........................................................................................................................26

2.4.3 RESET Pin ........................................................................................................................27

2.4.4 Background / Mode Select (BKGD/MS) ..........................................................................27

2.4.5 General-Purpose I/O (GPIO) and Peripheral Ports ...........................................................28

Chapter 3

Modes of Operation

3.1 Introduction .....................................................................................................................................31

3.2 Features ...........................................................................................................................................31

3.3 Run Mode ........................................................................................................................................31

3.3.1 Low Power Run Mode (LPRun) .......................................................................................31

3.4 Active Background Mode ...............................................................................................................32

3.5 Wait Mode .......................................................................................................................................33

3.5.1 Low Power Wait Mode (LPWait) .....................................................................................33

3.6 Stop Modes ......................................................................................................................................34

3.6.1 Stop2 Mode .......................................................................................................................35

3.6.2 Stop3 Mode .......................................................................................................................36

3.6.3 Active BDM Enabled in Stop Mode .................................................................................37

3.6.4 LVD Enabled in Stop Mode ..............................................................................................37

3.6.5 Stop Modes in Low Power Run Mode ..............................................................................37

3.7 Mode Selection ................................................................................................................................37

3.7.1 On-Chip Peripheral Modules in Stop and Low Power Modes .........................................40

Chapter 4

Memory

4.1 MC9S08QB8 Series Memory Map .................................................................................................43

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4.2 Reset and Interrupt Vector Assignments .........................................................................................43

4.3 Register Addresses and Bit Assignments ........................................................................................45

4.4 RAM ................................................................................................................................................49

4.5 Flash ................................................................................................................................................50

4.5.1 Features .............................................................................................................................50

4.5.2 Program and Erase Times .................................................................................................50

4.5.3 Program and Erase Command Execution .........................................................................51

4.5.4 Burst Program Execution ..................................................................................................52

4.5.5 Access Errors ....................................................................................................................53

4.5.6 Flash Block Protection ......................................................................................................54

4.5.7 Vector Redirection ............................................................................................................55

4.6 Security ............................................................................................................................................55

4.7 Flash Registers and Control Bits .....................................................................................................56

4.7.1 Flash Clock Divider Register (FCDIV) ............................................................................57

4.7.2 Flash Options Register (FOPT and NVOPT) ....................................................................58

4.7.3 Flash Configuration Register (FCNFG) ...........................................................................59

4.7.4 Flash Protection Register (FPROT and NVPROT) ..........................................................59

4.7.5 Flash Status Register (FSTAT) ..........................................................................................60

4.7.6 Flash Command Register (FCMD) ...................................................................................61

Chapter 5

Resets, Interrupts, and General System Control

5.1 Introduction .....................................................................................................................................63

5.2 Features ...........................................................................................................................................63

5.3 MCU Reset ......................................................................................................................................63

5.4 Computer Operating Properly (COP) Watchdog .............................................................................64

5.5 Interrupts .........................................................................................................................................65

5.5.1 Interrupt Stack Frame .......................................................................................................66

5.5.2 External Interrupt Request (IRQ) Pin ...............................................................................66

5.5.3 Interrupt Vectors, Sources, and Local Masks ...................................................................67

5.6 Low-Voltage Detect (LVD) System ................................................................................................69

5.6.1 Power-On Reset Operation ...............................................................................................69

5.6.2 Low-Voltage Detection (LVD) Reset Operation ...............................................................69

5.6.3 Low-Voltage Detection (LVD) Interrupt Operation ..........................................................69

5.6.4 Low-Voltage Warning (LVW) Interrupt Operation ...........................................................69

5.7 Peripheral Clock Gating ..................................................................................................................69

5.8 Reset, Interrupt, and System Control Registers and Control Bits ...................................................70

5.8.1 Interrupt Pin Request Status and Control Register (IRQSC) ............................................70

5.8.2 System Reset Status Register (SRS) .................................................................................72

5.8.3 System Background Debug Force Reset Register (SBDFR) ............................................73

5.8.4 System Options Register 1 (SOPT1) ................................................................................74

5.8.5 System Options Register 2 (SOPT2) ................................................................................75

5.8.6 System Device Identification Register (SDIDH, SDIDL) ................................................76

5.8.7 System Power Management Status and Control 1 Register (SPMSC1) ...........................77

5.8.8 System Power Management Status and Control 2 Register (SPMSC2) ...........................78

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5.8.9 System Power Management Status and Control 3 Register (SPMSC3) ...........................79

5.8.10 System Clock Gating Control 1 Register (SCGC1) ..........................................................80

5.8.11 System Clock Gating Control 2 Register (SCGC2) ..........................................................81

Chapter 6

Parallel Input/Output Control

6.1 Port Data and Data Direction ..........................................................................................................83

6.2 Pullup, Slew Rate, and Drive Strength ............................................................................................84

6.2.1 Port Internal Pullup Enable ...............................................................................................84

6.2.2 Port Slew Rate Enable ......................................................................................................84

6.2.3 Port Drive Strength Select ................................................................................................84

6.3 Pin Behavior in Stop Modes ............................................................................................................85

6.4 Parallel I/O and Pin Control Registers ............................................................................................85

6.4.1 Port A Registers ................................................................................................................86

6.4.2 Port B Registers ................................................................................................................88

6.4.3 Port C Registers ................................................................................................................91

Chapter 7

Keyboard Interrupt (S08KBIV2)

7.1 Introduction .....................................................................................................................................95

7.1.1 KBI Clock Gating .............................................................................................................95

7.1.2 Features .............................................................................................................................97

7.1.3 Modes of Operation ..........................................................................................................97

7.1.4 Block Diagram ..................................................................................................................97

7.2 External Signal Description ............................................................................................................98

7.3 Register Definition ..........................................................................................................................99

7.3.1 KBI Interrupt Status and Control Register (KBISC) ........................................................99

7.3.2 KBI Interrupt Pin Select Register (KBIPE) ....................................................................100

7.3.3 KBI Interrupt Edge Select Register (KBIES) .................................................................100

7.4 Functional Description ..................................................................................................................100

7.4.1 Edge Only Sensitivity .....................................................................................................101

7.4.2 Edge and Level Sensitivity .............................................................................................101

7.4.3 Pullup/Pulldown Resistors ..............................................................................................101

7.4.4 Keyboard Interrupt Initialization ....................................................................................101

Chapter 8

Central Processor Unit (S08CPUV5)

8.1 Introduction ...................................................................................................................................103

8.1.1 Features ...........................................................................................................................103

8.2 Programmer’s Model and CPU Registers .....................................................................................104

8.2.1 Accumulator (A) .............................................................................................................104

8.2.2 Index Register (H:X) ......................................................................................................104

8.2.3 Stack Pointer (SP) ...........................................................................................................105

8.2.4 Program Counter (PC) ....................................................................................................105

8.2.5 Condition Code Register (CCR) .....................................................................................105

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8.3 Addressing Modes .........................................................................................................................107

8.3.1 Inherent Addressing Mode (INH) ...................................................................................107

8.3.2 Relative Addressing Mode (REL) ..................................................................................107

8.3.3 Immediate Addressing Mode (IMM) ..............................................................................107

8.3.4 Direct Addressing Mode (DIR) ......................................................................................107

8.3.5 Extended Addressing Mode (EXT) ................................................................................108

8.3.6 Indexed Addressing Mode ..............................................................................................108

8.4 Special Operations .........................................................................................................................109

8.4.1 Reset Sequence ...............................................................................................................109

8.4.2 Interrupt Sequence ..........................................................................................................109

8.4.3 Wait Mode Operation ......................................................................................................110

8.4.4 Stop Mode Operation ......................................................................................................110

8.4.5 BGND Instruction ...........................................................................................................111

8.5 HCS08 Instruction Set Summary ..................................................................................................112

Chapter 9

Analog Comparator (S08ACMPVLPV1)

9.1 Introduction ...................................................................................................................................123

9.1.1 ACMP Configuration Information ..................................................................................123

9.1.2 ACMP/TPM Configuration Information ........................................................................123

9.1.3 ACMP Clock Gating .......................................................................................................123

9.1.4 Stop1 Not Available ........................................................................................................123

9.1.5 Features ...........................................................................................................................125

9.1.6 Modes of Operation ........................................................................................................125

9.1.7 Block Diagram ................................................................................................................125

9.2 External Signal Description ..........................................................................................................126

9.3 Register Definition ........................................................................................................................126

9.3.1 Status and Control Register (ACMPSC) .........................................................................126

9.4 Functional Description ..................................................................................................................127

9.5 Interrupts .......................................................................................................................................127

Chapter 10

Analog-to-Digital Converter (S08ADC12V1)

10.1 Introduction ...................................................................................................................................129

10.1.1 ADC Clock Gating ..........................................................................................................129

10.1.2 Module Configurations ...................................................................................................130

10.1.3 Features ...........................................................................................................................133

10.1.4 ADC Module Block Diagram .........................................................................................133

10.2 External Signal Description ..........................................................................................................134

10.2.1 Analog Power (V

DDAD

) ..................................................................................................135

10.2.2 Analog Ground (V

SSAD

) .................................................................................................135

10.2.3 Voltage Reference High (V

REFH

) ...................................................................................135

10.2.4 Voltage Reference Low (V

REFL

) ....................................................................................135

10.2.5 Analog Channel Inputs (ADx) ........................................................................................135

10.3 Register Definition ........................................................................................................................135

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10.3.1 Status and Control Register 1 (ADCSC1) ......................................................................135

10.3.2 Status and Control Register 2 (ADCSC2) ......................................................................137

10.3.3 Data Result High Register (ADCRH) .............................................................................137

10.3.4 Data Result Low Register (ADCRL) ..............................................................................138

10.3.5 Compare Value High Register (ADCCVH) ....................................................................138

10.3.6 Compare Value Low Register (ADCCVL) .....................................................................139

10.3.7 Configuration Register (ADCCFG) ................................................................................139

10.3.8 Pin Control 1 Register (APCTL1) ..................................................................................140

10.3.9 Pin Control 2 Register (APCTL2) ..................................................................................141

10.3.10Pin Control 3 Register (APCTL3) ..................................................................................142

10.4 Functional Description ..................................................................................................................143

10.4.1 Clock Select and Divide Control ....................................................................................144

10.4.2 Input Select and Pin Control ...........................................................................................144

10.4.3 Hardware Trigger ............................................................................................................144

10.4.4 Conversion Control .........................................................................................................144

10.4.5 Automatic Compare Function .........................................................................................147

10.4.6 MCU Wait Mode Operation ............................................................................................147

10.4.7 MCU Stop3 Mode Operation ..........................................................................................148

10.4.8 MCU Stop2 Mode Operation ..........................................................................................148

10.5 Initialization Information ..............................................................................................................149

10.5.1 ADC Module Initialization Example .............................................................................149

10.6 Application Information ................................................................................................................151

10.6.1 External Pins and Routing ..............................................................................................151

10.6.2 Sources of Error ..............................................................................................................152

Chapter 11

Internal Clock Source (S08ICSV3)

11.1 Introduction ...................................................................................................................................155

11.1.1 DCO Select bits ..............................................................................................................155

11.1.2 Features ...........................................................................................................................157

11.1.3 Block Diagram ................................................................................................................157

11.1.4 Modes of Operation ........................................................................................................158

11.2 External Signal Description ..........................................................................................................159

11.3 Register Definition ........................................................................................................................159

11.3.1 ICS Control Register 1 (ICSC1) .....................................................................................160

11.3.2 ICS Control Register 2 (ICSC2) .....................................................................................161

11.3.3 ICS Trim Register (ICSTRM) .........................................................................................161

11.3.4 ICS Status and Control (ICSSC) .....................................................................................162

11.4 Functional Description ..................................................................................................................164

11.4.1 Operational Modes ..........................................................................................................164

11.4.2 Mode Switching ..............................................................................................................166

11.4.3 Bus Frequency Divider ...................................................................................................167

11.4.4 Low Power Bit Usage .....................................................................................................167

11.4.5 DCO Maximum Frequency with 32.768 kHz Oscillator ................................................167

11.4.6 Internal Reference Clock ................................................................................................167

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11.4.7 External Reference Clock ...............................................................................................168

11.4.8 Fixed Frequency Clock ...................................................................................................168

11.4.9 Local Clock .....................................................................................................................168

Chapter 12

Modulo Timer (S08MTIMV1)

12.1 Introduction ...................................................................................................................................169

12.1.1 MTIM/TPM Configuration Information .........................................................................169

12.1.2 MTIM Clock Gating .......................................................................................................169

12.1.3 Features ...........................................................................................................................171

12.1.4 Modes of Operation ........................................................................................................171

12.1.5 Block Diagram ................................................................................................................172

12.2 External Signal Description ..........................................................................................................172

12.3 Register Definition ........................................................................................................................172

12.3.1 MTIM Status and Control Register (MTIMSC) .............................................................174

12.3.2 MTIM Clock Configuration Register (MTIMCLK) .......................................................175

12.3.3 MTIM Counter Register (MTIMCNT) ...........................................................................176

12.3.4 MTIM Modulo Register (MTIMMOD) ..........................................................................176

12.4 Functional Description ..................................................................................................................177

12.4.1 MTIM Operation Example .............................................................................................178

Chapter 13

Real-Time Counter (S08RTCV1)

13.1 Introduction ...................................................................................................................................179

13.1.1 ADC Hardware Trigger ..................................................................................................179

13.1.2 RTC Clock Sources .........................................................................................................179

13.1.3 RTC Modes of Operation ................................................................................................179

13.1.4 RTC Status after Stop2 Wakeup ......................................................................................179

13.1.5 RTC Clock Gating ..........................................................................................................179

13.1.6 Features ...........................................................................................................................181

13.1.7 Modes of Operation ........................................................................................................181

13.1.8 Block Diagram ................................................................................................................182

13.2 External Signal Description ..........................................................................................................182

13.3 Register Definition ........................................................................................................................182

13.3.1 RTC Status and Control Register (RTCSC) ....................................................................183

13.3.2 RTC Counter Register (RTCCNT) ..................................................................................184

13.3.3 RTC Modulo Register (RTCMOD) ................................................................................184

13.4 Functional Description ..................................................................................................................184

13.4.1 RTC Operation Example .................................................................................................185

13.5 Initialization/Application Information ..........................................................................................186

Chapter 14

Serial Communications Interface (S08SCIV4)

14.1 Introduction ...................................................................................................................................189

14.1.1 SCI Clock Gating ............................................................................................................189

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14.1.2 Features ...........................................................................................................................192

14.1.3 Modes of Operation ........................................................................................................192

14.1.4 Block Diagram ................................................................................................................193

14.2 Register Definition ........................................................................................................................195

14.2.1 SCI Baud Rate Registers (SCIBDH, SCIBDL) ..............................................................195

14.2.2 SCI Control Register 1 (SCIC1) .....................................................................................196

14.2.3 SCI Control Register 2 (SCIC2) .....................................................................................197

14.2.4 SCI Status Register 1 (SCIS1) ........................................................................................198

14.2.5 SCI Status Register 2 (SCIS2) ........................................................................................200

14.2.6 SCI Control Register 3 (SCIC3) .....................................................................................201

14.2.7 SCI Data Register (SCID) ...............................................................................................202

14.3 Functional Description ..................................................................................................................202

14.3.1 Baud Rate Generation .....................................................................................................202

14.3.2 Transmitter Functional Description ................................................................................203

14.3.3 Receiver Functional Description ....................................................................................204

14.3.4 Interrupts and Status Flags ..............................................................................................206

14.3.5 Additional SCI Functions ...............................................................................................207

Chapter 15

Timer/Pulse-Width Modulator (S08TPMV3)

15.1 Introduction ...................................................................................................................................209

15.1.1 ACMP/TPM Configuration Information ........................................................................209

15.1.2 TPM External Clock .......................................................................................................209

15.1.3 TPM Pin Repositioning ..................................................................................................209

15.1.4 TPM Clock Gating ..........................................................................................................209

15.1.5 TPMV3 Differences from Previous Versions .................................................................210

15.1.6 Migrating from TPMV1 ..................................................................................................212

15.1.7 Features ...........................................................................................................................214

15.1.8 Modes of Operation ........................................................................................................214

15.1.9 Block Diagram ................................................................................................................215

15.2 Signal Description .........................................................................................................................217

15.2.1 Detailed Signal Descriptions ..........................................................................................217

15.3 Register Definition ........................................................................................................................221

15.3.1 TPM Status and Control Register (TPMSC) ..................................................................221

15.3.2 TPM-Counter Registers (TPMCNTH:TPMCNTL) ........................................................222

15.3.3 TPM Counter Modulo Registers (TPMMODH:TPMMODL) ........................................223

15.3.4 TPM Channel n Status and Control Register (TPMCnSC) ............................................224

15.3.5 TPM Channel Value Registers (TPMCnVH:TPMCnVL) ..............................................225

15.4 Functional Description ..................................................................................................................227

15.4.1 Counter ............................................................................................................................227

15.4.2 Channel Mode Selection .................................................................................................229

15.5 Reset Overview .............................................................................................................................232

15.5.1 General ............................................................................................................................232

15.5.2 Description of Reset Operation .......................................................................................232

15.6 Interrupts .......................................................................................................................................232

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15.6.1 General ............................................................................................................................232

15.6.2 Description of Interrupt Operation .................................................................................233

Chapter 16

Development Support

16.1 Introduction ...................................................................................................................................235

16.1.1 Forcing Active Background ............................................................................................235

16.1.2 Module Configuration .....................................................................................................235

16.1.3 Features ...........................................................................................................................236

16.2 Background Debug Controller (BDC) ..........................................................................................236

16.2.1 BKGD Pin Description ...................................................................................................237

16.2.2 Communication Details ..................................................................................................237

16.2.3 BDC Commands .............................................................................................................240

16.2.4 BDC Hardware Breakpoint .............................................................................................243

16.3 Register Definition ........................................................................................................................243

16.3.1 BDC Registers and Control Bits .....................................................................................244

16.3.2 System Background Debug Force Reset Register (SBDFR) ..........................................246

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Freescale Semiconductor 19

Chapter 1

Device Overview

The MC9S08QB8 and MC9S08QB4 are members of the cost-effective, low-power, low voltage,

high-performance HCS08 family of 8-bit microcontroller units (MCUs). All MCUs in the family use the

enhanced HCS08 core and are available with a variety of modules, memory sizes, memory types, and

package types.

1.1 Devices in the MC9S08QB8 Series

Table 1-1 summarizes the feature set available in the MC9S08QB8 series of MCUs.

t

Table 1-1. MC9S08QB8 Series Features by MCU and Package

Feature MC9S08QB8 MC9S08QB4

Flash size

(bytes)

8192 4096

RAM size (bytes) 512 256

Pin quantity 28 24 16 28 24 16

ACMP yes

ADC channels 8

ADC Resolution 12 12 10 12 12 10

ICS yes

MTIM yes

IRQ yes

KBI 8

Port I/O

1

Port I/O count includes the output-only PTA4 and the input-only

PTA5 pins.

24 20 14 24 20 14

RTC yes

SCI yes

TPM channels 1

XOSCVLP yes

Package 28-pin SOIC, 24-pin QFN, 16-pin TSSOP

Chapter 1 Device Overview

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20 Freescale Semiconductor

1.2 MCU Block Diagram

The block diagram in Figure 1-1 shows the structure of the MC9S08QB8 series MCU.

Figure 1-1. MC9S08QB8 Series Block Diagram

USER FLASH

USER RAM

HCS08 CORE

CPU

BDC

16-BIT TIMER/PWM

MODULE (TPM)

PTB7/EXTAL

PORT B

HCS08 SYSTEM CONTROL

RESETS AND INTERRUPTS

MODES OF OPERATION

POWER MANAGEMENT

COP

LVD

8-BIT MODULO TIMER

MODULE (MTIM)

PTB6/XTAL

PTB5/TPMCH0

PTB4

PTB3/KBIP7/ADP7

PTB2/KBIP6/ADP6

VOLTAGE REGULATOR

PORT A

PTA1/KBIP1/ADP1/ACMP–

ANALOG COMPARATOR

(ACMP)

LOW-POWER OSCILLATOR

20 MHz INTERNAL CLOCK

SOURCE (ICS)

31.25 kHz to 38.4 kHz

1 MHz to 16 MHz

(XOSC)

V

SS

V

DD

ANALOG-TO-DIGITAL

CONVERTER (ADC)

12-BIT

PTB1/KBIP5/TxD/ADP5

PTB0/KBIP4/RxD/ADP4

PORT C

PTC7

PTC6

PTC5

PTC4

REAL-TIME COUNTER

(MC9S08QB8 = 8192 BYTES)

(MC9S08QB4 = 4096 BYTES)

(MC9S08QB8 = 512 BYTES)

(MC9S08QB4 = 256 BYTES)

PTA3/KBIP3/ADP3

PTA2/KBIP2/ADP2

PTA0/KBIP0/TPMCH0/ADP0/ACMP+

PTA4/ACMPO/BKGD/MS

PTA5/IRQ/TCLK/RESET

IRQ

pins not available on 16-pin package

(RTC)

PTA7

PTA6

PTC3

PTC2

PTC1

PTC0

V

REFL

/V

SSA

V

REFH

/V

DDA

SERIAL COMMUNICATIONS

INTERFACE MODULE (SCI)

pins not available on 24-pin or 16-pin packages

KEYBOARD INTERRUPT

(KBI)

1

V

DDA

/V

REFH

and V

SSA

/V

REFL

are double bonded to V

DD

and V

SS

respectively in16-pin package.

Chapter 1 Device Overview

MC9S08QB8 MCU Series Reference Manual, Rev. 1

Freescale Semiconductor 21

Table 1-2 provides the functional version of the on-chip modules.

1.3 System Clock Distribution

Figure 1-2 shows a simplified clock connection diagram. Some modules in the MCU have selectable clock

inputs. The clock inputs to the modules indicate the clock(s) that are used to drive the module functions.

All memory mapped registers associated with the modules are clocked with BUSCLK.

Figure 1-2. System Clock Distribution Diagram

Table 1-2. Module Versions

Module Version

Analog Comparator (ACMPVLP) 1

Analog-to-Digital Converter (ADC12) 1

Central Processor Unit (CPU) 5

Internal Clock Source (ICS) 3

Keyboard Interrupt (KBI) 2

Low Power Oscillator (XOSCVLP) 1

Modulo Timer (MTIM) 1

Real-Time Counter (RTC) 1

Timer Pulse Width Modulator (TPM) 3

Serial Communications Interface (SCI) 4

TPM MTIM

BDCCPU

ADC

3

FLASH

2

ICS

ICSOUT

÷2

BUSCLK

ICSLCLK

ICSIRCLK

COP

1

The fixed frequency clock (FFCLK) is internally synchronized to the bus clock and

must not exceed one half of the bus clock frequency. It is XCLK in Chapter 12,

“Modulo Timer (S08MTIMV1).”

2

Flash has frequency requirements for program and erase operation. See

MC9S08QB8 Series Data Sheet for details.

3

ADC has minimum and maximum frequency requirements. See the Chapter 10,

“Analog-to-Digital Converter (S08ADC12V1),” and MC9S08QB8 Data Sheet for

details.

XOSCVLP

EXTAL

XTAL

FFCLK

1

ICSFFCLK

RTC

1 kHZ

LPO

TCLK

ICSERCLK

÷2

SYNC*

LPOCLK

OSCOUT

SCI

Chapter 1 Device Overview

MC9S08QB8 MCU Series Reference Manual, Rev. 1

22 Freescale Semiconductor

The ICS supplies the following clock sources:

• ICSOUT — This clock source is used as the CPU clock and is divided by 2 to generate the

peripheral bus clock, BUSCLK. Control bits in the ICS control registers determine which of three

clock sources is connected:

— Internal reference clock

— External reference clock

— Frequency-locked loop (FLL) output

See Chapter 11, “Internal Clock Source (S08ICSV3),” for details on configuring the ICSOUT

clock.

• ICSLCLK — This clock source is derived from the digitally controlled oscillator, DCO, of the ICS

when the ICS is configured to run off of the internal or external reference clock. Development tools

can select this internal self-clocked source (~ 8 MHz) to speed up BDC communications in systems

where the bus clock is slow.

• ICSERCLK — This is the external reference clock and can be selected as the alternate clock for

the ADC module. Section 11.4.7, “External Reference Clock,” explains the ICSERCLK in more

detail. See Chapter 10, “Analog-to-Digital Converter (S08ADC12V1),” for more information

regarding the use of ICSERCLK with these modules.

• ICSIRCLK — This is the internal reference clock and can be selected as the real-time counter clock

source. Chapter 11, “Internal Clock Source (S08ICSV3)” explains the ICSIRCLK in more detail.

See Chapter 13, “Real-Time Counter (S08RTCV1)” for more information regarding the use of

ICSIRCLK.

• ICSFFCLK — This generates the fixed frequency clock (FFCLK) after being synchronized to the

bus clock. It can be selected as clock source for the TPM module and MTIM module. The

frequency of the ICSFFCLK is determined by the settings of the ICS. See the “Fixed Frequency

Clock” section in Chapter 11, “Internal Clock Source (S08ICSV3)” for details.

• LPOCLK — This clock is generated from an internal low power oscillator that is completely

independent of the ICS module. The LPOCLK can be selected as the clock source to the RTC or

COP modules. See Chapter 13, “Real-Time Counter (S08RTCV1),” and Section 5.4, “Computer

Operating Properly (COP) Watchdog,” for details on using the LPOCLK with these modules.

• OSCOUT — This is the output of the XOSCVLP module and can be selected as the real-time

counter clock source.

• TCLK — TCLK is the optional external clock source for the TPM and MTIM modules. The TCLK

must be limited to 1/4th the frequency of the bus clock for synchronization. See Chapter 15,

“Timer/Pulse-Width Modulator (S08TPMV3),” and Chapter 12, “Modulo Timer (S08MTIMV1),”

for more details.

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NXP S08QB Reference guide

NXP S08QB Reference guide

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