MANUZOID
Explore
Explore
Bookmarks
NXP
S08QB
NXP S08QB Reference guide
Type
Reference guide
Brand
NXP
Size
3.80 MB
Pages
248
Language
English
View document
NXP S08QB Reference guide
Type
Reference guide
Brand
NXP
Size
2.95 MB
Pages
56
Language
English
View document
NXP S08QB Reference guide
Type
Reference guide
Brand
NXP
Size
4.72 MB
Pages
324
Language
English
Table of contents
List of Chapters
3
Table of Contents
5
Chapter 1 General Information and Block Diagram
15
1.1 Introduction to the HCS08 Family of Microcontrollers
15
1.2 Programmer’s Model for the HCS08 CPU
16
1.3 Peripheral Modules
16
1.4 Features of the MC9S08GB60
17
1.4.1 Standard Features of the HCS08 Family
17
1.4.2 Features of MC9S08GB60 MCU
17
1.5 Block Diagram of the MC9S08GB60
17
Chapter 2 Pins and Connections
19
2.1 Introduction
19
2.2 Recommended System Connections
19
2.2.1 Power
19
2.2.2 MC9S08GB60 Oscillator
21
2.2.3 Reset
21
2.2.4 Background/Mode Select (BKGD/MS)
22
2.2.5 General-Purpose I/O and Peripheral Ports
22
Chapter 3 Modes of Operation
25
3.1 Introduction
25
3.2 Features
25
3.3 Run Mode
25
3.4 Active Background Mode
25
3.5 Wait Mode
26
3.6 Stop Modes
27
3.6.1 Stop1 Mode
28
3.6.2 Stop2 Mode
28
3.6.3 Stop3 Mode
29
3.6.4 Active BDM Enabled in Stop Mode
29
3.6.5 OSCSTEN Bit Set
30
3.6.6 LVD Enabled in Stop Mode
30
3.6.7 On-Chip Peripheral Modules in Stop Modes
30
3.6.8 System Options Register (SOPT)
32
3.6.9 System Power Management Status and Control 1 Register (SPMSC1)
33
3.6.10 System Power Management Status and Control 2 Register (SPMSC2)
34
Chapter 4 On-Chip Memory
37
4.1 Introduction
37
4.2 HCS08 Core-Defined Memory Map
37
4.2.1 HCS08 Memory Map
37
4.2.2 MC9S08GB60 Memory Map
38
4.2.3 Reset and Interrupt Vector Assignments
39
4.3 Register Addresses and Bit Assignments
41
4.4 RAM
46
4.5 60-Kbyte FLASH
46
4.5.1 Features
47
4.5.2 Program, Erase, and Blank Check Commands
47
4.5.3 Command Timing and Burst Programming
49
4.5.3.1 Rows and FLASH Organization
49
4.5.3.2 Program Command Timing Sequence
49
4.5.4 Access Errors
50
4.5.5 Vector Redirection
51
4.5.6 FLASH Block Protection (MC9S08GB60)
51
4.6 Security (MC9S08GB60)
51
4.7 FLASH Registers and Control Bits (MC9S08GB60)
53
4.7.1 FLASH Clock Divider Register (FCDIV)
53
4.7.2 FLASH Options Register (FOPT and NVFOPT)
54
4.7.3 FLASH Configuration Register (FCNFG)
55
4.7.4 FLASH Protection Register (FPROT and NVFPROT)
56
4.7.5 FLASH Status Register (FSTAT)
57
4.7.6 FLASH Command Register (FCMD)
58
4.8 FLASH Application Examples
58
4.8.1 Initialization of the FLASH Module Clock
59
4.8.2 Erase One 512-Byte Page in FLASH
60
4.8.3 DoOnStack Subroutine
61
4.8.4 SpSub Subroutine
63
4.8.5 Program One Byte of FLASH
64
Chapter 5 Resets and Interrupts
65
5.1 Introduction
65
5.2 Reset and Interrupt Features for MC9S08GB60
65
5.3 MCU Reset
66
5.4 Computer Operating Properly (COP) Watchdog
66
5.5 Interrupts
66
5.5.1 Interrupt Stack Frame
67
5.5.2 External Interrupt Request (IRQ) Pin
67
5.5.2.1 Pin Configuration Options
68
5.5.2.2 Edge and Level Sensitivity
68
5.5.3 Interrupt Vectors, Sources, and Local Masks
69
5.6 Low-Voltage Detect (LVD) System
69
5.6.1 Power-On Reset Operation
69
5.6.2 LVD Reset Operation
69
5.6.3 LVD Interrupt Operation
69
5.6.4 Low-Voltage Warning (LVW)
69
5.7 Real-Time Interrupt (RTI)
71
5.8 Reset, Interrupt, and System Control Registers and Control Bits
71
5.8.1 Interrupt Request Status and Control Register (IRQSC)
72
5.8.2 System Reset Status Register (SRS)
73
5.8.3 System Background Debug Force Reset Register (SBDFR)
74
5.8.4 System Options Register (SOPT)
74
5.8.5 System Device Identification Register (SDIDH, SDIDL)
75
5.8.6 System Real-Time Interrupt Status and Control Register (SRTISC)
76
5.8.7 System Power Management Status and Control 1 Register (SPMSC1)
77
5.8.8 System Power Management Status and Control 2 Register (SPMSC2)
78
Chapter 6 Central Processor Unit (CPU)
79
6.1 Introduction
79
6.2 Programmer’s Model and CPU Registers
80
6.2.1 Accumulator (A)
80
6.2.2 Index Register (H:X)
81
6.2.3 Stack Pointer (SP)
82
6.2.4 Program Counter (PC)
84
6.2.5 Condition Code Register
84
6.3 Addressing Modes
89
6.3.1 Inherent Addressing Mode (INH)
90
6.3.2 Relative Addressing Mode (REL)
90
6.3.3 Immediate Addressing Mode (IMM)
91
6.3.4 Direct Addressing Mode (DIR)
91
6.3.5 Extended Addressing Mode (EXT)
92
6.3.6 Indexed Addressing Mode
92
6.3.6.1 Indexed, No Offset (IX)
92
6.3.6.2 Indexed, No Offset with Post Increment (IX+)
92
6.3.6.3 Indexed, 8-Bit Offset (IX1)
92
6.3.6.4 Indexed, 8-Bit Offset with Post Increment (IX1+)
93
6.3.6.5 Indexed, 16-Bit Offset (IX2)
93
6.3.6.6 SP-Relative, 8-Bit Offset (SP1)
93
6.3.6.7 SP-Relative, 16-Bit Offset (SP2)
94
6.4 Special Operations
94
6.4.1 Reset Sequence
94
6.4.2 Interrupts
95
6.4.3 Wait Mode
96
6.4.4 Stop Mode
96
6.4.5 Active Background Mode
96
6.4.6 User’s View of a Bus Cycle
97
6.5 Instruction Set Description by Instruction Types
97
6.5.1 Data Movement Instructions
97
6.5.1.1 Loads and Stores
98
6.5.1.2 Bit Set and Bit Clear
100
6.5.1.3 Memory-to-Memory Moves
101
6.5.1.4 Register Transfers and Nibble Swap
101
6.5.2 Math Instructions
102
6.5.2.1 Add, Subtract, Multiply, and Divide
102
6.5.2.2 Increment, Decrement, Clear, and Negate
107
6.5.2.3 Compare and Test
107
6.5.2.4 BCD Arithmetic
107
6.5.3 Logical Operation Instructions
108
6.5.3.1 AND, OR, Exclusive-OR, and Complement
109
6.5.3.2 BIT Instruction
110
6.5.4 Shift and Rotate Instructions
110
6.5.5 Jump, Branch, and Loop Control Instructions
112
6.5.5.1 Unconditional Jump and Branch
113
6.5.5.2 Simple Branches
113
6.5.5.3 Signed Branches
114
6.5.5.4 Unsigned Branches
114
6.5.5.5 Bit Condition Branches
114
6.5.5.6 Loop Control
115
6.5.6 Stack-Related Instructions
116
6.5.7 Miscellaneous Instructions
119
6.6 Instruction Set Summary
121
6.7 Assembly Language Tutorial
132
6.7.1 Parts of a Listing Line
132
6.7.2 Assembler Directives
133
6.7.2.1 BASE - Set Default Number Base for Assembler
133
6.7.2.2 INCLUDE - Specify Additional Source Files
133
6.7.2.3 NOLIST/LIST - Turn Off or Turn On Listing
134
6.7.2.4 ORG - Set Program Starting Location
134
6.7.2.5 EQU - Equate a Label to a Value
135
6.7.2.6 dc.b - Define Byte-Sized Constants in Memory
136
6.7.2.7 dc.w - Define 16-Bit (Word) Constants in Memory
136
6.7.2.8 ds.b - Define Storage (Reserve) Memory Bytes
137
6.7.3 Labels
138
6.7.4 Expressions
139
6.7.5 Equate File Conventions
140
6.7.6 Object Code (S19) Files
141
Chapter 7 Development Support
145
7.1 Introduction
145
7.2 Features
146
7.3 Background Debug Controller (BDC)
146
7.3.1 BKGD Pin Description
147
7.3.2 Communication Details
148
7.3.2.1 BDC Communication Speed Considerations
149
7.3.2.2 Bit Timing Details
149
7.3.3 BDC Registers and Control Bits
151
7.3.3.1 BDC Status and Control Register
152
7.3.3.2 BDC Breakpoint Match Register
153
7.3.4 BDC Commands
153
7.3.4.1 SYNC - Request Timed Reference Pulse
155
7.3.4.2 ACK_ENABLE
156
7.3.4.3 ACK_DISABLE
156
7.3.4.4 BACKGROUND
157
7.3.4.5 READ_STATUS
157
7.3.4.6 WRITE_CONTROL
158
7.3.4.7 READ_BYTE
159
7.3.4.8 READ_BYTE_WS
159
7.3.4.9 READ_LAST
160
7.3.4.10 WRITE_BYTE
160
7.3.4.11 WRITE_BYTE_WS
160
7.3.4.12 READ_BKPT
161
7.3.4.13 WRITE_BKPT
161
7.3.4.14 GO
162
7.3.4.15 TRACE1
162
7.3.4.16 TAGGO
162
7.3.4.17 READ_A
163
7.3.4.18 READ_CCR
163
7.3.4.19 READ_PC
163
7.3.4.20 READ_HX
164
7.3.4.21 READ_SP
164
7.3.4.22 READ_NEXT
164
7.3.4.23 READ_NEXT_WS
165
7.3.4.24 WRITE_A
165
7.3.4.25 WRITE_CCR
166
7.3.4.26 WRITE_PC
166
7.3.4.27 WRITE_HX
166
7.3.4.28 WRITE_SP
166
7.3.4.29 WRITE_NEXT
167
7.3.4.30 WRITE_NEXT_WS
167
7.3.5 Serial Interface Hardware Handshake Protocol
168
7.3.6 Hardware Handshake Abort Procedure
170
7.3.7 BDC Hardware Breakpoint
173
7.3.8 Differences from M68HC12 BDM
173
7.3.8.1 8-Bit Architecture
174
7.3.8.2 Command Formats
174
7.3.8.3 Read and Write with Status
174
7.3.8.4 BDM Versus Stop and Wait Modes
175
7.3.8.5 SYNC Command
175
7.3.8.6 Hardware Breakpoint
175
7.4 Part Identification and BDC Force Reset
176
7.4.1 System Device Identification Registers (SDIDH:SDIDL)
176
7.4.2 System Background Debug Force Reset Register
177
7.5 On-Chip Debug System (DBG)
177
7.5.1 Comparators A and B
177
7.5.2 Bus Capture Information and FIFO Operation
178
7.5.3 Change-of-Flow information
179
7.5.4 Tag vs. Force Breakpoints and Triggers
180
7.5.5 CPU Breakpoint Requests
180
7.5.6 Trigger Modes
180
7.5.6.1 A-Only Trigger
181
7.5.6.2 A OR B Trigger
181
7.5.6.3 A Then B Trigger
181
7.5.6.4 Event-Only B Trigger (Store Data)
181
7.5.6.5 A Then Event-Only B Trigger (Store Data)
182
7.5.6.6 A AND B Data Trigger (Full Mode)
182
7.5.6.7 A AND NOT B Data Trigger (Full Mode)
182
7.5.6.8 Inside Range Trigger: A £ Address £ B
182
7.5.6.9 Outside Range Trigger: Address < A or Address > B
182
7.5.7 DBG Registers and Control Bits
183
7.5.7.1 Debug Comparator A High Register (DBGCAH)
183
7.5.7.2 Debug Comparator A Low Register (DBGCAL)
183
7.5.7.3 Debug Comparator B High Register (DBGCBH)
183
7.5.7.4 Debug Comparator B Low Register (DBGCBL)
183
7.5.7.5 Debug FIFO High Register (DBGFH)
183
7.5.7.6 Debug FIFO Low Register (DBGFL)
184
7.5.7.7 Debug Control Register
184
7.5.7.8 Debug Trigger Register
186
7.5.7.9 Debug Status Register
187
7.5.8 Application Information and Examples
188
7.5.8.1 Orientation to the Debugger Examples
189
7.5.8.2 Example 1: Stop Execution at Address A
190
7.5.8.3 Example 2: Stop Execution at the Instruction at Address A
190
7.5.8.4 Example 3: Stop Execution at the Instruction at Address A or Address B
191
7.5.8.5 Example 4: Begin Trace at the Instruction at Address A
191
7.5.8.6 Example 5: End Trace to Stop After A-Then-B Sequence
192
7.5.8.7 Example 6: Begin Trace On Write of Data B to Address A
192
7.5.8.8 Example 7: Capture the First Eight Values Read From Address B
193
7.5.8.9 Example 8: Capture Values Written to Address B After Address A Read
193
7.5.8.10 Example 9: Trigger On Any Execution Within a Routine
194
7.5.8.11 Example 10: Trigger On Any Attempt To Execute Outside FLASH
194
7.5.9 Hardware Breakpoints and ROM Patching
194
Appendix A Instruction Set Details
197
A.1 Introduction
197
A.2 Nomenclature
197
A.3 Convention Definitions
200
A.4 Instruction Set
200
Appendix B Equate File Conventions
295
B.1 Introduction
295
B.2 Memory Map Definition
296
B.3 Vector Definitions
296
B.4 Bits Defined in Two Ways
297
B.5 Complete Equate File for MC9S08GB60
298
View document
NXP S08QB User guide
Type
User guide
Brand
NXP
Size
419.67 KB
Pages
2
Language
English
View document
NXP S08QB User guide
Type
User guide
Brand
NXP
Size
1.93 MB
Category
Supplementary music equipment
Pages
116
Language
English
View document
NXP S08QB User guide
Type
User guide
Brand
NXP
Size
2.43 MB
Category
Motherboards
Pages
121
Language
English
View document