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Altera MAX 10 series User manual

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MAX 10 FPGA Development Kit User
Guide
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UG-01169
2017.09.07
101 Innovation Drive
San Jose, CA 95134
www.altera.com
Contents
Overview.............................................................................................................. 1-1
General Description.....................................................................................................................................1-2
Handling the Board..................................................................................................................................... 1-4
Getting Started.................................................................................................... 2-1
Quartus II Web Edition Soware...............................................................................................................2-1
Installing the Development Kit.................................................................................................................. 2-1
Installing the USB-Blaster Driver.............................................................................................................. 2-2
Board Update Portal.................................................................................................................................... 2-2
Board Test System................................................................................................3-1
Using the Congure Menu..........................................................................................................................3-3
e System Info Tab.....................................................................................................................................3-5
e GPIO Tab...............................................................................................................................................3-7
e Flash Tab................................................................................................................................................ 3-9
e HSMC Tab...........................................................................................................................................3-11
e DDR3 Tab............................................................................................................................................3-13
e ADC Tab.............................................................................................................................................. 3-15
e HDMI Tab........................................................................................................................................... 3-17
e Sleep Mode Tab...................................................................................................................................3-18
e Power Monitor.................................................................................................................................... 3-20
e Clock Control......................................................................................................................................3-22
Board Components..............................................................................................4-1
Board Overview............................................................................................................................................4-1
Featured Device............................................................................................................................................4-3
Conguration............................................................................................................................................... 4-4
Using the Quartus II Programmer.................................................................................................4-4
Selecting the Internal Conguration Scheme.............................................................................. 4-4
Switch and Jumper Settings............................................................................................................ 4-5
Status Elements.............................................................................................................................................4-7
Setup Elements............................................................................................................................................. 4-8
General User Input/Output.........................................................................................................................4-8
Clock Circuitry.............................................................................................................................................4-9
On-Board Oscillators.................................................................................................................... 4-10
O-Board Clock Input/Output.................................................................................................... 4-11
Components and Interfaces......................................................................................................................4-12
10/100/1000 Ethernet PHY...........................................................................................................4-12
Digital-to-Analog Converter........................................................................................................ 4-15
HDMI Video Output..................................................................................................................... 4-16
TOC-2
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HSMC.............................................................................................................................................. 4-17
Pmod Connectors.......................................................................................................................... 4-22
USB to UART..................................................................................................................................4-23
Memory....................................................................................................................................................... 4-24
DDR3 Rev. B Board....................................................................................................................... 4-24
DDR3 Rev. C Board....................................................................................................................... 4-26
Flash.................................................................................................................................................4-29
Power Distribution System....................................................................................................................... 4-31
Additional Information...................................................................................... A-1
User Guide Revision History..................................................................................................................... A-1
Compliance and Conformity Statements.................................................................................................A-2
CE EMI Conformity Caution........................................................................................................ A-2
TOC-3
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Overview
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e MAX
®
10 FPGA development board provides a hardware platform for evaluating the performance
and features of the Altera
®
MAX 10 device.
e development kit includes a RoHS- and CE-compliant MAX 10 FPGA Development board with the
following components:
• Featured Devices:
• MAX 10 FPGA (10M50D, dual supply, F484 package)
• Enpirion
®
EN2342QI 4 A PowerSoC Voltage-Mode Synchronous Step-Down Converter with
Integrated Inductor Enpirion
• EN6337QI 3 A High-Eciency PowerSoC DC-DC Step-Down Converters with Integrated Inductor
• Enpirion EP5358xUI 600 mA PowerSoC DC-DC Step-Down Converters with Integrated Inductor
• MAX II CPLD – EPM1270M256C4N (On-board USB-Blaster
™
II)
• Programming and Conguration:
• Embedded USB-Blaster II (JTAG)
• Optional JTAG direct via 10-pin header
• Memory Devices:
• 64-Mx16 1 Gb DDR3 SDRAM with so memory controller
• 128-Mx8 1 Gb DDR3 SDRAM with so memory controller
• 512-Mb Quad serial peripheral interface (quad SPI) ash
• Communication Ports:
• Two Gigabit Ethernet (GbE) RJ-45 ports
• Ethernet Port A (Bottom)
• Ethernet Port B (Top)
• One mini-USB2.0 UART
• One high-denition multimedia interface (HDMI) video output
• One universal high-speed mezzanine card (HSMC) connector
• Two 12-pin Digilent Pmod
™
compatible connectors
Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of
Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current
specications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice.
Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly
agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specications before relying on any published information
and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2008
Registered
www.altera.com
101 Innovation Drive, San Jose, CA 95134
• Analog:
• Two MAX 10 FPGA analog-to-digital converter (ADC) SMA inputs
• 2x10 ADC header
• Potentiometer input to ADC
• One external 16 bit digital-to-analog converter (DAC) device with SMA output
• Clocking
• 25 MHz single-ended, external oscillator clock source
• Silicon labs clock generator with programmable frequency GUI
• Mini-USB cable for on-board USB-Blaster
™
II
• 2A Power Supply and cord
• Free Quartus
®
II Web Edition design soware (download soware and license from website)
• Complete documentation
• User manual, bill of materials, schematic, and board les
General Description
Figure 1-1: MAX 10 FPGA Board Components (Top)
PMOD
CONNECTOR
(J4)
FPGA
RECONFIGURE
BUTTON
USER
PUSH BUTTONS
DC INPUT
12 V
(J15)
HSMC CONNECTOR
(J2)
USER LEDs
DDR3 64Mx16
SDRAM
Enpirion EN2342QI 4A
PowerSoC
Enpirion EN6337 3A
PowerSoC
JTAG HEADER
(J14)
USB
BLASTER
(J12)
USB to UART
(J11)
CLOCK GENERATION
CHIP
POT1
2x10 PIN HEADER
(J20)
SMA - ANAIN2
(J19)
HDMI CONNECTOR
(J8)
FPGA_CPU_RESET
BUTTON
POWER
SWITCH
(SW3)
PMOD
CONNECTOR
(J5)
DUAL ETHERNET
CONNECTOR
(RJ1)
SMA - ANAIN1
(J18)
SMA - DACOUT
(J1)
16-Bit DAC
MAX II USB-BLASTER II
CIRCUIT
Ethernet A (Bottom)
Ethernet B (Top)
LED4
LED3
LED2
LED1
LED0
USER PB3
USER PB2
USER PB1
USER PB0
1-2
General Description
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Figure 1-2: MAX 10 FPGA Board Components (Bottom)
Note: To determine the revision of your board, look for the serial number at the bottom of the board.
DDR3 128Mx8
BOARD
REVISON
SDRAM (U6)
USER DIP SWITCH
(SW2)
QUAD SPI FLASH
USER DIP SWITCH
(SW1)
ENPIRION
EN6337
ENPIRION
EN6337
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General Description
1-3
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Figure 1-3: System Block Diagram
~
HDMI TX
USB Blaster
FTDI + MAXII/ V
USB to UART
DC Supply
DDR 3
512 Mb x16
QSPI Flash
1 Gb x16
2x10
ADC IN/GPI O
DACOUT
DAC
AIN1
AIN2
FPGA _RESET
JTAG
Qsci llator
Potentiometer
PMOD
PMOD
HSMC
2x 1 GbE
~
User DIP Switches User Push Buttons
User LEDs
Handling the Board
When handling the board, it is important to observe static discharge precautions.
Caution:
Without proper anti-static handling, the board can be damaged. erefore, use anti-static
handling precautions when touching the board.
Caution: is development kit should not be operated in a Vibration Environment.
1-4
Handling the Board
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Getting Started
2
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Quartus II Web Edition Software
e Quartus II Web Edition Soware is a free with no license required.
You can download the Web Edition soware from the Altera website. Alternatively, you can request a
DVD.
Related Information
• Quartus II Web Edition Soware
• Altera IP and Soware DVD Request Form
• Altera Quartus II Soware - Subscription Edition vs. Web Edition
Installing the Development Kit
1. Download the MAX 10 Development Kit installer from the MAX 10 FPGA Development Kit page of
the Altera website. Alternatively, you can request a development kit DVD from the Altera Kit Installa‐
tions DVD Request Form page of the Altera website.
2. Run the MAX 10 FPGA Development Kit installer.
3. Follow the on-screen instructions to complete the installation process. Be sure that the installation
directory you choose is in the same relative location to the Quartus II soware installation.
e installation program creates the development kit directory structure shown in the following gure.
Attention:
.sof les are used by BTS GUI to congure the MAX 10 device and start corresponding
test. erefore, do not to move the .sof les from the *\examples\board_test_
system directory.
Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of
Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current
specications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice.
Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly
agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specications before relying on any published information
and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2008
Registered
www.altera.com
101 Innovation Drive, San Jose, CA 95134
Figure 2-1: Installed Development Kit Directory Structure
<install dir>
documents
board_design_files
The default Windows installation directory is C:\altera\<version>\.
examples
factory_recovery
demos
kits
<device name>
Table 2-1: Installed Directory Contents
Directory Name Description of Contents
board_design_files Contains schematic, layout, assembly, and bill of material board design les.
Use these les as a starting point for a new prototype board design.
demos Contains demonstration applications when available.
documents Contains the following documentation:
• MAX 10 FPGA Development Kit User Guide
• Quick Start Guide
• Dear Customer Letter
examples Contains the sample design les for this kit.
factory_recovery Contains the original data programmed onto the board before shipment. Use
this data to restore the board with its original factory contents.
Installing the USB-Blaster Driver
e development board includes integrated USB-Blaster circuitry for FPGA programming. However, for
the host computer and board to communicate, you must install the On-Board USB-Blaster II driver on the
host computer.
Installation instructions for the On-Board USB-Blaster II driver for your operating system are available on
the Altera website. On the Altera Programming Cable Driver Information page of the Altera website,
locate the table entry for your conguration and click the link to access the instructions.
Board Update Portal
You can keep your board current by accessing the Board Update Portal on www.altera.com.
2-2
Installing the USB-Blaster Driver
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is web site allows you access useful information and updated soware and design examples for your
board. For instructions on setting up your board to access the Board Update Portal, consult the printed
Quick Start Guide that is included in the kit box.
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Board Update Portal
2-3
Getting Started
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Board Test System
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is kit includes an application called the Board Test System (BTS).
e BTS provides an easy-to-use interface to alter functional settings and observe the results. You can use
the BTS to test board components, modify functional parameters, observe performance, and measure
power usage. While using the BTS, you recongure the FPGA several times with test designs specic to the
functionality you are testing.
Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of
Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current
specications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice.
Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly
agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specications before relying on any published information
and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2008
Registered
www.altera.com
101 Innovation Drive, San Jose, CA 95134
Figure 3-1: Board Test System GUI
Several designs are provided to test the major board features. Each design provides data for one or more
tabs in the application. e Congure menu identies the appropriate design to download to the FPGA
for each tab.
Aer successful FPGA conguration, the appropriate tab appears that allows you to exercise the related
board features. Highlights appear in the board picture around the corresponding components
e BTS communicates over the JTAG bus to a test design running in the FPGA. e Board Test System
and Power Monitor share the JTAG bus with other applications like the Nios II debugger and the
SignalTap
®
II Embedded Logic Analyzer. Because the Quartus II programmer uses most of the bandwidth
of the JTAG bus, other applications using the JTAG bus might time out. Be sure to close the other applica‐
tions before attempting to recongure the FPGA using the Quartus II Programmer.
3-2
Board Test System
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Using the Congure Menu
Use the Congure menu to select the design you want to use. Each design example tests dierent board
features. Choose a design from this menu and the corresponding tabs become active for testing.
Figure 3-2: The Congure Menu
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Using the Congure Menu
3-3
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To congure the FPGA with a test system design, perform the following steps:
1. On the Congure menu, click the congure command that corresponds to the functionality you wish
to test.
2. In the dialog box that appears, click Congure to download the corresponding design to the FPGA.
3. When conguration nishes, close the Quartus II Programmer if open. e design begins running in
the FPGA. e corresponding GUI application tabs that interface with the design are now enabled.
If you use the Quartus II Programmer for conguration, rather than the Board Test System GUI, you may
need to restart the GUI.
3-4
Using the Congure Menu
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The System Info Tab
e System Info tab shows the board’s current conguration. e tab displays the JTAG chain, the board’s
MAC address, the Qsys memory map, and other details stored on the board.
Figure 3-3: The System Info Tab
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The System Info Tab
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Table 3-1: Controls on the System Info Tab
Controls Description
Board Information Controls e board information is updated once the GPIO design is congured.
Otherwise, this control displays the default static information about
your board.
Board Name Indicates the ocial name of the board, given by the Board Test
System.
Board P/N Indicates the part number of the board.
Serial Number Indicates the serial number of the board.
Factory Test Version Indicates the version of the Board Test System currently running on
the board.
MAX Version Indicates the version of MAX code currently running on the board.
Ethernet A MAC Indicates the Ethernet A MAC address of the board.
Ethernet B MAC Indicates the Ethernet B MAC address of the board.
JTAG Chain Shows all the devices currently in the JTAG chain.
Qsys Memory Map Shows the memory map of the Qsys system on your board.
3-6
The System Info Tab
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The GPIO Tab
e GPIO tab allows you to interact with all the general purpose user I/O components on your board. You
can read DIP switch settings, turn LEDs on or o, and detect push button presses.
Figure 3-4: The GPIO Tab
Table 3-2: Controls on the GPIO Tab
User DIP Switch
Displays the current positions of the switches in the user DIP switch
banks. Change the switches on the board to see the graphical display
change accordingly.
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The GPIO Tab
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User LEDs Displays the current state of the user LEDs for the FPGA. To toggle the
board LEDs, click the 0 to 4 buttons to toggle red or green LEDs, or
click the All button.
Push Button Switches Read-only control displays the current state of the board user push
buttons. Press a push button on the board to see the graphical display
change accordingly.
3-8
The GPIO Tab
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The Flash Tab
e Flash Tab allows you to read and write ash memory on your board.
Figure 3-5: The Flash Tab (Detail)
Control Description
Read Reads the ash memory on your board. To see the ash memory
contents, type a starting address in the text box and click Read. Values
starting at the specied address appear in the table.
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The Flash Tab
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Control Description
Write Writes the ash memory on your board. To update the ash memory
contents, change values in the table and click Write. e application
writes the new values to ash memory and then reads the values back
to guarantee that the graphical display accurately reects the memory
contents.
Erase Erases ash memory.
Increment Test Starts an incrementing data pattern test to ash memory, limited to the
512 K test system scratch page.
Random Test Starts a random data pattern test to ash memory, limited to the 512 K
test system scratch page.
Flash Memory Map Displays the ash memory map for the development board.
3-10
The Flash Tab
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