NXP LS1043ARDB-PD Operating instructions

QorIQ LS1043A Reference Design

Board Reference Manual

Document Number: LS1043ARDBRM

Rev. 4, 11/2017

QorIQ LS1043A Reference Design Board Reference Manual, Rev. 4, 11/2017

2 NXP Semiconductors

Contents

Section number Title Page

Chapter 1

Introduction

1.1 Acronyms and abbreviations.............................................................................................................................................7

1.2 Related documentation......................................................................................................................................................10

1.3 Board features................................................................................................................................................................... 11

1.4 Block diagrams................................................................................................................................................................. 12

1.5 Board views...................................................................................................................................................................... 14

Chapter 2

Interfaces

2.1 DDR interface................................................................................................................................................................... 17

2.2 IFC interface..................................................................................................................................................................... 18

2.2.1 NOR flash memory.............................................................................................................................................. 19

2.2.2 NAND flash memory...........................................................................................................................................20

2.3 Serial interfaces.................................................................................................................................................................20

2.3.1 UART interface....................................................................................................................................................21

2.3.2 eSDHC interface.................................................................................................................................................. 21

2.3.3 DSPI interface......................................................................................................................................................23

2.4 Ethernet interface..............................................................................................................................................................24

2.4.1 Ethernet management interfaces.......................................................................................................................... 25

2.5 SerDes interface................................................................................................................................................................26

2.5.1 Mini-PCIe card.....................................................................................................................................................27

2.6 USB interface....................................................................................................................................................................28

2.7 I2C interface......................................................................................................................................................................29

Chapter 3

Power Supplies and CPLD Controller

3.1 Power supply block diagram.............................................................................................................................................33

3.2 Power supply operation.....................................................................................................................................................34

3.2.1 Power ON.............................................................................................................................................................34

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Section number Title Page

3.2.2 Power sequencing................................................................................................................................................ 34

3.3 CPLD controller................................................................................................................................................................35

3.3.1 CPLD features......................................................................................................................................................35

3.3.2 CPLD block diagram........................................................................................................................................... 36

3.3.3 CPLD registers.....................................................................................................................................................37

3.4 Power-on reset.................................................................................................................................................................. 38

3.4.1 Reset configuration signals.................................................................................................................................. 39

3.4.2 Reset architecture.................................................................................................................................................40

3.5 DDR supply...................................................................................................................................................................... 41

3.6 POVDD supply.................................................................................................................................................................42

Chapter 4

Clocks, Interrupts, and Temperature Monitoring

4.1 Clocking scheme...............................................................................................................................................................43

4.2 Clock frequency selection.................................................................................................................................................44

4.3 MPIC controller................................................................................................................................................................ 45

4.4 Temperature anode and cathode....................................................................................................................................... 45

Chapter 5

Debug and Input/Output

5.1 ARM/JTAG architecture...................................................................................................................................................47

5.2 CMSIS-DAP..................................................................................................................................................................... 48

5.3 GPIOs................................................................................................................................................................................49

Chapter 6

CPLD Programming

6.1 CPLD memory map / register definitions.........................................................................................................................51

6.1.1 CPLD major version register (CPLD_VER)....................................................................................................... 52

6.1.2 CPLD minor version register (CPLD_VER_SUB)............................................................................................. 52

6.1.3 PCBA version register (CPLD_PCBA_VER)..................................................................................................... 53

6.1.4 System reset register (CPLD_SYSTEM_RST)................................................................................................... 53

6.1.5 CPLD override physical switches enable register (CPLD_SOFT_MUX_ON)...................................................54

6.1.6 POR RCW source location register 1 (CPLD_REG_RCW_SRC1)....................................................................55

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Section number Title Page

6.1.7 POR RCW source location register 2 (CPLD_REG_RCW_SRC2)....................................................................56

6.1.8 Flash bank selection register (CPLD_REG_BANK)...........................................................................................56

6.1.9 System clock single-ended or differential input selection register (CPLD_SYSCLK_SEL)..............................57

6.1.10 UART1 output selection register (CPLD_UART_SEL)..................................................................................... 58

6.1.11 SerDes PLL1 reference clock input selection register (CPLD_SD1REFCLK_SEL)..........................................58

6.1.12 TDM clock or SDHC/USB selection register (CPLD_TDMCLK_MUX_SEL).................................................59

6.1.13 Status LED control register (CPLD_STATUS_LED).........................................................................................60

6.1.14 Global reset register (CPLD_GLOBAL_RST)....................................................................................................60

6.1.15 TDM riser card presence detection register (CPLD_TDMR_PRS_N)................................................................61

6.1.16 RTC clock assignment register (CPLD_REG_RTC)...........................................................................................61

6.1.17 EVDD control register (CPLD_EVDD_SEL)..................................................................................................... 62

6.1.18 CPLD register override physical switch SDHC_VS/SPI_CS0 enable register (CPLD_SOFT_VS_SPICS0)....62

6.1.19 SDHC_VS or SPI_CS0 selection register (CPLD_VS_SPICS0_SEL)...............................................................63

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Chapter 1

Introduction

The LS1043A reference design board (RDB) is a high-performance computing,

evaluation, and development platform for the QorIQ LS1043A processor. It can also be

used as a software development and debugging platform for the LS1043A processor. It

functions as a desktop computer and operates as a development and evaluation system.

The LS1043ARDB is lead-free and RoHS-compliant.

NOTE

Use the part number LS1043ARDB-PD to order the

LS1043ARDB.

You can perform the following operations using the LS1043ARDB onboard resources

and debugging devices:

• Upload and run code

• Set breakpoints

• Display memory and registers

• Connect and incorporate proprietary hardware into the target systems, using the

LS1043A processor as a host processor

• Use the LS1043ARDB as a demonstration tool

A software application developed for the LS1043ARDB can run with various input/

output data streams, for example, PCIe or XFI connections.

The board support package (BSP) is developed using the Linux operating system.

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1.1 Acronyms and abbreviations

The table below lists and describes the acronyms and abbreviations used in this

document.

Table 1-1. Acronyms and abbreviations

Acronym/abbreviation Description

AVDD Supply voltages for the core, platform, DDR, and SerDes PLLs

BCSR Board control and status register

BGA Ball grid array

BRDCFG Board configuration

CLKIN Clock input (interchangeable with SYSCLK)

COP Common on-chip processor

CPLD Complex programmable logic device

CTS Clear to send

CVDD Supply voltage for the DSPI block

DDR Double data rate

DIP Dual inline package

DMA Direct memory access

DRAM Dynamic random access memory

DSPI Deserial serial peripheral interface

DVDD Supply voltage for UART/I2C/DMA

EC Ethernet controllers

ECC Error checking and correction

EEPROM Electrically erasable programmable ROM

EMI Ethernet management interface

eMMC Embedded multimedia card

eSDHC Enhanced secure digital high capacity card

FCM NAND flash control machine

FMan Frame manager

FPGA Field programmable gate array

G1VDD Supply voltage for the DDR module

GETH Gigabit Ethernet (GbE)

GPCM General-purpose chip-select machine

GPINPUT General purpose input

GPIO General purpose input/output

HRESET Hard reset

I2C Inter-integrated circuit multi-master serial computer bus

IFC Integrated flash controller

IPL Initial program load

JTAG Joint Test Action Group (IEEE® standard 1149.1™)

LBMAP Local bus map

Table continues on the next page...

Acronyms and abbreviations

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Table 1-1. Acronyms and abbreviations (continued)

Acronym/abbreviation Description

LDO Low-dropout

LED Light-emitting diode

LSB Least significant bit

LVDD Supply voltage for the GETH block

MAC Medium access control

MMC Multimedia card

MSB Most significant bit

MSD Mass storage device

OCM Offline Configuration Manager (FPGA-embedded)

OVDD Supply voltage for general purpose I/O

PCBA Printed circuit board assembly

PLL Phase-locked loop

PMIC Power management integrated circuit

POR Power-on reset

POVDD Security fuse programming override supply voltage (PROG_SFP)

ppm Parts per million

PROMJet Memory emulator by EmuTec Inc.

QSGMII Quad serial gigabit media-independent interface

RCW Reset configuration word

REFCLK Reference clock (clock synthesizer input value)

RGMII Reduced gigabit media-independent interface

ROM Read-only memory

RTC Real-time clock

RTS Request to send

SATA Serial advanced technology attachment

SCL/SCLK Serial clock

SD Secure digital card

SDHC Secure digital high capacity card

SDRAM Synchronous dynamic random access memory

SDREFCLK SerDes reference clock

SERCLK SerDes clock

SerDes (SRDS) Serializer/deserializer, for example, PEX, XAUI, SGMII, SATA, sRIO,

AURORA, and XFI

SGMII Serial gigabit media-independent interface

SIP Secure interfaces and power

SLAC Subscriber line access controller

SLC Single-level cell

SLIC Subscriber line interface controller

SMB Subminiature version B connector

SPD Serial presence detect

Table continues on the next page...

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Table 1-1. Acronyms and abbreviations (continued)

Acronym/abbreviation Description

SPI Serial peripheral interface

SRAM Static random-access memory

S1VDD Supply voltage for SerDes1 and SerDes2 core logic

SYSCLK System clock

TAP Test access port, for example, USB TAP or Ethernet TAP

TESTSEL Test select

TH_VDD Supply voltage for the Thermal Monitor unit

TRIG_IN/OUT Trigger input/output

TSEC Three-speed Ethernet controller

UART Universal asynchronous receiver/transmitter

uDIMM Unbuffered dual inline memory module form factor

USB Universal serial bus

USBCLK USB clock

VDD Supply voltage for core and platform

TA_BB_VDD Supply voltage for low power security monitor

XAUI Ten gigabit attachment unit interface

XVDD Supply voltage for SerDes1 and SerDes2 transceivers

1.2 Related documentation

This table lists and describes the additional documents available for more information on

the LS1043ARDB.

Table 1-2. Related documentation

Document Description

QorIQ LS1043ARDB Getting Started Guide

(LS1043ARDBGSG)

Describes the LS1043ARDB hardware kit, provides settings for the

onboard switches, connectors, jumpers, and LEDs, and explains the

basic board operations in a step-by-step manner

QorIQ LS1043A Reference Manual (LS1043ARM) Provides a detailed description on the LS1043A multicore processor and

its features, such as memory map, serial interfaces, power supply, chip

features, and clock information

QorIQ LS1043A Data Sheet Contains information on the LS1043A pin assignments, electrical

characteristics, hardware design considerations, package information,

and ordering information

LS1043A Chip Errata Provides details of all known silicon errata for the LS1043A processor

NOTE

Some of the documents listed in the table above, may be

available only under a non-disclosure agreement (NDA). To

Related documentation

QorIQ LS1043A Reference Design Board Reference Manual, Rev. 4, 11/2017

10 NXP Semiconductors

request access to such documents, contact your local NXP field

applications engineer or sales representative.

1.3 Board features

The table below lists the features of the LS1043ARDB.

Table 1-3. LS1043ARDB features

LS1043ARDB feature Specification Description

Processor support Core processors 4x64-bit up to 1.6 GHz ARM® Cortex®-v8 A53 cores

High-speed serial ports (SerDes) • Supports 4 lanes, up to 10.3125 GHz SerDes

• Supports PCIe 2.0, QSGMII, and XFI

• Two PCIe connectors supporting:

• Mini-PCIe card

• Standard PCIe card

• X1 RJ45 connector for Ethernet 10G support

• X4 RJ45 connector for QSGMII support

DDR • Supports 2 GB DDR4 SDRAM discrete devices

• 32-bit DDR4 bus

• Supports data rates of up to 1600 MT/s

USB 3.0 • Two super-speed USB 3.0 type A ports

• Supports x1 USB 2.0 connection on the mini-PCIe

connector

IFC • One 128 MB NOR flash 16-bit data bus (1.8 V)

• One 512 MB SLC NAND flash with ECC support (1.8

V)

• CPLD connection: 8-bit registers in CPLD to configure

some mux/demux selections

eSDHC • SDHC port connects directly to a full SD/MMC slot.

DSPI • 16 MB high-speed flash memory (up to 108 MHz in

the Single-Transfer Rate mode)

DUART • One RJ45 to DB9 connector with two UART ports

• UART1 is routed to CMSISDAP circuit and supports

USB port to access serial port as console

Package • 21 x 21 mm, 621 flip-chip, plastic-ball, grid array (FC-

PBGA)

System logic CPLD • Manages system power and reset sequencing

• Latches IFC address/data multiplexed signals

• Controls signal muxing/demuxing

Clock SYSCLK • Supports single-ended SYSCLK, DDRCLK clock

input, with default value as 100 MHz

• Supports single-source differential DIFF_SYCLK_/

DIFF_SYSCLK_N, 100 MHz

SerDes • Provides clocks to all SerDes blocks and slots

• 100 MHz or 156.25 MHz for PLL1

• 100 MHz for PLL2

RTC • Supports 32.768 kHz for RTC

Table continues on the next page...

Chapter 1 Introduction

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Table 1-3. LS1043ARDB features (continued)

LS1043ARDB feature Specification Description

Power One dedicated programmable

regulator supplying the LS1043A

core and DDR power domains.

Power supply details for the LS1043ARDB are given below:

• 1.0 V for core VDD, USB_SVDD, and USB_SDVDD

• 1.2 V for GVDD

• 1.8 V for LS1043A PROG_SFP and PROG_MTR

(POVDD)

• 3.3 V / 1.8 V for CPLD

• 1.35 V for XVDD

• 1.0 V for S1VDD

• 1.8 V for LS1043A general I/O

• 3.3 V for UART/I2C

• 3.3 V for USB HVDD

• 0.6 V for DDR4 VTT/VREF

• 3.3 V / 1.8 V for eSDHC

• 1.0 V for security monitor (TA_BB_VDD)

NOTE: For core VDD, USB_SVDD, USB_SDVDD, and

TA_BB_VDD, the LS1043A processor supports 1.0

V as well as 0.9 V; however, the LS1043ARDB

only supports 1.0 V.

1.4 Block diagrams

The figure below shows the LS1043A processor block diagram.

Block diagrams

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Watchpoint

Cross

Trigger

Trust Zone

Power Management

IFC, QuadSPI, SPI

2x DUART

32-bit

DDR3L/4

Memory Controller

Real Time Debug

Perf

Monitor

4x I2C, 4x GPIO

Secure Boot

8x FlexTimer

Queue

Manager

Buffer

Manager

Parse, classify,

distribute

1/2.5/10G

PCI Express 2.0

SATA 3.0

Trace

4-Lane, 10 GHz SerDes

ARM Cortex-

A53 64b Cores

1G

SMMUs

3x USB3.0 w/PHY

CCI-400™ Coherency Fabric

32 KB

D-Cache

32 KB

I-Cache

ARM Cortex-

A53 64b Cores

32 KB

D-Cache

32 KB

I-Cache

ARM Cortex-

A53 64b Cores

32 KB

D-Cache

32 KB

I-Cache

ARM Cortex-

A53 64b Cores

1G

1G 1/2.5G

1G

QUICC Engine

PCI Express 2.0

Frame Manager

SD/SDIO/eMMC

DMA

6x LPUART

Core Complex

Accelerators and Memory Control

Basic Peripherals, Interconnect and Debug

Networking Elements

Security

Engine

(SEC)

DPAA Hardware

Arm® Cortex®-A53

64-bit Core

32 KB

D-Cache

32 KB

I-Cache

1 MB L2 - Cache

Figure 1-1. LS1043A processor block diagram

The figure below shows the LS1043ARDB block diagram.

Chapter 1 Introduction

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NXP Semiconductors 13

DUART

QE

For PMC plug-in card

T1/E1 QE

connector

SerDes

lane

USB 3.0

SerDes

lane

PCle X1

USB 3.0

Type A X2

Mini PCle

USB

PCle x1

Board

EEPROM

RTC

Board components

Connectors

Expansion modules

+12 V PSU

I2C

DPAA Ethernet

SPI

COP

Clocks

RJ45

JTAG

header

SPl flash

16 MB

10G

PHY

RGMII

PHY

RGMII

PHY

Quad

PHY

Full SD

slot

CPLD

512 MB

NAND

128 MB

NOR

DDR4

2 GB

x32

DDR

IFC

LS1043A

SDHC

USB 3.0

RJ45

I2C

RJ45

XFI

USB 2.0

RS-232 Kinetis

K22 MCU UART1

RS-232

serial

Figure 1-2. LS1043ARDB block diagram

1.5 Board views

The figure below shows the LS1043ARDB top view.

Board views

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14 NXP Semiconductors

J4

Up: UART2

Down: UART1

SW1

Reset

switch

P1

Up: RGMII2

Down: RGMII1

J3

10G port

P3

Up: QSGMII.P1

Down: QSGMII.P0

J2

Up: USB2

Down: USB1

J1

+12 V power jack

SW2

Power switch

P2

Up: QSGMII.P3

Down: QSGMII.P2

J8

CPLD JTAG

P4

PCIe slot

P5

Mini-PCIe slot

J11

TDM slot

J17

Chassis fan

J16

CPU JTAG

J18

K22 JTAG

J20

Mini-USB to UART1

BT1

RTC battery

Figure 1-3. LS1043ARDB top view

The figure below shows the LS1043ARDB bottom view.

Chapter 1 Introduction

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Figure 1-4. LS1043ARDB bottom view

Board views

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Chapter 2

Interfaces

The LS1043ARDB architecture is primarily determined by the LS1043A processor with

the need to evaluate LS1043A processor features and to test its ability to deliver an easily

usable off-the-shelf software development platform. Following are the main interfaces

that form the LS1043ARDB architecture:

•DDR interface

•IFC interface

•Serial interfaces

•Ethernet interface

•SerDes interface

•USB interface

•I2C interface

2.1 DDR interface

The LS1043ARDB supports high-speed DRAM with 2 GB double data rate 4 (DDR4)

SDRAM discrete devices (32-bit bus). The memory interface includes all necessary

termination and I/O powers. It is routed such that maximum performance of the memory

bus can be achieved. The figure below shows the DDR memory architecture.

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LS1043A

DDR4

(MT40A512M8)

DDR4_A[0:14], BA[0:2]

MRAS_B, MCAS_B, MWE_B

MCK, MCK_B, MCKE[0:1], MODT[0:1]

MCS[0:1]_B

MDQ[0:31]

MDQS[0:3], MDQS[0:3]_B

MDM[0:3]

Figure 2-1. DDR memory architecture

For power supply details for the DDR interface, see DDR supply.

2.2 IFC interface

The LS1043ARDB integrated flash controller (IFC) has the following features:

• Supports 1.8 V I/O voltage

• Implements little endian support

• Supports 28-bit addressing and 16-bit data bus

• Supports GPCM, NOR, and NAND FCM

• Supports the following IFC clients on the LS1043ARDB:

• NAND flash (async/sync - ONFI 1.0 compatible)

• NOR flash 16-bit

The figure below shows the IFC block diagram.

IFC interface

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LS1043A

NOR

(MT28EW01G)

IFC_AD[0:15]

NAND

(MT29F4G08ABB

DAH4)

IFC_ADDR[16:27]

IFC_AD[0:7]

IFC

CPLD

NOR_CS_B

NOR_RB_B

NAND_CS_B

NAND_RB_B

IFC_CLE

IFC_AD[0:15]

IFC_CS[0:3]_B

IFC_WE_B, IFC_OE_B, IFC_AVD

IFC_CLE, IFC_TE, IFC_CLK0

IFC_RB[0:1]_B

Figure 2-2. IFC block diagram

LS1043ARDB uses a combination of the IFC chip select signals and DIP switches to

allow dynamic reconfiguration of the IFC boot device (which addresses IFC_CS_B[0]

only).

The table below summarizes the IFC chip select routing.

Table 2-1. IFC chip select device mapping

SW4[1:8]+SW5[1]= Chip select Memory Data width

000100101 CS0 NOR flash 16 bits

CS1 NAND flash 8 bits

CS2 CPLD registers 8 bits

100000110 CS0 NAND flash 8 bits

CS1 NOR flash 16 bits

CS2 CPLD registers 8 bits

Chapter 2 Interfaces

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2.2.1 NOR flash memory

The LS1043ARDB has a Micron NOR flash memory (MT28EW01G) with 128 MB size

and 16-bit data bus. The NOR flash memory is powered from a 3.3 V power supply but

the signals are driven with the 1.8 V I/O level. The NOR flash memory is controlled by

the NOR IFC machine.

Flash controls are explained below:

• IFC OE_B controls flash OE, whereas IFC WE0_B controls the flash WE_B signal.

• Flash RY/BY_B output signal shows the ready/busy status of the flash. This signal is

connected to the CPLD.

• IFC_NOR_CS_B driven by CPLD selects either IFC_CS0_B or IFC_CS1_B to the

NOR flash memory based on CFG_RCW_SRC[0:8].

CPLD-generated signals are used to re-arrange internal addresses according to user

configuration options CFG_RCW_SRC[0:8]. For details, see CPLD Programming.

2.2.2 NAND flash memory

The LS1043ARDB has an ONFI 1.0 compatible Micron NAND flash memory

(MT29F4G08ABBDAH4-ITX) with 512 MB size and 8-bit data bus. The NAND flash

memory is powered from a 1.8 V power supply. It has signals going to and coming from

the LS1043A processor directly. The NAND flash memory is controlled by the LS1043A

IFC FCM machine.

Flash controls are explained below:

• Flash R/B_B output indicates the status of the NAND operation. This open drain

output connects to complex programmable logic device (CPLD).

• IFC_NAND_CS_B from CPLD drives the NAND flash according to

CFG_RCW_SRC[0:8]. For details, see CPLD Programming.

2.3 Serial interfaces

The LS1043ARDB has several serial interfaces, such as RS-232, DSPI, eSDHC/eMMC,

and I2C. This section describes the following main serial interfaces used in the

LS1043ARDB:

•UART interface

•eSDHC interface

•DSPI interface

Serial interfaces

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