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K80 Sub-Family Reference Manual
Supports: MK80FN256VDC15, MK80FN256VLL15,
MK80FN256VLQ15, MK80FN256CAx15
Document Number: K80P121M150SF5RM
Rev. 4, 09/2015
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Contents
Section number Title Page
Chapter 1
About This Manual
1.1 Audience....................................................................................................................................................................... 25
1.2 Organization..................................................................................................................................................................25
1.3 Module descriptions......................................................................................................................................................25
1.4 Register descriptions.....................................................................................................................................................28
1.5 Conventions.................................................................................................................................................................. 29
Chapter 2
Introduction
2.1 Overview.......................................................................................................................................................................31
2.2 Block Diagram..............................................................................................................................................................31
2.3 Module Functional Categories......................................................................................................................................32
2.4 Orderable part numbers.................................................................................................................................................40
Chapter 3
Core Overview
3.1 Introduction...................................................................................................................................................................43
3.2 Interrupt priority levels................................................................................................................................................. 45
3.3 Non-maskable interrupt................................................................................................................................................ 45
3.4 Interrupt channel assignments.......................................................................................................................................46
3.5 AWIC overview............................................................................................................................................................50
3.6 Wake-up sources...........................................................................................................................................................50
Chapter 4
Memories and Memory Interfaces
4.1 Flash memory types......................................................................................................................................................51
4.2 Flash Memory Sizes......................................................................................................................................................51
4.3 Flash Security............................................................................................................................................................... 51
4.4 Flash Modes..................................................................................................................................................................51
4.5 Erase All Flash Contents...............................................................................................................................................52
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4.6 FTF_FOPT Register..................................................................................................................................................... 52
4.7 SRAM sizes.................................................................................................................................................................. 52
4.8 SRAM accesses.............................................................................................................................................................53
4.9 SRAM retention in low power modes.......................................................................................................................... 54
4.10 QuadSPI memory interface...........................................................................................................................................54
4.11 System Register file......................................................................................................................................................54
4.12 VBAT register file........................................................................................................................................................ 54
Chapter 5
Memory Map
5.1 Introduction...................................................................................................................................................................57
5.2 System memory map.....................................................................................................................................................57
5.3 Flash Memory Map.......................................................................................................................................................59
5.4 Flash Access Control Introduction................................................................................................................................60
5.5 SRAM memory map.....................................................................................................................................................61
5.6 Peripheral bridge (AIPS-Lite0 and AIPS-Lite1) memory maps...................................................................................61
5.7 Private Peripheral Bus (PPB) memory map..................................................................................................................69
Chapter 6
Clock Distribution using MCG
6.1 Introduction...................................................................................................................................................................71
6.2 Programming model......................................................................................................................................................71
6.3 High-Level device clocking diagram............................................................................................................................72
6.4 Clock definitions...........................................................................................................................................................73
6.5 Internal clocking requirements..................................................................................................................................... 76
6.6 Clock Gating.................................................................................................................................................................78
6.7 Module clocks...............................................................................................................................................................78
Chapter 7
Reset and Boot
7.1 Introduction...................................................................................................................................................................89
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7.2 Reset..............................................................................................................................................................................89
7.3 Boot...............................................................................................................................................................................97
Chapter 8
Kinetis ROM Bootloader
8.1 Chip-Specific Information............................................................................................................................................ 101
8.2 Introduction...................................................................................................................................................................102
8.3 Functional Description..................................................................................................................................................104
8.4 Peripherals Supported................................................................................................................................................... 147
8.5 Get/SetProperty Command Properties..........................................................................................................................166
8.6 SB File Decryption Support..........................................................................................................................................170
8.7 Kinetis Bootloader Status Error Codes.........................................................................................................................172
Chapter 9
Power Management
9.1 Introduction...................................................................................................................................................................175
9.2 Clocking modes............................................................................................................................................................ 175
9.3 Power Modes Description.............................................................................................................................................179
9.4 Entering and exiting power modes............................................................................................................................... 181
9.5 Power mode transitions.................................................................................................................................................182
9.6 Power modes shutdown sequencing............................................................................................................................. 183
9.7 Flash Program Restrictions...........................................................................................................................................184
9.8 Module Operation in Low Power Modes......................................................................................................................184
Chapter 10
Flash Security Measures & Module Interactions
10.1 Introduction...................................................................................................................................................................189
10.2 Flash Security............................................................................................................................................................... 189
10.3 Security Interactions with other Modules.....................................................................................................................190
Chapter 11
Debug
11.1 Introduction...................................................................................................................................................................191
11.2 Cortex-M4 Debug Topology with CAU.......................................................................................................................192
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11.3 Debug Components.......................................................................................................................................................192
11.4 The Debug Port.............................................................................................................................................................193
11.5 Debug Port Pin Descriptions.........................................................................................................................................195
11.6 System TAP connection................................................................................................................................................195
11.7 JTAG status and control registers.................................................................................................................................196
11.8 Debug Resets................................................................................................................................................................ 200
11.9 AHB-AP........................................................................................................................................................................201
11.10 ITM............................................................................................................................................................................... 201
11.11 Core Trace Connectivity with ETM............................................................................................................................. 202
11.12 Embedded Trace Macrocell v3.5 (ETM)......................................................................................................................203
11.13 TPIU..............................................................................................................................................................................203
11.14 DWT............................................................................................................................................................................. 203
11.15 Debug in Low Power Modes........................................................................................................................................ 204
11.16 Debug & Security......................................................................................................................................................... 205
Chapter 12
Signal Multiplexing and Signal Descriptions
12.1 Signal Multiplexing Introduction..................................................................................................................................207
12.2 Signal Multiplexing Integration....................................................................................................................................207
12.3 Pinout............................................................................................................................................................................209
12.4 Module Signal Description Tables................................................................................................................................221
Chapter 13
Port Control and Interrupts (PORT)
13.1 Introduction...................................................................................................................................................................237
13.2 Overview.......................................................................................................................................................................237
13.3 External signal description............................................................................................................................................239
13.4 Detailed signal description............................................................................................................................................239
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13.5 Memory map and register definition.............................................................................................................................239
13.6 Functional description...................................................................................................................................................252
Chapter 14
System Integration Module (SIM)
14.1 Introduction...................................................................................................................................................................257
14.2 Memory map and register definition.............................................................................................................................258
14.3 Functional description...................................................................................................................................................297
Chapter 15
EMV SIM
15.1 Chip-specific EMVSIM information............................................................................................................................ 299
15.2 Introduction...................................................................................................................................................................299
15.3 Block Diagram..............................................................................................................................................................300
15.4 Design Overview.......................................................................................................................................................... 301
15.5 Signal Description.........................................................................................................................................................303
15.6 Memory Map and Registers..........................................................................................................................................303
15.7 Functional Description..................................................................................................................................................329
Chapter 16
Reset Control Module (RCM)
16.1 Introduction...................................................................................................................................................................353
16.2 Reset memory map and register descriptions............................................................................................................... 353
Chapter 17
System Mode Controller (SMC)
17.1 Introduction...................................................................................................................................................................365
17.2 Modes of operation....................................................................................................................................................... 365
17.3 Memory map and register descriptions.........................................................................................................................367
17.4 Functional description...................................................................................................................................................373
Chapter 18
Power Management Controller (PMC)
18.1 Introduction...................................................................................................................................................................387
18.2 Features.........................................................................................................................................................................387
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18.3 Low-voltage detect (LVD) system................................................................................................................................387
18.4 High-voltage detect (HVD) system.............................................................................................................................. 389
18.5 I/O retention..................................................................................................................................................................390
18.6 Memory map and register descriptions.........................................................................................................................390
Chapter 19
Low-Leakage Wakeup Unit (LLWU)
19.1 Chip-specific LLWU information.................................................................................................................................397
19.2 Introduction...................................................................................................................................................................398
19.3 LLWU signal descriptions............................................................................................................................................ 401
19.4 Memory map/register definition................................................................................................................................... 402
19.5 Functional description...................................................................................................................................................426
Chapter 20
Miscellaneous Control Module (MCM)
20.1 Introduction...................................................................................................................................................................429
20.2 Memory map/register descriptions............................................................................................................................... 429
20.3 Functional description...................................................................................................................................................442
Chapter 21
Crossbar Switch (AXBS)
21.1 Chip-specific AXBS information................................................................................................................................. 443
21.2 Introduction...................................................................................................................................................................444
21.3 Memory Map / Register Definition...............................................................................................................................445
21.4 Functional Description..................................................................................................................................................451
21.5 Initialization/application information........................................................................................................................... 455
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Chapter 22
Peripheral Bridge (AIPS-Lite)
22.1 Chip-specific AIPS-Lite information............................................................................................................................457
22.2 Introduction...................................................................................................................................................................458
22.3 Memory map/register definition................................................................................................................................... 458
22.4 Functional description...................................................................................................................................................472
Chapter 23
Memory Protection Unit (MPU)
23.1 Chip-specific MPU information................................................................................................................................... 475
23.2 Introduction...................................................................................................................................................................477
23.3 Overview.......................................................................................................................................................................477
23.4 Memory map/register definition................................................................................................................................... 479
23.5 Functional description...................................................................................................................................................492
23.6 Initialization information.............................................................................................................................................. 495
23.7 Application information................................................................................................................................................495
Chapter 24
Bit Manipulation Engine2 (BME2)
24.1 Introduction...................................................................................................................................................................499
24.2 Memory map and register definition.............................................................................................................................501
24.3 Functional description...................................................................................................................................................502
24.4 Application information................................................................................................................................................515
Chapter 25
Direct Memory Access Multiplexer (DMAMUX)
25.1 Chip-specific DMAMUX information......................................................................................................................... 517
25.2 Introduction...................................................................................................................................................................521
25.3 External signal description............................................................................................................................................523
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25.4 Memory map/register definition................................................................................................................................... 523
25.5 Functional description...................................................................................................................................................525
25.6 Initialization/application information........................................................................................................................... 529
Chapter 26
Enhanced Direct Memory Access (eDMA)
26.1 Introduction...................................................................................................................................................................533
26.2 Modes of operation....................................................................................................................................................... 536
26.3 Memory map/register definition................................................................................................................................... 537
26.4 Functional description...................................................................................................................................................615
26.5 Initialization/application information........................................................................................................................... 625
Chapter 27
External Watchdog Monitor (EWM)
27.1 Chip-specific EWM information.................................................................................................................................. 641
27.2 Introduction...................................................................................................................................................................642
27.3 EWM Signal Descriptions............................................................................................................................................ 644
27.4 Memory Map/Register Definition.................................................................................................................................645
27.5 Functional Description..................................................................................................................................................649
Chapter 28
Watchdog Timer (WDOG)
28.1 Chip-specific WDOG information................................................................................................................................653
28.2 Introduction...................................................................................................................................................................654
28.3 Features.........................................................................................................................................................................654
28.4 Functional overview......................................................................................................................................................655
28.5 Testing the watchdog.................................................................................................................................................... 660
28.6 Backup reset generator..................................................................................................................................................663
28.7 Generated resets and interrupts.....................................................................................................................................663
28.8 Memory map and register definition.............................................................................................................................664
28.9 Watchdog operation with 8-bit access.......................................................................................................................... 671
28.10 Restrictions on watchdog operation..............................................................................................................................672
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Chapter 29
Multipurpose Clock Generator (MCG)
29.1 Chip-specific MCG information...................................................................................................................................675
29.2 Introduction...................................................................................................................................................................675
29.3 External Signal Description.......................................................................................................................................... 679
29.4 Memory Map/Register Definition.................................................................................................................................679
29.5 Functional description...................................................................................................................................................693
29.6 Initialization / Application information........................................................................................................................ 701
Chapter 30
Oscillator (OSC)
30.1 Chip-specific OSC information.................................................................................................................................... 713
30.2 Introduction...................................................................................................................................................................713
30.3 Features and Modes...................................................................................................................................................... 713
30.4 Block Diagram..............................................................................................................................................................714
30.5 OSC Signal Descriptions.............................................................................................................................................. 715
30.6 External Crystal / Resonator Connections.................................................................................................................... 715
30.7 External Clock Connections......................................................................................................................................... 716
30.8 Memory Map/Register Definitions...............................................................................................................................717
30.9 Functional Description..................................................................................................................................................719
30.10 Reset..............................................................................................................................................................................723
30.11 Low power modes operation.........................................................................................................................................724
30.12 Interrupts.......................................................................................................................................................................724
Chapter 31
RTC Oscillator (OSC32K)
31.1 Introduction...................................................................................................................................................................725
31.2 RTC Signal Descriptions.............................................................................................................................................. 726
31.3 External Crystal Connections....................................................................................................................................... 727
31.4 Memory Map/Register Descriptions.............................................................................................................................727
31.5 Functional Description..................................................................................................................................................727
31.6 Reset Overview.............................................................................................................................................................728
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31.7 Interrupts.......................................................................................................................................................................728
Chapter 32
Local Memory Controller
32.1 Chip-specific LMEM information................................................................................................................................ 729
32.2 Introduction...................................................................................................................................................................730
32.3 Memory Map/Register Definition.................................................................................................................................733
32.4 Functional Description..................................................................................................................................................750
Chapter 33
Flash Memory Controller (FMC)
33.1 Chip-specific FMC information....................................................................................................................................761
33.2 Introduction...................................................................................................................................................................761
33.3 Modes of operation....................................................................................................................................................... 762
33.4 External signal description............................................................................................................................................762
33.5 Memory map and register descriptions.........................................................................................................................763
33.6 Functional description...................................................................................................................................................785
33.7 Initialization and application information.....................................................................................................................798
Chapter 34
Flash Memory Module (FTFA)
34.1 Introduction...................................................................................................................................................................799
34.2 External Signal Description.......................................................................................................................................... 802
34.3 Memory Map and Registers..........................................................................................................................................802
34.4 Functional Description..................................................................................................................................................819
Chapter 35
Synchronous DRAM Controller Module (SDRAM)
35.1 Chip-specific SDRAM information..............................................................................................................................849
35.2 Introduction...................................................................................................................................................................850
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35.3 Overview.......................................................................................................................................................................850
35.4 SDRAM Controller Operation......................................................................................................................................852
35.5 General Synchronous Operation Guidelines.................................................................................................................860
35.6 Initialization Sequence..................................................................................................................................................867
35.7 SDRAM Example.........................................................................................................................................................869
Chapter 36
Quad Serial Peripheral Interface (QuadSPI)
36.1 Chip-specific QuadSPI information..............................................................................................................................875
36.2 Introduction...................................................................................................................................................................881
36.3 External Signal Description.......................................................................................................................................... 886
36.4 Memory Map and Register Definition..........................................................................................................................889
36.5 Interrupt Signals............................................................................................................................................................943
36.6 Functional Description..................................................................................................................................................944
36.7 Initialization/Application Information..........................................................................................................................968
36.8 Byte Ordering - Endianness..........................................................................................................................................979
36.9 Serial Flash Devices......................................................................................................................................................982
36.10 Sampling of Serial Flash Input Data.............................................................................................................................991
36.11 Data Input Hold Requirement of Flash.........................................................................................................................1004
Chapter 37
External Bus Interface (FlexBus)
37.1 Chip-specific Flexbus information............................................................................................................................... 1007
37.2 Introduction...................................................................................................................................................................1009
37.3 Signal descriptions........................................................................................................................................................1010
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37.4 Memory Map/Register Definition.................................................................................................................................1012
37.5 Functional description...................................................................................................................................................1019
37.6 Initialization/Application Information..........................................................................................................................1055
Chapter 38
Cyclic Redundancy Check (CRC)
38.1 Introduction...................................................................................................................................................................1057
38.2 Memory map and register descriptions.........................................................................................................................1058
38.3 Functional description...................................................................................................................................................1061
Chapter 39
Memory-Mapped Cryptographic Acceleration Unit (MMCAU)
39.1 Overview.......................................................................................................................................................................1067
39.2 Features.........................................................................................................................................................................1067
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39.3 Register definition.........................................................................................................................................................1068
39.4 Functional description...................................................................................................................................................1071
39.5 Application/initialization information.......................................................................................................................... 1079
Chapter 40
True Random Number Generator
40.1 Standalone True Random Number Generator (SA-TRNG)..........................................................................................1081
Chapter 41
Analog-to-Digital Converter (ADC)
41.1 Chip-specific ADC information....................................................................................................................................1135
41.2 Introduction...................................................................................................................................................................1139
41.3 ADC signal descriptions............................................................................................................................................... 1142
41.4 Memory map and register definitions...........................................................................................................................1144
41.5 Functional description...................................................................................................................................................1166
41.6 Initialization information.............................................................................................................................................. 1184
41.7 Application information................................................................................................................................................1186
Chapter 42
Comparator (CMP)
42.1 Chip-specific Comparator information.........................................................................................................................1193
42.2 Introduction...................................................................................................................................................................1194
42.3 Memory map/register definitions..................................................................................................................................1199
42.4 Functional description...................................................................................................................................................1205
42.5 CMP interrupts..............................................................................................................................................................1218
42.6 DMA support................................................................................................................................................................ 1218
42.7 CMP Asynchronous DMA support...............................................................................................................................1219
42.8 Digital-to-analog converter...........................................................................................................................................1220
42.9 DAC functional description.......................................................................................................................................... 1220
42.10 DAC resets....................................................................................................................................................................1221
42.11 DAC clocks...................................................................................................................................................................1221
42.12 DAC interrupts..............................................................................................................................................................1221
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Chapter 43
Voltage Reference (VREFV1)
43.1 Chip-specific VREF information..................................................................................................................................1223
43.2 Introduction...................................................................................................................................................................1223
43.3 Memory Map and Register Definition..........................................................................................................................1226
43.4 Functional Description..................................................................................................................................................1228
43.5 Initialization/Application Information..........................................................................................................................1231
Chapter 44
12-bit Digital-to-Analog Converter (DAC)
44.1 Chip-specific DAC information....................................................................................................................................1233
44.2 Introduction...................................................................................................................................................................1234
44.3 Features.........................................................................................................................................................................1234
44.4 Block diagram...............................................................................................................................................................1234
44.5 Memory map/register definition................................................................................................................................... 1235
44.6 Functional description...................................................................................................................................................1241
Chapter 45
FlexTimer Module (FTM)
45.1 Chip-specific FTM information....................................................................................................................................1245
45.2 Introduction...................................................................................................................................................................1251
45.3 FTM signal descriptions............................................................................................................................................... 1256
45.4 Memory map and register definition.............................................................................................................................1256
45.5 Functional description...................................................................................................................................................1306
45.6 Reset overview..............................................................................................................................................................1384
45.7 FTM Interrupts..............................................................................................................................................................1385
45.8 Initialization Procedure.................................................................................................................................................1386
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Chapter 46
Timer/PWM Module (TPM)
46.1 Chip-specific TPM information....................................................................................................................................1389
46.2 Introduction...................................................................................................................................................................1391
46.3 TPM Signal Descriptions..............................................................................................................................................1393
46.4 Memory Map and Register Definition..........................................................................................................................1394
46.5 Functional description...................................................................................................................................................1409
Chapter 47
Low-Power Timer (LPTMR)
47.1 Chip-specific LPTMR information...............................................................................................................................1433
47.2 Introduction...................................................................................................................................................................1434
47.3 LPTMR signal descriptions.......................................................................................................................................... 1435
47.4 Memory map and register definition.............................................................................................................................1436
47.5 Functional description...................................................................................................................................................1440
Chapter 48
Carrier Modulator Transmitter (CMT)
48.1 Chip-specific CMT information................................................................................................................................... 1445
48.2 Introduction...................................................................................................................................................................1445
48.3 Features.........................................................................................................................................................................1446
48.4 Block diagram...............................................................................................................................................................1446
48.5 Modes of operation....................................................................................................................................................... 1447
48.6 CMT external signal descriptions................................................................................................................................. 1449
48.7 Memory map/register definition................................................................................................................................... 1450
48.8 Functional description...................................................................................................................................................1460
48.9 CMT interrupts and DMA............................................................................................................................................ 1469
Chapter 49
Programmable Delay Block (PDB)
49.1 Chip-specific PDB information.................................................................................................................................... 1471
49.2 Introduction...................................................................................................................................................................1474
49.3 PDB signal descriptions................................................................................................................................................1478
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49.4 Memory map and register definition.............................................................................................................................1478
49.5 Functional description...................................................................................................................................................1488
49.6 Application information................................................................................................................................................1494
Chapter 50
Periodic Interrupt Timer (PIT)
50.1 Chip-specific PIT information...................................................................................................................................... 1495
50.2 Introduction...................................................................................................................................................................1496
50.3 Signal description..........................................................................................................................................................1497
50.4 Memory map/register description.................................................................................................................................1497
50.5 Functional description...................................................................................................................................................1502
50.6 Initialization and application information.....................................................................................................................1504
50.7 Example configuration for chained timers....................................................................................................................1505
50.8 Example configuration for the lifetime timer............................................................................................................... 1506
Chapter 51
Real Time Clock (RTC)
51.1 Chip-specific RTC information.................................................................................................................................... 1509
51.2 Introduction...................................................................................................................................................................1509
51.3 Register definition.........................................................................................................................................................1511
51.4 Functional description...................................................................................................................................................1523
Chapter 52
Universal Serial Bus Full Speed OTG Controller (USBFSOTG)
52.1 Chip-specific USBFSOTG information........................................................................................................................1529
52.2 Introduction...................................................................................................................................................................1534
52.3 Functional description...................................................................................................................................................1537
52.4 Programmers interface..................................................................................................................................................1540
52.5 Memory map/Register definitions................................................................................................................................ 1547
52.6 OTG and Host mode operation.....................................................................................................................................1576
52.7 Host Mode Operation Examples...................................................................................................................................1577
52.8 On-The-Go operation....................................................................................................................................................1580
52.9 Device mode IRC48M operation..................................................................................................................................1583
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Chapter 53
USB Device Charger Detection Module (USBDCD)
53.1 Preface...........................................................................................................................................................................1585
53.2 Introduction...................................................................................................................................................................1586
53.3 Module signal descriptions........................................................................................................................................... 1589
53.4 Memory map/Register definition..................................................................................................................................1589
53.5 Functional description...................................................................................................................................................1599
53.6 Initialization information.............................................................................................................................................. 1615
53.7 Application information................................................................................................................................................1615
Chapter 54
USB Voltage Regulator
54.1 Introduction...................................................................................................................................................................1617
54.2 USB Voltage Regulator Module Signal Descriptions.................................................................................................. 1619
Chapter 55
Serial Peripheral Interface (SPI)
55.1 Chip-specific SPI information...................................................................................................................................... 1621
55.2 Introduction...................................................................................................................................................................1624
55.3 Module signal descriptions........................................................................................................................................... 1630
55.4 Memory Map/Register Definition.................................................................................................................................1632
55.5 Functional description...................................................................................................................................................1654
55.6 Initialization/application information........................................................................................................................... 1677
Chapter 56
Inter-Integrated Circuit (I2C)
56.1 Chip-specific I2C information...................................................................................................................................... 1683
56.2 Introduction...................................................................................................................................................................1683
56.3 I2C signal descriptions..................................................................................................................................................1685
56.4 Memory map/register definition................................................................................................................................... 1686
56.5 Functional description...................................................................................................................................................1700
56.6 Initialization/application information........................................................................................................................... 1716
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Chapter 57
Low Power Universal asynchronous receiver/transmitter (LPUART)
57.1 Chip-specific LPUART information.............................................................................................................................1719
57.2 Introduction...................................................................................................................................................................1720
57.3 Register definition.........................................................................................................................................................1723
57.4 Functional description...................................................................................................................................................1745
Chapter 58
FlexIO
58.1 Chip-specific FlexIO information.................................................................................................................................1761
58.2 Introduction...................................................................................................................................................................1762
58.3 Memory Map and Registers..........................................................................................................................................1765
58.4 Functional description...................................................................................................................................................1789
58.5 Application Information................................................................................................................................................1799
Chapter 59
Integrated Interchip Sound (I2S) / Synchronous Audio Interface (SAI)
59.1 Chip-specific I2S/SAI information...............................................................................................................................1815
59.2 Introduction...................................................................................................................................................................1819
59.3 External signals.............................................................................................................................................................1821
59.4 Memory map and register definition.............................................................................................................................1822
59.5 Functional description...................................................................................................................................................1847
Chapter 60
Secured digital host controller (SDHC)
60.1 Chip-specific SDHC information................................................................................................................................. 1859
60.2 Introduction...................................................................................................................................................................1860
60.3 Overview.......................................................................................................................................................................1860
60.4 SDHC signal descriptions.............................................................................................................................................1863
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