Section number Title Page
9.4 System TAP connection................................................................................................................................................169
9.4.1 IR Codes.......................................................................................................................................................169
9.5 JTAG status and control registers.................................................................................................................................170
9.5.1 MDM-AP Control Register..........................................................................................................................171
9.5.2 MDM-AP Status Register............................................................................................................................173
9.6 Debug Resets................................................................................................................................................................174
9.7 AHB-AP........................................................................................................................................................................175
9.8 ITM...............................................................................................................................................................................175
9.9 Core Trace Connectivity...............................................................................................................................................176
9.10 Embedded Trace Macrocell v3.5 (ETM)......................................................................................................................176
9.11 TPIU..............................................................................................................................................................................177
9.12 DWT.............................................................................................................................................................................177
9.13 Debug in Low Power Modes........................................................................................................................................177
9.13.1 Debug Module State in Low Power Modes.................................................................................................178
9.14 Debug & Security.........................................................................................................................................................179
Chapter 10
Signal Multiplexing and Signal Descriptions
10.1 Introduction...................................................................................................................................................................181
10.2 Signal Multiplexing Integration....................................................................................................................................181
10.2.1 Port control and interrupt module features..................................................................................................182
10.2.2 PCRn reset values for port A.......................................................................................................................182
10.2.3 Clock gating.................................................................................................................................................182
10.2.4 Signal multiplexing constraints....................................................................................................................182
10.3 Pinout............................................................................................................................................................................183
10.3.1 K11 Signal Multiplexing and Pin Assignments...........................................................................................183
10.3.2 K11 Pinouts..................................................................................................................................................186
10.4 Module Signal Description Tables................................................................................................................................187
10.4.1 Core Modules...............................................................................................................................................188
10.4.2 System Modules...........................................................................................................................................188
K11 Sub-Family Reference Manual, Rev. 6, April 2014
Freescale Semiconductor, Inc. 9