NXP KM3x Reference guide

KM Family Reference Manual

Supports: MKM14Z64CHH5, MKM14Z128CHH5, MKM33Z64CLH5,

MKM33Z128CLH5, MKM33Z64CLL5, MKM33Z128CLL5,

MKM34Z128CLL5

Document Number: MKMxxZxxCxx5RM

Rev. 5, Oct 2013

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Contents

Section number Title Page

Chapter 1

About This Document

1.1 Overview.......................................................................................................................................................................39

1.1.1 Purpose.........................................................................................................................................................39

1.1.2 Audience......................................................................................................................................................39

1.2 Conventions..................................................................................................................................................................39

1.2.1 Numbering systems......................................................................................................................................39

1.2.2 Typographic notation...................................................................................................................................40

1.2.3 Special terms................................................................................................................................................40

Chapter 2

Introduction

2.1 KM family introduction................................................................................................................................................41

2.2 Detailed block diagram.................................................................................................................................................41

2.3 KM feature set...............................................................................................................................................................42

2.4 Device configuration.....................................................................................................................................................45

2.5 Modules on the device..................................................................................................................................................47

2.5.1 Platform modules.........................................................................................................................................47

2.5.2 System modules...........................................................................................................................................48

2.5.3 Clock............................................................................................................................................................50

2.5.4 Security modules..........................................................................................................................................50

2.5.5 Analog modules...........................................................................................................................................51

2.5.6 Timer modules.............................................................................................................................................52

2.5.7 Communication interfaces...........................................................................................................................53

2.5.8 Human-machine interfaces..........................................................................................................................55

Chapter 3

Chip Configuration

3.1 Introduction...................................................................................................................................................................57

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3.2 Core modules................................................................................................................................................................57

3.2.1 ARM Cortex-M0+ Core Configuration.......................................................................................................57

3.2.2 ARM Cortex M0+ core ...............................................................................................................................58

3.2.3 Buses, interconnects, and interfaces............................................................................................................59

3.2.4 Debug facilities............................................................................................................................................59

3.2.5 Interrupt priority levels................................................................................................................................59

3.2.6 Performance targets......................................................................................................................................60

3.2.7 Nested Vectored Interrupt Controller (NVIC) configuration.......................................................................60

3.2.8 Asynchronous Wake-up Interrupt Controller (AWIC) Configuration.........................................................62

3.3 System modules............................................................................................................................................................64

3.3.1 SIM Configuration.......................................................................................................................................64

3.3.2 PMC Configuration......................................................................................................................................64

3.3.3 Low-Leakage Wake-up Unit (LLWU) Configuration.................................................................................65

3.3.4 Crossbar-Light Switch Configuration..........................................................................................................67

3.3.5 DMA request multiplexer (DMA MUX) configuration..............................................................................69

3.3.6 External Watchdog Monitor (EWM) configuration.....................................................................................71

3.3.7 Watchdog Configuration..............................................................................................................................72

3.3.8 Inter-Peripheral Crossbar Switch (XBAR) Configuration...........................................................................73

3.4 Memories and Memory Interfaces................................................................................................................................77

3.4.1 RAM sizes....................................................................................................................................................77

3.4.2 Flash Memory Sizes.....................................................................................................................................77

3.5 Clock Modules..............................................................................................................................................................77

3.5.1 RTC OSC configuration...............................................................................................................................77

3.6 Security.........................................................................................................................................................................78

3.6.1 CRC Configuration......................................................................................................................................78

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3.6.2 RNG Configuration......................................................................................................................................79

3.7 Analog...........................................................................................................................................................................80

3.7.1 16-bit SAR ADC..........................................................................................................................................80

3.7.2 Analog Front End (AFE) configuration.......................................................................................................84

3.7.3 CMP Configuration......................................................................................................................................86

3.7.4 VREF Configuration....................................................................................................................................88

3.8 Timers...........................................................................................................................................................................92

3.8.1 Independent Real Time Clock (iRTC) configuration..................................................................................92

3.8.2 TMR Configuration......................................................................................................................................94

3.8.3 Low-power timer (LPTMR)configuration...................................................................................................95

3.8.4 PIT Configuration........................................................................................................................................97

3.9 Communication interface..............................................................................................................................................98

3.9.1 Serial Peripheral Interface (SPI) Configuration...........................................................................................98

3.9.2 UART configuration....................................................................................................................................99

3.9.3 I2C Configuration........................................................................................................................................101

3.10 Human machine interface.............................................................................................................................................103

3.10.1 eGPIO controller..........................................................................................................................................103

3.10.2 Segment LCD controller..............................................................................................................................106

Chapter 4

System Memory Map

4.1 Introduction...................................................................................................................................................................109

4.2 System Memory Map....................................................................................................................................................109

4.3 Flash Memory Map.......................................................................................................................................................110

4.4 SRAM memory map.....................................................................................................................................................110

4.5 Peripheral bridge (AIPS-Lite) memory map.................................................................................................................111

4.6 AIPS peripheral slot assignment...................................................................................................................................112

4.7 Private peripherals........................................................................................................................................................116

4.8 Private Peripheral Bus (PPB) memory map..................................................................................................................116

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Chapter 5

Clock Distribution

5.1 Introduction...................................................................................................................................................................119

5.2 High-Level clocking diagram.......................................................................................................................................119

5.3 Clock definitions...........................................................................................................................................................121

5.3.1 Device clock summary.................................................................................................................................122

5.4 Internal clocking requirements.....................................................................................................................................123

5.4.1 Clock divider values after reset....................................................................................................................123

5.4.2 VLPR mode clocking...................................................................................................................................124

5.4.3 Enable PLL in VLPR or VLPR and PSTOP1 .............................................................................................124

5.5 Clock Gating.................................................................................................................................................................125

5.6 Module clocks...............................................................................................................................................................125

Chapter 6

Reset and Boot

6.1 Reset..............................................................................................................................................................................129

6.1.1 System resets and sources............................................................................................................................129

6.2 Boot...............................................................................................................................................................................133

6.2.1 Boot sources.................................................................................................................................................133

6.2.2 Boot options.................................................................................................................................................133

6.2.3 FOPT boot options.......................................................................................................................................133

6.2.4 Boot sequence..............................................................................................................................................134

Chapter 7

Power Management

7.1 Introduction...................................................................................................................................................................137

7.2 Power Modes................................................................................................................................................................137

7.3 Entering and exiting power modes...............................................................................................................................139

7.4 Power mode transitions.................................................................................................................................................140

7.5 Power modes shutdown sequencing.............................................................................................................................141

7.6 Module Operation in Low Power Modes......................................................................................................................141

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7.7 Clocking modes............................................................................................................................................................144

7.7.1 Partial Stop...................................................................................................................................................144

7.7.2 DMA Wakeup..............................................................................................................................................145

7.7.3 Compute Operation......................................................................................................................................146

7.7.4 Peripheral Doze............................................................................................................................................147

7.7.5 Clock gating.................................................................................................................................................148

Chapter 8

Security

8.1 Introduction...................................................................................................................................................................149

8.2 External Watchdog Monitor.........................................................................................................................................149

8.2.1 EWM Counter..............................................................................................................................................149

8.2.2 EWM_out Signal..........................................................................................................................................150

8.2.3 EWM_In Signal...........................................................................................................................................150

8.3 Robust Watchdog for Improved System Reliability.....................................................................................................151

8.3.1 32-bit programmable timeout Period...........................................................................................................151

8.3.2 Independent Clock Source...........................................................................................................................152

8.3.3 Write Protection...........................................................................................................................................152

8.3.4 Robust Refresh Mechanism.........................................................................................................................153

8.3.5 Windowed Refresh.......................................................................................................................................154

8.3.6 Fast Response to Code Runaway.................................................................................................................154

8.4 Watchdog configuration................................................................................................................................................156

8.5 iRTC Write Protect State Machine...............................................................................................................................156

8.6 iRTC Tamper Detection Mechanism............................................................................................................................157

8.6.1 Internal Tamper Condition 1: Battery removed when MCU is powered OFF............................................157

8.6.2 Internal Tamper Condition 2: Battery removed when MCU is powered ON..............................................157

8.6.3 External Tamper Condition: Off Chip Tamper Indication...........................................................................158

8.6.4 Tamper Detection Flow...............................................................................................................................158

8.6.5 Active Tamper Detection.............................................................................................................................159

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Chapter 9

Debug

9.1 Introduction...................................................................................................................................................................161

9.2 Debug Port Pin Descriptions.........................................................................................................................................161

9.3 SWD status and control registers..................................................................................................................................162

9.3.1 MDM-AP Control Register..........................................................................................................................163

9.3.2 MDM-AP Status Register............................................................................................................................164

9.4 Debug Resets................................................................................................................................................................166

9.5 Micro Trace Buffer (MTB)...........................................................................................................................................166

9.6 Debug in Low Power Modes........................................................................................................................................167

9.7 Debug & Security.........................................................................................................................................................167

Chapter 10

Pinouts and Packaging

10.1 Package Types..............................................................................................................................................................169

10.2 Photon Signal Multiplexing and Pin Assignments.......................................................................................................169

10.3 KM Family Pinouts.......................................................................................................................................................172

10.3.1 100-pin LQFP..............................................................................................................................................172

10.3.2 64-pin LQFP................................................................................................................................................173

10.3.3 44-pin LGA..................................................................................................................................................174

Chapter 11

Port Control and Interrupts (PORT)

11.1 Introduction...................................................................................................................................................................177

11.2 Overview.......................................................................................................................................................................177

11.2.1 Features........................................................................................................................................................177

11.2.2 Modes of operation......................................................................................................................................178

11.3 External signal description............................................................................................................................................179

11.4 Detailed signal description............................................................................................................................................179

11.5 Memory map and register definition.............................................................................................................................179

11.5.1 Pin Control Register n (PORTx_PCRn).......................................................................................................184

11.5.2 Global Pin Control Low Register (PORTx_GPCLR)..................................................................................186

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11.5.3 Global Pin Control High Register (PORTx_GPCHR).................................................................................187

11.5.4 Interrupt Status Flag Register (PORTx_ISFR)............................................................................................187

11.5.5 Digital Filter Enable Register (PORTx_DFER)...........................................................................................188

11.5.6 Digital Filter Clock Register (PORTx_DFCR)............................................................................................189

11.5.7 Digital Filter Width Register (PORTx_DFWR)..........................................................................................189

11.6 Functional description...................................................................................................................................................190

11.6.1 Pin control....................................................................................................................................................190

11.6.2 Global pin control........................................................................................................................................191

11.6.3 External interrupts........................................................................................................................................191

11.6.4 Digital filter..................................................................................................................................................192

Chapter 12

System Integration Module (SIM)

12.1 Introduction...................................................................................................................................................................193

12.2 Features.........................................................................................................................................................................193

12.3 Memory map and register definition.............................................................................................................................194

12.3.1 System Options Register 1 (SIM_SOPT1)..................................................................................................195

12.3.2 SOPT1 Configuration Register (SIM_SOPT1_CFG)..................................................................................196

12.3.3 System Control Register (SIM_CTRL_REG).............................................................................................197

12.3.4 System Device Identification Register (SIM_SDID)...................................................................................198

12.3.5 System Clock Gating Control Register 4 (SIM_SCGC4)............................................................................200

12.3.6 System Clock Gating Control Register 5 (SIM_SCGC5)............................................................................203

12.3.7 System Clock Gating Control Register 6 (SIM_SCGC6)............................................................................207

12.3.8 System Clock Gating Control Register 7 (SIM_SCGC7)............................................................................210

12.3.9 System Clock Divider Register 1 (SIM_CLKDIV1)...................................................................................211

12.3.10 Flash Configuration Register 1 (SIM_FCFG1)...........................................................................................213

12.3.11 Flash Configuration Register 2 (SIM_FCFG2)...........................................................................................215

12.3.12 Unique Identification Register 0 (SIM_UID0)............................................................................................215

12.3.13 Unique Identification Register 1 (SIM_UID1)............................................................................................216

12.3.14 Unique Identification Register 2 (SIM_UID2)............................................................................................216

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12.3.15 Unique Identification Register 3 (SIM_UID3)............................................................................................217

12.3.16 Miscellaneous Control Register (SIM_MISC_CTL)...................................................................................217

12.4 Functional description...................................................................................................................................................221

Chapter 13

Miscellaneous Control Module (MCM)

13.1 Introduction...................................................................................................................................................................223

13.1.1 Features........................................................................................................................................................223

13.2 Memory map/register descriptions...............................................................................................................................223

13.2.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)................................................................224

13.2.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC)............................................................225

13.2.3 Platform Control Register (MCM_PLACR)................................................................................................225

13.2.4 Process ID register (MCM_PID).................................................................................................................228

13.2.5 Compute Operation Control Register (MCM_CPO)...................................................................................229

13.2.6 Master Attribute Configuration Register (MCM_MATCRn)......................................................................230

Chapter 14

Reset Control Module (RCM)

14.1 Introduction...................................................................................................................................................................233

14.2 Reset memory map and register descriptions...............................................................................................................233

14.2.1 System Reset Status Register 0 (RCM_SRS0)............................................................................................234

14.2.2 System Reset Status Register 1 (RCM_SRS1)............................................................................................235

14.2.3 Reset Pin Filter Control register (RCM_RPFC)..........................................................................................236

14.2.4 Reset Pin Filter Width register (RCM_RPFW)...........................................................................................237

Chapter 15

System Mode Controller (SMC)

15.1 Introduction...................................................................................................................................................................239

15.2 Modes of operation.......................................................................................................................................................239

15.3 Memory map and register descriptions.........................................................................................................................241

15.3.1 Power Mode Protection register (SMC_PMPROT).....................................................................................242

15.3.2 Power Mode Control register (SMC_PMCTRL).........................................................................................243

15.3.3 Stop Control Register (SMC_STOPCTRL).................................................................................................244

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15.3.4 Power Mode Status register (SMC_PMSTAT)...........................................................................................245

15.4 Functional description...................................................................................................................................................246

15.4.1 Power mode transitions................................................................................................................................246

15.4.2 Power mode entry/exit sequencing..............................................................................................................249

15.4.3 Run modes....................................................................................................................................................252

15.4.4 Wait modes..................................................................................................................................................253

15.4.5 Stop modes...................................................................................................................................................254

15.4.6 Debug in low power modes.........................................................................................................................256

Chapter 16

Inter-Peripheral Crossbar Switch (XBAR)

16.1 Introduction...................................................................................................................................................................259

16.1.1 Overview......................................................................................................................................................259

16.1.2 Features........................................................................................................................................................259

16.1.3 Modes of Operation.....................................................................................................................................260

16.1.4 Block Diagram.............................................................................................................................................260

16.2 Signal Descriptions.......................................................................................................................................................261

16.2.1 XBAR_OUT[0:NUM_OUT-1] - MUX Outputs.........................................................................................261

16.2.2 XBAR_IN[0:NUM_IN-1] - MUX Inputs....................................................................................................261

16.2.3 DMA_REQ[n] - DMA Request Output(s)...................................................................................................261

16.2.4 DMA_ACK[n] - DMA Acknowledge Input(s)............................................................................................261

16.2.5 INT_REQ[n] - Interrupt Request Output(s).................................................................................................262

16.3 Memory Map and Register Descriptions......................................................................................................................262

16.3.1 Crossbar Select Register 0 (XBAR_SEL0).................................................................................................263

16.3.2 Crossbar Select Register 1 (XBAR_SEL1).................................................................................................263

16.3.3 Crossbar Select Register 2 (XBAR_SEL2).................................................................................................264

16.3.4 Crossbar Select Register 3 (XBAR_SEL3).................................................................................................264

16.3.5 Crossbar Select Register 4 (XBAR_SEL4).................................................................................................265

16.3.6 Crossbar Select Register 5 (XBAR_SEL5).................................................................................................265

16.3.7 Crossbar Select Register 6 (XBAR_SEL6).................................................................................................266

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16.3.8 Crossbar Select Register 7 (XBAR_SEL7).................................................................................................266

16.3.9 Crossbar Select Register 8 (XBAR_SEL8).................................................................................................267

16.3.10 Crossbar Select Register 9 (XBAR_SEL9).................................................................................................267

16.3.11 Crossbar Select Register 10 (XBAR_SEL10).............................................................................................268

16.3.12 Crossbar Select Register 11 (XBAR_SEL11).............................................................................................268

16.3.13 Crossbar Select Register 12 (XBAR_SEL12).............................................................................................269

16.3.14 Crossbar Select Register 13 (XBAR_SEL13).............................................................................................269

16.3.15 Crossbar Select Register 14 (XBAR_SEL14).............................................................................................270

16.3.16 Crossbar Select Register 15 (XBAR_SEL15).............................................................................................270

16.3.17 Crossbar Select Register 16 (XBAR_SEL16).............................................................................................271

16.3.18 Crossbar Control Register 0 (XBAR_CTRL0)............................................................................................271

16.4 Functional Description..................................................................................................................................................272

16.4.1 General.........................................................................................................................................................272

16.4.2 Functional Mode..........................................................................................................................................273

16.5 Resets............................................................................................................................................................................273

16.6 Clocks...........................................................................................................................................................................273

16.7 Interrupts and DMA Requests......................................................................................................................................273

Chapter 17

Low-Leakage Wakeup Unit (LLWU)

17.1 Introduction...................................................................................................................................................................275

17.1.1 Features........................................................................................................................................................275

17.1.2 Modes of operation......................................................................................................................................276

17.1.3 Block diagram..............................................................................................................................................276

17.2 LLWU signal descriptions............................................................................................................................................277

17.3 Memory map/register definition...................................................................................................................................278

17.3.1 LLWU Pin Enable 1 register (LLWU_PE1)................................................................................................279

17.3.2 LLWU Pin Enable 2 register (LLWU_PE2)................................................................................................280

17.3.3 LLWU Pin Enable 3 register (LLWU_PE3)................................................................................................281

17.3.4 LLWU Pin Enable 4 register (LLWU_PE4)................................................................................................282

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17.3.5 LLWU Module Enable register (LLWU_ME)............................................................................................283

17.3.6 LLWU Flag 1 register (LLWU_F1).............................................................................................................285

17.3.7 LLWU Flag 2 register (LLWU_F2).............................................................................................................286

17.3.8 LLWU Flag 3 register (LLWU_F3).............................................................................................................288

17.3.9 LLWU Pin Filter 1 register (LLWU_FILT1)..............................................................................................290

17.3.10 LLWU Pin Filter 2 register (LLWU_FILT2)..............................................................................................291

17.4 Functional description...................................................................................................................................................292

17.4.1 VLLS modes................................................................................................................................................292

17.4.2 Initialization.................................................................................................................................................292

Chapter 18

DMA Controller Module

18.1 Introduction...................................................................................................................................................................295

18.1.1 Overview......................................................................................................................................................295

18.1.2 Features........................................................................................................................................................296

18.2 DMA Transfer Overview..............................................................................................................................................297

18.3 Memory Map/Register Definition.................................................................................................................................298

18.3.1 Source Address Register (DMA_SARn).....................................................................................................300

18.3.2 Destination Address Register (DMA_DARn).............................................................................................301

18.3.3 DMA Status Register / Byte Count Register (DMA_DSR_BCRn).............................................................301

18.3.4 DMA Control Register (DMA_DCRn)........................................................................................................304

18.4 Functional Description..................................................................................................................................................308

18.4.1 Transfer requests (Cycle-Steal and Continuous modes)..............................................................................309

18.4.2 Channel initialization and startup................................................................................................................309

18.4.3 Dual-Address Data Transfer Mode..............................................................................................................312

18.4.4 Advanced Data Transfer Controls: Auto-Alignment...................................................................................312

18.4.5 Termination..................................................................................................................................................313

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Chapter 19

Direct Memory Access Multiplexer (DMAMUX)

19.1 Introduction...................................................................................................................................................................315

19.1.1 Overview......................................................................................................................................................315

19.1.2 Features........................................................................................................................................................316

19.1.3 Modes of operation......................................................................................................................................316

19.2 External signal description............................................................................................................................................317

19.3 Memory map/register definition...................................................................................................................................317

19.3.1 Channel Configuration register (DMAMUXx_CHCFG)............................................................................317

19.4 Functional description...................................................................................................................................................318

19.4.1 DMA channels with periodic triggering capability......................................................................................319

19.4.2 DMA channels with no triggering capability...............................................................................................321

19.4.3 Always-enabled DMA sources....................................................................................................................321

19.5 Initialization/application information...........................................................................................................................321

19.5.1 Reset.............................................................................................................................................................322

19.5.2 Enabling and configuring sources................................................................................................................322

Chapter 20

Peripheral Bridge (AIPS-Lite)

20.1 Introduction...................................................................................................................................................................327

20.1.1 Features........................................................................................................................................................327

20.1.2 General operation.........................................................................................................................................327

20.2 Memory map/register definition...................................................................................................................................328

20.2.1 Peripheral Access Control Register (AIPS_PACRn)...................................................................................329

20.2.2 Peripheral Access Control Register (AIPS_PACRn)...................................................................................332

20.3 Functional description...................................................................................................................................................335

20.3.1 Access support.............................................................................................................................................335

Chapter 21

Memory Protection Unit (MPU)

21.1 Introduction...................................................................................................................................................................337

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21.2 Overview.......................................................................................................................................................................337

21.2.1 Block diagram..............................................................................................................................................337

21.2.2 Features........................................................................................................................................................338

21.3 Memory map/register definition...................................................................................................................................339

21.3.1 Control/Error Status Register (MPU_CESR)..............................................................................................341

21.3.2 Error Address Register, slave port n (MPU_EARn)....................................................................................343

21.3.3 Error Detail Register, slave port n (MPU_EDRn).......................................................................................344

21.3.4 Region Descriptor n, Word 0 (MPU_RGDn_WORD0)..............................................................................345

21.3.5 Region Descriptor n, Word 1 (MPU_RGDn_WORD1)..............................................................................345

21.3.6 Region Descriptor n, Word 2 (MPU_RGDn_WORD2)..............................................................................346

21.3.7 Region Descriptor n, Word 3 (MPU_RGDn_WORD3)..............................................................................349

21.3.8 Region Descriptor Alternate Access Control n (MPU_RGDAACn)...........................................................350

21.4 Functional description...................................................................................................................................................352

21.4.1 Access evaluation macro..............................................................................................................................352

21.4.2 Putting it all together and error terminations...............................................................................................354

21.4.3 Power management......................................................................................................................................354

21.5 Initialization information..............................................................................................................................................355

21.6 Application information................................................................................................................................................355

Chapter 22

Power Management Controller (PMC)

22.1 Introduction...................................................................................................................................................................359

22.2 Features.........................................................................................................................................................................359

22.3 Low-voltage detect (LVD) system................................................................................................................................359

22.3.1 LVD reset operation.....................................................................................................................................360

22.3.2 LVD interrupt operation...............................................................................................................................360

22.3.3 Low-voltage warning (LVW) interrupt operation.......................................................................................360

22.4 I/O retention..................................................................................................................................................................361

22.5 Memory map and register descriptions.........................................................................................................................361

22.5.1 Low Voltage Detect Status And Control 1 register (PMC_LVDSC1)........................................................362

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22.5.2 Low Voltage Detect Status And Control 2 register (PMC_LVDSC2)........................................................363

22.5.3 Regulator Status And Control register (PMC_REGSC)..............................................................................364

Chapter 23

Watchdog Timer (WDOG)

23.1 Introduction...................................................................................................................................................................367

23.2 Features.........................................................................................................................................................................367

23.3 Functional overview......................................................................................................................................................369

23.3.1 Unlocking and updating the watchdog.........................................................................................................370

23.3.2 Watchdog configuration time (WCT)..........................................................................................................371

23.3.3 Refreshing the watchdog..............................................................................................................................372

23.3.4 Windowed mode of operation......................................................................................................................372

23.3.5 Watchdog disabled mode of operation.........................................................................................................372

23.3.6 Low-power modes of operation...................................................................................................................373

23.3.7 Low-power and Debug modes of operation.................................................................................................373

23.4 Testing the watchdog....................................................................................................................................................374

23.4.1 Quick test.....................................................................................................................................................374

23.4.2 Byte test........................................................................................................................................................375

23.5 Backup reset generator..................................................................................................................................................376

23.6 Generated resets and interrupts.....................................................................................................................................376

23.7 Memory map and register definition.............................................................................................................................377

23.7.1 Watchdog Status and Control Register High (WDOG_STCTRLH)...........................................................378

23.7.2 Watchdog Status and Control Register Low (WDOG_STCTRLL)............................................................379

23.7.3 Watchdog Time-out Value Register High (WDOG_TOVALH).................................................................380

23.7.4 Watchdog Time-out Value Register Low (WDOG_TOVALL)..................................................................380

23.7.5 Watchdog Window Register High (WDOG_WINH)..................................................................................381

23.7.6 Watchdog Window Register Low (WDOG_WINL)...................................................................................381

23.7.7 Watchdog Refresh register (WDOG_REFRESH).......................................................................................382

23.7.8 Watchdog Unlock register (WDOG_UNLOCK).........................................................................................382

23.7.9 Watchdog Timer Output Register High (WDOG_TMROUTH).................................................................382

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23.7.10 Watchdog Timer Output Register Low (WDOG_TMROUTL)..................................................................383

23.7.11 Watchdog Reset Count register (WDOG_RSTCNT)..................................................................................383

23.7.12 Watchdog Prescaler register (WDOG_PRESC)..........................................................................................384

23.8 Watchdog operation with 8-bit access..........................................................................................................................384

23.8.1 General guideline.........................................................................................................................................384

23.8.2 Refresh and unlock operations with 8-bit access.........................................................................................384

23.9 Restrictions on watchdog operation..............................................................................................................................385

Chapter 24

External Watchdog Monitor (EWM)

24.1 Introduction...................................................................................................................................................................389

24.1.1 Features........................................................................................................................................................389

24.1.2 Modes of Operation.....................................................................................................................................390

24.1.3 Block Diagram.............................................................................................................................................391

24.2 EWM Signal Descriptions............................................................................................................................................392

24.3 Memory Map/Register Definition.................................................................................................................................392

24.3.1 Control Register (EWM_CTRL).................................................................................................................392

24.3.2 Service Register (EWM_SERV)..................................................................................................................393

24.3.3 Compare Low Register (EWM_CMPL)......................................................................................................393

24.3.4 Compare High Register (EWM_CMPH).....................................................................................................394

24.4 Functional Description..................................................................................................................................................395

24.4.1 The EWM_out Signal..................................................................................................................................395

24.4.2 The EWM_in Signal....................................................................................................................................396

24.4.3 EWM Counter..............................................................................................................................................396

24.4.4 EWM Compare Registers............................................................................................................................396

24.4.5 EWM Refresh Mechanism...........................................................................................................................397

24.4.6 EWM Interrupt.............................................................................................................................................397

Chapter 25

Analog Front End (AFE)

25.1 Introduction...................................................................................................................................................................399

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25.2 Features.........................................................................................................................................................................399

25.3 Block Diagram..............................................................................................................................................................400

25.4 AFE Clocking...............................................................................................................................................................402

25.5 OSR Select....................................................................................................................................................................403

25.6 Analog Gain Select.......................................................................................................................................................403

25.7 Memory Map and Register Definition..........................................................................................................................403

25.7.1 Channel0 Configuration Register (AFE_CH0_CFR)..................................................................................404

25.7.2 Channel1 Configuration Register (AFE_CH1_CFR)..................................................................................406

25.7.3 Channel2 Configuration Register (AFE_CH2_CFR)..................................................................................409

25.7.4 Channel3 Configuration Register (AFE_CH3_CFR)..................................................................................411

25.7.5 Control Register (AFE_CR).........................................................................................................................413

25.7.6 Clock Configuration Register (AFE_CKR).................................................................................................415

25.7.7 DMA and Interrupt Register (AFE_DI).......................................................................................................416

25.7.8 Channel0 Delay Register (AFE_CH0_DR).................................................................................................417

25.7.9 Channel1 Delay Register (AFE_CH1_DR).................................................................................................417

25.7.10 Channel2 Delay Register (AFE_CH2_DR).................................................................................................418

25.7.11 Channel3 Delay Register (AFE_CH3_DR).................................................................................................418

25.7.12 Channel0 Result Register (AFE_CH0_RR).................................................................................................419

25.7.13 Channel1 Result Register (AFE_CH1_RR).................................................................................................419

25.7.14 Channel2 Result Register (AFE_CH2_RR).................................................................................................420

25.7.15 Channel3 Result Register (AFE_CH3_RR).................................................................................................420

25.7.16 Status Register (AFE_SR)...........................................................................................................................422

25.8 Power Modes................................................................................................................................................................424

25.8.1 Normal Run Mode.......................................................................................................................................424

25.8.2 Wait Mode....................................................................................................................................................424

25.8.3 Low Power Run Mode.................................................................................................................................424

25.8.4 STOP Mode..................................................................................................................................................424

25.9 Functional Description..................................................................................................................................................425

25.9.1 Start Up........................................................................................................................................................425

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25.9.2 Conversion Control......................................................................................................................................425

25.9.3 Modes of Conversion...................................................................................................................................429

25.9.4 Independent Control for Conversion............................................................................................................433

25.10 Decimation Filter..........................................................................................................................................................434

25.10.1 Sampling Phase Control...............................................................................................................................434

25.10.2 Frequency response......................................................................................................................................434

25.11 Modulator Bypass Mode...............................................................................................................................................435

Chapter 26

Analog-to-Digital Converter (ADC)

26.1 Introduction...................................................................................................................................................................437

26.1.1 Features........................................................................................................................................................437

26.1.2 Block diagram..............................................................................................................................................438

26.2 ADC signal descriptions...............................................................................................................................................439

26.2.1 Analog Power (VDDA)...............................................................................................................................440

26.2.2 Analog Ground (VSSA)...............................................................................................................................440

26.2.3 Analog Channel Inputs (ADx).....................................................................................................................440

26.3 Memory map and register definitions...........................................................................................................................440

26.3.1 ADC Status and Control Registers 1 (ADC_SC1n).....................................................................................441

26.3.2 ADC Configuration Register 1 (ADC_CFG1).............................................................................................445

26.3.3 ADC Configuration Register 2 (ADC_CFG2).............................................................................................446

26.3.4 ADC Data Result Register (ADC_Rn)........................................................................................................447

26.3.5 Compare Value Registers (ADC_CVn).......................................................................................................448

26.3.6 Status and Control Register 2 (ADC_SC2)..................................................................................................449

26.3.7 Status and Control Register 3 (ADC_SC3)..................................................................................................451

26.3.8 ADC Offset Correction Register (ADC_OFS)............................................................................................453

26.3.9 ADC Plus-Side Gain Register (ADC_PG)...................................................................................................453

26.3.10 ADC Plus-Side General Calibration Value Register (ADC_CLPD)...........................................................454

26.3.11 ADC Plus-Side General Calibration Value Register (ADC_CLPS)............................................................454

26.3.12 ADC Plus-Side General Calibration Value Register (ADC_CLP4)............................................................455

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26.3.13 ADC Plus-Side General Calibration Value Register (ADC_CLP3)............................................................455

26.3.14 ADC Plus-Side General Calibration Value Register (ADC_CLP2)............................................................456

26.3.15 ADC Plus-Side General Calibration Value Register (ADC_CLP1)............................................................456

26.3.16 ADC Plus-Side General Calibration Value Register (ADC_CLP0)............................................................457

26.4 Functional description...................................................................................................................................................457

26.4.1 Clock select and divide control....................................................................................................................458

26.4.2 Voltage reference selection..........................................................................................................................458

26.4.3 Hardware trigger and channel selects..........................................................................................................459

26.4.4 Conversion control.......................................................................................................................................460

26.4.5 Automatic compare function........................................................................................................................468

26.4.6 Calibration function.....................................................................................................................................469

26.4.7 User-defined offset function........................................................................................................................470

26.4.8 Temperature sensor......................................................................................................................................471

26.4.9 MCU wait mode operation...........................................................................................................................472

26.4.10 MCU Normal Stop mode operation.............................................................................................................473

26.4.11 MCU Low-Power Stop mode operation......................................................................................................474

26.5 Initialization information..............................................................................................................................................474

26.5.1 ADC module initialization example............................................................................................................474

26.6 Application information................................................................................................................................................476

26.6.1 External pins and routing.............................................................................................................................476

26.6.2 Sources of error............................................................................................................................................478

Chapter 27

Comparator (CMP)

27.1 Introduction...................................................................................................................................................................483

27.1.1 CMP features................................................................................................................................................483

27.1.2 6-bit DAC key features................................................................................................................................484

27.1.3 ANMUX key features..................................................................................................................................484

27.1.4 CMP, DAC and ANMUX diagram..............................................................................................................485

27.1.5 CMP block diagram.....................................................................................................................................486

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