NXP K12_50 Reference guide

Type
Reference guide
K12 Sub-Family Reference Manual
Supports: MK12DX128VMC5, MK12DX256VMC5, MK12DN512VMC5
Document Number: K12P121M50SF4RM
Rev. 4, February 2013
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Contents
Section number Title Page
Chapter 1
About This Document
1.1 Overview.......................................................................................................................................................................45
1.1.1 Purpose.........................................................................................................................................................45
1.1.2 Audience......................................................................................................................................................45
1.2 Conventions..................................................................................................................................................................45
1.2.1 Numbering systems......................................................................................................................................45
1.2.2 Typographic notation...................................................................................................................................46
1.2.3 Special terms................................................................................................................................................46
Chapter 2
Introduction
2.1 Overview.......................................................................................................................................................................47
2.2 Module Functional Categories......................................................................................................................................47
2.2.1 ARM® Cortex™-M4 Core Modules...........................................................................................................48
2.2.2 System Modules...........................................................................................................................................49
2.2.3 Memories and Memory Interfaces...............................................................................................................50
2.2.4 Clocks...........................................................................................................................................................50
2.2.5 Security and Integrity modules....................................................................................................................51
2.2.6 Analog modules...........................................................................................................................................51
2.2.7 Timer modules.............................................................................................................................................51
2.2.8 Communication interfaces...........................................................................................................................53
2.2.9 Human-machine interfaces..........................................................................................................................53
2.3 Orderable part numbers.................................................................................................................................................53
Chapter 3
Chip Configuration
3.1 Introduction...................................................................................................................................................................55
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3.2 Core modules................................................................................................................................................................55
3.2.1 ARM Cortex-M4 Core Configuration..........................................................................................................55
3.2.2 Nested Vectored Interrupt Controller (NVIC) Configuration......................................................................57
3.2.3 Asynchronous Wake-up Interrupt Controller (AWIC) Configuration.........................................................62
3.2.4 JTAG Controller Configuration...................................................................................................................64
3.3 System modules............................................................................................................................................................64
3.3.1 SIM Configuration.......................................................................................................................................64
3.3.2 System Mode Controller (SMC) Configuration...........................................................................................65
3.3.3 PMC Configuration......................................................................................................................................66
3.3.4 Low-Leakage Wake-up Unit (LLWU) Configuration.................................................................................66
3.3.5 MCM Configuration....................................................................................................................................68
3.3.6 Crossbar-Light Switch Configuration..........................................................................................................69
3.3.7 Peripheral Bridge Configuration..................................................................................................................70
3.3.8 DMA request multiplexer configuration......................................................................................................71
3.3.9 DMA Controller Configuration...................................................................................................................74
3.3.10 External Watchdog Monitor (EWM) Configuration....................................................................................75
3.3.11 Watchdog Configuration..............................................................................................................................77
3.4 Clock modules..............................................................................................................................................................78
3.4.1 MCG Configuration.....................................................................................................................................78
3.4.2 OSC Configuration......................................................................................................................................79
3.4.3 RTC OSC configuration...............................................................................................................................80
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3.5 Memories and memory interfaces.................................................................................................................................80
3.5.1 Flash Memory Configuration.......................................................................................................................80
3.5.2 Flash Memory Controller Configuration.....................................................................................................84
3.5.3 SRAM Configuration...................................................................................................................................85
3.5.4 System Register File Configuration.............................................................................................................87
3.5.5 VBAT Register File Configuration..............................................................................................................88
3.5.6 EzPort Configuration...................................................................................................................................89
3.6 Security.........................................................................................................................................................................90
3.6.1 CRC Configuration......................................................................................................................................90
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3.7 Analog...........................................................................................................................................................................91
3.7.1 16-bit SAR ADC Configuration..................................................................................................................91
3.7.2 CMP Configuration......................................................................................................................................95
3.7.3 12-bit DAC Configuration...........................................................................................................................96
3.7.4 VREF Configuration....................................................................................................................................97
3.8 Timers...........................................................................................................................................................................98
3.8.1 PDB Configuration......................................................................................................................................99
3.8.2 FlexTimer Configuration.............................................................................................................................101
3.8.3 PIT Configuration........................................................................................................................................105
3.8.4 Low-power timer configuration...................................................................................................................106
3.8.5 CMT Configuration......................................................................................................................................107
3.8.6 RTC configuration.......................................................................................................................................108
3.9 Communication interfaces............................................................................................................................................109
3.9.1 SPI configuration.........................................................................................................................................110
3.9.2 I2C Configuration........................................................................................................................................113
3.9.3 UART Configuration...................................................................................................................................113
3.9.4 I2S configuration..........................................................................................................................................116
3.10 Human-machine interfaces...........................................................................................................................................119
3.10.1 GPIO configuration......................................................................................................................................119
Chapter 4
Memory Map
4.1 Introduction...................................................................................................................................................................121
4.2 System memory map.....................................................................................................................................................121
4.2.1 Aliased bit-band regions..............................................................................................................................122
4.3 Flash Memory Map.......................................................................................................................................................123
4.3.1 Alternate Non-Volatile IRC User Trim Description....................................................................................124
4.4 SRAM memory map.....................................................................................................................................................124
4.5 Peripheral bridge (AIPS-Lite) memory map.................................................................................................................125
4.5.1 Read-after-write sequence and required serialization of memory operations..............................................125
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4.5.2 Peripheral Bridge 0 (AIPS-Lite 0) Memory Map........................................................................................125
4.6 Private Peripheral Bus (PPB) memory map..................................................................................................................129
Chapter 5
Clock Distribution
5.1 Introduction...................................................................................................................................................................131
5.2 Programming model......................................................................................................................................................131
5.3 High-Level device clocking diagram............................................................................................................................131
5.4 Clock definitions...........................................................................................................................................................132
5.4.1 Device clock summary.................................................................................................................................133
5.5 Internal clocking requirements.....................................................................................................................................134
5.5.1 Clock divider values after reset....................................................................................................................135
5.5.2 VLPR mode clocking...................................................................................................................................135
5.6 Clock Gating.................................................................................................................................................................136
5.7 Module clocks...............................................................................................................................................................136
5.7.1 PMC 1-kHz LPO clock................................................................................................................................137
5.7.2 WDOG clocking..........................................................................................................................................138
5.7.3 Debug trace clock.........................................................................................................................................138
5.7.4 PORT digital filter clocking.........................................................................................................................139
5.7.5 LPTMR clocking..........................................................................................................................................139
5.7.6 UART clocking............................................................................................................................................140
5.7.7 I2S/SAI clocking..........................................................................................................................................140
Chapter 6
Reset and Boot
6.1 Introduction...................................................................................................................................................................141
6.2 Reset..............................................................................................................................................................................142
6.2.1 Power-on reset (POR)..................................................................................................................................142
6.2.2 System reset sources....................................................................................................................................142
6.2.3 MCU Resets.................................................................................................................................................146
6.2.4 Reset Pin .....................................................................................................................................................148
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6.2.5 Debug resets.................................................................................................................................................148
6.3 Boot...............................................................................................................................................................................149
6.3.1 Boot sources.................................................................................................................................................149
6.3.2 Boot options.................................................................................................................................................149
6.3.3 FOPT boot options.......................................................................................................................................150
6.3.4 Boot sequence..............................................................................................................................................151
Chapter 7
Power Management
7.1 Introduction...................................................................................................................................................................153
7.2 Power modes.................................................................................................................................................................153
7.3 Entering and exiting power modes...............................................................................................................................155
7.4 Power mode transitions.................................................................................................................................................156
7.5 Power modes shutdown sequencing.............................................................................................................................157
7.6 Module Operation in Low Power Modes......................................................................................................................158
7.7 Clock Gating.................................................................................................................................................................161
Chapter 8
Security
8.1 Introduction...................................................................................................................................................................163
8.2 Flash Security...............................................................................................................................................................163
8.3 Security Interactions with other Modules.....................................................................................................................164
8.3.1 Security Interactions with EzPort................................................................................................................164
8.3.2 Security Interactions with Debug.................................................................................................................164
Chapter 9
Debug
9.1 Introduction...................................................................................................................................................................165
9.1.1 References....................................................................................................................................................167
9.2 The Debug Port.............................................................................................................................................................167
9.2.1 JTAG-to-SWD change sequence.................................................................................................................168
9.2.2 JTAG-to-cJTAG change sequence...............................................................................................................168
9.3 Debug Port Pin Descriptions.........................................................................................................................................169
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9.4 System TAP connection................................................................................................................................................169
9.4.1 IR Codes.......................................................................................................................................................169
9.5 JTAG status and control registers.................................................................................................................................170
9.5.1 MDM-AP Control Register..........................................................................................................................171
9.5.2 MDM-AP Status Register............................................................................................................................173
9.6 Debug Resets................................................................................................................................................................174
9.7 AHB-AP........................................................................................................................................................................175
9.8 ITM...............................................................................................................................................................................175
9.9 Core Trace Connectivity...............................................................................................................................................176
9.10 Embedded Trace Macrocell v3.5 (ETM)......................................................................................................................176
9.11 TPIU..............................................................................................................................................................................176
9.12 DWT.............................................................................................................................................................................177
9.13 Debug in Low Power Modes........................................................................................................................................177
9.13.1 Debug Module State in Low Power Modes.................................................................................................178
9.14 Debug & Security.........................................................................................................................................................179
Chapter 10
Signal Multiplexing and Signal Descriptions
10.1 Introduction...................................................................................................................................................................181
10.2 Signal Multiplexing Integration....................................................................................................................................181
10.2.1 Port control and interrupt module features..................................................................................................182
10.2.2 PCRn reset values for port A.......................................................................................................................182
10.2.3 Clock gating.................................................................................................................................................182
10.2.4 Signal multiplexing constraints....................................................................................................................182
10.3 Pinout............................................................................................................................................................................183
10.3.1 K12 Signal Multiplexing and Pin Assignments...........................................................................................183
10.3.2 K12 Pinouts..................................................................................................................................................187
10.4 Module Signal Description Tables................................................................................................................................188
10.4.1 Core Modules...............................................................................................................................................188
10.4.2 System Modules...........................................................................................................................................189
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10.4.3 Clock Modules.............................................................................................................................................190
10.4.4 Memories and Memory Interfaces...............................................................................................................190
10.4.5 Analog..........................................................................................................................................................190
10.4.6 Timer Modules.............................................................................................................................................191
10.4.7 Communication Interfaces...........................................................................................................................193
10.4.8 Human-Machine Interfaces (HMI)..............................................................................................................195
Chapter 11
Port control and interrupts (PORT)
11.1 Introduction...................................................................................................................................................................197
11.2 Overview.......................................................................................................................................................................197
11.2.1 Features........................................................................................................................................................197
11.2.2 Modes of operation......................................................................................................................................198
11.3 External signal description............................................................................................................................................199
11.4 Detailed signal description............................................................................................................................................199
11.5 Memory map and register definition.............................................................................................................................199
11.5.1 Pin Control Register n (PORTx_PCRn).......................................................................................................206
11.5.2 Global Pin Control Low Register (PORTx_GPCLR)..................................................................................208
11.5.3 Global Pin Control High Register (PORTx_GPCHR).................................................................................209
11.5.4 Interrupt Status Flag Register (PORTx_ISFR)............................................................................................210
11.5.5 Digital Filter Enable Register (PORTx_DFER)...........................................................................................210
11.5.6 Digital Filter Clock Register (PORTx_DFCR)............................................................................................211
11.5.7 Digital Filter Width Register (PORTx_DFWR)..........................................................................................211
11.6 Functional description...................................................................................................................................................212
11.6.1 Pin control....................................................................................................................................................212
11.6.2 Global pin control........................................................................................................................................213
11.6.3 External interrupts........................................................................................................................................213
11.6.4 Digital filter..................................................................................................................................................214
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Chapter 12
System Integration Module (SIM)
12.1 Introduction...................................................................................................................................................................215
12.1.1 Features........................................................................................................................................................215
12.2 Memory map and register definition.............................................................................................................................216
12.2.1 System Options Register 1 (SIM_SOPT1)..................................................................................................217
12.2.2 System Options Register 2 (SIM_SOPT2)..................................................................................................218
12.2.3 System Options Register 4 (SIM_SOPT4)..................................................................................................220
12.2.4 System Options Register 5 (SIM_SOPT5)..................................................................................................222
12.2.5 System Options Register 7 (SIM_SOPT7)..................................................................................................224
12.2.6 System Device Identification Register (SIM_SDID)...................................................................................225
12.2.7 System Clock Gating Control Register 4 (SIM_SCGC4)............................................................................226
12.2.8 System Clock Gating Control Register 5 (SIM_SCGC5)............................................................................228
12.2.9 System Clock Gating Control Register 6 (SIM_SCGC6)............................................................................230
12.2.10 System Clock Gating Control Register 7 (SIM_SCGC7)............................................................................233
12.2.11 System Clock Divider Register 1 (SIM_CLKDIV1)...................................................................................233
12.2.12 System Clock Divider Register 2 (SIM_CLKDIV2)...................................................................................235
12.2.13 Flash Configuration Register 1 (SIM_FCFG1)...........................................................................................236
12.2.14 Flash Configuration Register 2 (SIM_FCFG2)...........................................................................................239
12.2.15 Unique Identification Register High (SIM_UIDH).....................................................................................240
12.2.16 Unique Identification Register Mid-High (SIM_UIDMH)..........................................................................241
12.2.17 Unique Identification Register Mid Low (SIM_UIDML)...........................................................................241
12.2.18 Unique Identification Register Low (SIM_UIDL)......................................................................................242
12.3 Functional description...................................................................................................................................................242
Chapter 13
Reset Control Module (RCM)
13.1 Introduction...................................................................................................................................................................243
13.2 Reset memory map and register descriptions...............................................................................................................243
13.2.1 System Reset Status Register 0 (RCM_SRS0)............................................................................................244
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13.2.2 System Reset Status Register 1 (RCM_SRS1)............................................................................................245
13.2.3 Reset Pin Filter Control register (RCM_RPFC)..........................................................................................247
13.2.4 Reset Pin Filter Width register (RCM_RPFW)...........................................................................................248
13.2.5 Mode Register (RCM_MR).........................................................................................................................249
Chapter 14
System Mode Controller (SMC)
14.1 Introduction...................................................................................................................................................................251
14.2 Modes of operation.......................................................................................................................................................251
14.3 Memory map and register descriptions.........................................................................................................................253
14.3.1 Power Mode Protection register (SMC_PMPROT).....................................................................................254
14.3.2 Power Mode Control register (SMC_PMCTRL).........................................................................................255
14.3.3 VLLS Control register (SMC_VLLSCTRL)...............................................................................................257
14.3.4 Power Mode Status register (SMC_PMSTAT)...........................................................................................258
14.4 Functional description...................................................................................................................................................259
14.4.1 Power mode transitions................................................................................................................................259
14.4.2 Power mode entry/exit sequencing..............................................................................................................261
14.4.3 Run modes....................................................................................................................................................263
14.4.4 Wait modes..................................................................................................................................................265
14.4.5 Stop modes...................................................................................................................................................266
14.4.6 Debug in low power modes.........................................................................................................................269
Chapter 15
Power Management Controller (PMC)
15.1 Introduction...................................................................................................................................................................271
15.2 Features.........................................................................................................................................................................271
15.3 Low-voltage detect (LVD) system................................................................................................................................271
15.3.1 LVD reset operation.....................................................................................................................................272
15.3.2 LVD interrupt operation...............................................................................................................................272
15.3.3 Low-voltage warning (LVW) interrupt operation.......................................................................................272
15.4 I/O retention..................................................................................................................................................................273
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15.5 Memory map and register descriptions.........................................................................................................................273
15.5.1 Low Voltage Detect Status And Control 1 register (PMC_LVDSC1)........................................................274
15.5.2 Low Voltage Detect Status And Control 2 register (PMC_LVDSC2)........................................................275
15.5.3 Regulator Status And Control register (PMC_REGSC)..............................................................................276
Chapter 16
Low-Leakage Wakeup Unit (LLWU)
16.1 Introduction...................................................................................................................................................................279
16.1.1 Features........................................................................................................................................................279
16.1.2 Modes of operation......................................................................................................................................280
16.1.3 Block diagram..............................................................................................................................................281
16.2 LLWU signal descriptions............................................................................................................................................282
16.3 Memory map/register definition...................................................................................................................................283
16.3.1 LLWU Pin Enable 1 register (LLWU_PE1)................................................................................................284
16.3.2 LLWU Pin Enable 2 register (LLWU_PE2)................................................................................................285
16.3.3 LLWU Pin Enable 3 register (LLWU_PE3)................................................................................................286
16.3.4 LLWU Pin Enable 4 register (LLWU_PE4)................................................................................................287
16.3.5 LLWU Module Enable register (LLWU_ME)............................................................................................288
16.3.6 LLWU Flag 1 register (LLWU_F1).............................................................................................................290
16.3.7 LLWU Flag 2 register (LLWU_F2).............................................................................................................291
16.3.8 LLWU Flag 3 register (LLWU_F3).............................................................................................................293
16.3.9 LLWU Pin Filter 1 register (LLWU_FILT1)..............................................................................................295
16.3.10 LLWU Pin Filter 2 register (LLWU_FILT2)..............................................................................................296
16.3.11 LLWU Reset Enable register (LLWU_RST)...............................................................................................297
16.4 Functional description...................................................................................................................................................298
16.4.1 LLS mode.....................................................................................................................................................298
16.4.2 VLLS modes................................................................................................................................................298
16.4.3 Initialization.................................................................................................................................................299
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Chapter 17
Miscellaneous Control Module (MCM)
17.1 Introduction...................................................................................................................................................................301
17.1.1 Features........................................................................................................................................................301
17.2 Memory map/register descriptions...............................................................................................................................301
17.2.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)................................................................302
17.2.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC)............................................................302
17.2.3 Crossbar Switch (AXBS) Control Register (MCM_PLACR).....................................................................303
Chapter 18
Crossbar Switch Lite (AXBS-Lite)
18.1 Introduction...................................................................................................................................................................305
18.1.1 Features........................................................................................................................................................305
18.2 Memory Map / Register Definition...............................................................................................................................305
18.3 Functional Description..................................................................................................................................................306
18.3.1 General operation.........................................................................................................................................306
18.3.2 Arbitration....................................................................................................................................................307
18.4 Initialization/application information...........................................................................................................................308
Chapter 19
Peripheral Bridge (AIPS-Lite)
19.1 Introduction...................................................................................................................................................................309
19.1.1 Features........................................................................................................................................................309
19.1.2 General operation.........................................................................................................................................309
19.2 Functional description...................................................................................................................................................310
19.2.1 Access support.............................................................................................................................................310
Chapter 20
Direct Memory Access Multiplexer (DMAMUX)
20.1 Introduction...................................................................................................................................................................311
20.1.1 Overview......................................................................................................................................................311
20.1.2 Features........................................................................................................................................................312
20.1.3 Modes of operation......................................................................................................................................312
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20.2 External signal description............................................................................................................................................313
20.3 Memory map/register definition...................................................................................................................................313
20.3.1 Channel Configuration register (DMAMUX_CHCFGn)............................................................................314
20.4 Functional description...................................................................................................................................................315
20.4.1 DMA channels with periodic triggering capability......................................................................................315
20.4.2 DMA channels with no triggering capability...............................................................................................317
20.4.3 Always-enabled DMA sources....................................................................................................................317
20.5 Initialization/application information...........................................................................................................................319
20.5.1 Reset.............................................................................................................................................................319
20.5.2 Enabling and configuring sources................................................................................................................319
Chapter 21
Direct Memory Access Controller (eDMA)
21.1 Introduction...................................................................................................................................................................323
21.1.1 Block diagram..............................................................................................................................................323
21.1.2 Block parts...................................................................................................................................................324
21.1.3 Features........................................................................................................................................................325
21.2 Modes of operation.......................................................................................................................................................327
21.3 Memory map/register definition...................................................................................................................................327
21.3.1 Control Register (DMA_CR).......................................................................................................................339
21.3.2 Error Status Register (DMA_ES)................................................................................................................341
21.3.3 Enable Request Register (DMA_ERQ).......................................................................................................343
21.3.4 Enable Error Interrupt Register (DMA_EEI)...............................................................................................345
21.3.5 Clear Enable Error Interrupt Register (DMA_CEEI)..................................................................................347
21.3.6 Set Enable Error Interrupt Register (DMA_SEEI)......................................................................................348
21.3.7 Clear Enable Request Register (DMA_CERQ)...........................................................................................349
21.3.8 Set Enable Request Register (DMA_SERQ)...............................................................................................350
21.3.9 Clear DONE Status Bit Register (DMA_CDNE)........................................................................................351
21.3.10 Set START Bit Register (DMA_SSRT)......................................................................................................352
21.3.11 Clear Error Register (DMA_CERR)............................................................................................................353
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21.3.12 Clear Interrupt Request Register (DMA_CINT).........................................................................................354
21.3.13 Interrupt Request Register (DMA_INT)......................................................................................................355
21.3.14 Error Register (DMA_ERR)........................................................................................................................357
21.3.15 Hardware Request Status Register (DMA_HRS)........................................................................................360
21.3.16 Channel n Priority Register (DMA_DCHPRIn)..........................................................................................362
21.3.17 TCD Source Address (DMA_TCDn_SADDR)...........................................................................................363
21.3.18 TCD Signed Source Address Offset (DMA_TCDn_SOFF)........................................................................363
21.3.19 TCD Transfer Attributes (DMA_TCDn_ATTR).........................................................................................364
21.3.20 TCD Minor Byte Count (Minor Loop Disabled) (DMA_TCDn_NBYTES_MLNO).................................365
21.3.21 TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
(DMA_TCDn_NBYTES_MLOFFNO).......................................................................................................365
21.3.22 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
(DMA_TCDn_NBYTES_MLOFFYES).....................................................................................................367
21.3.23 TCD Last Source Address Adjustment (DMA_TCDn_SLAST).................................................................368
21.3.24 TCD Destination Address (DMA_TCDn_DADDR)...................................................................................368
21.3.25 TCD Signed Destination Address Offset (DMA_TCDn_DOFF)................................................................369
21.3.26 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
(DMA_TCDn_CITER_ELINKYES)...........................................................................................................369
21.3.27 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
(DMA_TCDn_CITER_ELINKNO)............................................................................................................371
21.3.28 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCDn_DLASTSGA)..........372
21.3.29 TCD Control and Status (DMA_TCDn_CSR)............................................................................................372
21.3.30 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
(DMA_TCDn_BITER_ELINKYES)...........................................................................................................375
21.3.31 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
(DMA_TCDn_BITER_ELINKNO)............................................................................................................376
21.4 Functional description...................................................................................................................................................377
21.4.1 eDMA basic data flow.................................................................................................................................377
21.4.2 Error reporting and handling........................................................................................................................380
21.4.3 Channel preemption.....................................................................................................................................381
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21.4.4 Performance.................................................................................................................................................382
21.5 Initialization/application information...........................................................................................................................386
21.5.1 eDMA initialization.....................................................................................................................................386
21.5.2 Programming errors.....................................................................................................................................388
21.5.3 Arbitration mode considerations..................................................................................................................389
21.5.4 Performing DMA transfers (examples)........................................................................................................389
21.5.5 Monitoring transfer descriptor status...........................................................................................................393
21.5.6 Channel Linking...........................................................................................................................................395
21.5.7 Dynamic programming................................................................................................................................396
Chapter 22
External Watchdog Monitor (EWM)
22.1 Introduction...................................................................................................................................................................401
22.1.1 Features........................................................................................................................................................401
22.1.2 Modes of Operation.....................................................................................................................................402
22.1.3 Block Diagram.............................................................................................................................................403
22.2 EWM Signal Descriptions............................................................................................................................................404
22.3 Memory Map/Register Definition.................................................................................................................................404
22.3.1 Control Register (EWM_CTRL).................................................................................................................404
22.3.2 Service Register (EWM_SERV)..................................................................................................................405
22.3.3 Compare Low Register (EWM_CMPL)......................................................................................................405
22.3.4 Compare High Register (EWM_CMPH).....................................................................................................406
22.4 Functional Description..................................................................................................................................................407
22.4.1 The EWM_out Signal..................................................................................................................................407
22.4.2 The EWM_in Signal....................................................................................................................................408
22.4.3 EWM Counter..............................................................................................................................................408
22.4.4 EWM Compare Registers............................................................................................................................408
22.4.5 EWM Refresh Mechanism...........................................................................................................................409
22.4.6 EWM Interrupt.............................................................................................................................................409
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Chapter 23
Watchdog Timer (WDOG)
23.1 Introduction...................................................................................................................................................................411
23.2 Features.........................................................................................................................................................................411
23.3 Functional overview......................................................................................................................................................413
23.3.1 Unlocking and updating the watchdog.........................................................................................................414
23.3.2 Watchdog configuration time (WCT)..........................................................................................................415
23.3.3 Refreshing the watchdog..............................................................................................................................416
23.3.4 Windowed mode of operation......................................................................................................................416
23.3.5 Watchdog disabled mode of operation.........................................................................................................416
23.3.6 Low-power modes of operation...................................................................................................................417
23.3.7 Debug modes of operation...........................................................................................................................417
23.4 Testing the watchdog....................................................................................................................................................418
23.4.1 Quick test.....................................................................................................................................................418
23.4.2 Byte test........................................................................................................................................................419
23.5 Backup reset generator..................................................................................................................................................420
23.6 Generated resets and interrupts.....................................................................................................................................420
23.7 Memory map and register definition.............................................................................................................................421
23.7.1 Watchdog Status and Control Register High (WDOG_STCTRLH)...........................................................422
23.7.2 Watchdog Status and Control Register Low (WDOG_STCTRLL)............................................................423
23.7.3 Watchdog Time-out Value Register High (WDOG_TOVALH).................................................................424
23.7.4 Watchdog Time-out Value Register Low (WDOG_TOVALL)..................................................................424
23.7.5 Watchdog Window Register High (WDOG_WINH)..................................................................................425
23.7.6 Watchdog Window Register Low (WDOG_WINL)...................................................................................425
23.7.7 Watchdog Refresh register (WDOG_REFRESH).......................................................................................426
23.7.8 Watchdog Unlock register (WDOG_UNLOCK).........................................................................................426
23.7.9 Watchdog Timer Output Register High (WDOG_TMROUTH).................................................................426
23.7.10 Watchdog Timer Output Register Low (WDOG_TMROUTL)..................................................................427
23.7.11 Watchdog Reset Count register (WDOG_RSTCNT)..................................................................................427
K12 Sub-Family Reference Manual, Rev. 4, February 2013
18 Freescale Semiconductor, Inc.
Section number Title Page
23.7.12 Watchdog Prescaler register (WDOG_PRESC)..........................................................................................428
23.8 Watchdog operation with 8-bit access..........................................................................................................................428
23.8.1 General guideline.........................................................................................................................................428
23.8.2 Refresh and unlock operations with 8-bit access.........................................................................................428
23.9 Restrictions on watchdog operation..............................................................................................................................429
Chapter 24
Multipurpose Clock Generator (MCG)
24.1 Introduction...................................................................................................................................................................433
24.1.1 Features........................................................................................................................................................433
24.1.2 Modes of Operation.....................................................................................................................................436
24.2 External Signal Description..........................................................................................................................................437
24.3 Memory Map/Register Definition.................................................................................................................................437
24.3.1 MCG Control 1 Register (MCG_C1)...........................................................................................................438
24.3.2 MCG Control 2 Register (MCG_C2)...........................................................................................................439
24.3.3 MCG Control 3 Register (MCG_C3)...........................................................................................................440
24.3.4 MCG Control 4 Register (MCG_C4)...........................................................................................................441
24.3.5 MCG Control 5 Register (MCG_C5)...........................................................................................................442
24.3.6 MCG Control 6 Register (MCG_C6)...........................................................................................................443
24.3.7 MCG Status Register (MCG_S)..................................................................................................................445
24.3.8 MCG Status and Control Register (MCG_SC)............................................................................................446
24.3.9 MCG Auto Trim Compare Value High Register (MCG_ATCVH)............................................................448
24.3.10 MCG Auto Trim Compare Value Low Register (MCG_ATCVL)..............................................................448
24.3.11 MCG Control 7 Register (MCG_C7)...........................................................................................................448
24.3.12 MCG Control 8 Register (MCG_C8)...........................................................................................................449
24.3.13 MCG Control 9 Register (MCG_C9)...........................................................................................................450
24.3.14 MCG Control 10 Register (MCG_C10).......................................................................................................450
24.4 Functional Description..................................................................................................................................................451
24.4.1 MCG mode state diagram............................................................................................................................451
24.4.2 Low Power Bit Usage..................................................................................................................................455
K12 Sub-Family Reference Manual, Rev. 4, February 2013
Freescale Semiconductor, Inc. 19
Section number Title Page
24.4.3 MCG Internal Reference Clocks..................................................................................................................455
24.4.4 External Reference Clock............................................................................................................................456
24.4.5 MCG Fixed frequency clock .......................................................................................................................456
24.4.6 MCG PLL clock ..........................................................................................................................................457
24.4.7 MCG Auto TRIM (ATM)............................................................................................................................457
24.5 Initialization / Application information........................................................................................................................458
24.5.1 MCG module initialization sequence...........................................................................................................458
24.5.2 Using a 32.768 kHz reference......................................................................................................................461
24.5.3 MCG mode switching..................................................................................................................................461
Chapter 25
Oscillator (OSC)
25.1 Introduction...................................................................................................................................................................471
25.2 Features and Modes......................................................................................................................................................471
25.3 Block Diagram..............................................................................................................................................................472
25.4 OSC Signal Descriptions..............................................................................................................................................472
25.5 External Crystal / Resonator Connections....................................................................................................................473
25.6 External Clock Connections.........................................................................................................................................474
25.7 Memory Map/Register Definitions...............................................................................................................................475
25.7.1 OSC Memory Map/Register Definition.......................................................................................................475
25.8 Functional Description..................................................................................................................................................476
25.8.1 OSC Module States......................................................................................................................................476
25.8.2 OSC Module Modes.....................................................................................................................................478
25.8.3 Counter.........................................................................................................................................................480
25.8.4 Reference Clock Pin Requirements.............................................................................................................480
25.9 Reset..............................................................................................................................................................................480
25.10 Low Power Modes Operation.......................................................................................................................................481
25.11 Interrupts.......................................................................................................................................................................481
K12 Sub-Family Reference Manual, Rev. 4, February 2013
20 Freescale Semiconductor, Inc.
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NXP K12_50 Reference guide

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Reference guide

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