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Analog Devices Blackfin ADSP-BF537 Hardware Reference Manual

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ADSP-BF537 Blackfin
®
Processor
Hardware Reference
Revision 2.0, December 2005
Part Number
82-000555-01
Analog Devices, Inc.
One Technology Way
Norwood, Mass. 02062-9106
a
Copyright Information
© 2005 Analog Devices, Inc., ALL RIGHTS RESERVED. This docu-
ment may not be reproduced in any form without prior, express written
consent from Analog Devices, Inc.
Printed in the USA.
Disclaimer
Analog Devices, Inc. reserves the right to change this product without
prior notice. Information furnished by Analog Devices is believed to be
accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use; nor for any infringement of patents or other rights of
third parties which may result from its use. No license is granted by impli-
cation or otherwise under the patent rights of Analog Devices, Inc.
Trademark and Service Mark Notice
The Analog Devices logo, Blackfin, the Blackfin logo, CrossCore, EZ-KIT
Lite, SHARC, TigerSHARC, and VisualDSP++ are registered trademarks
of Analog Devices, Inc.
All other brand and product names are trademarks or service marks of
their respective owners.
ADSP-BF537 Blackfin Processor Hardware Reference iii
CONTENTS
PREFACE
Purpose of This Manual ............................................................... xliii
Intended Audience ....................................................................... xliii
Manual Contents .......................................................................... xliv
What’s New in This Manual ......................................................... xlvii
Technical or Customer Support .................................................... xlvii
Supported Processors .................................................................. xlviii
Product Information ..................................................................... xlix
MyAnalog.com ........................................................................ xlix
Processor Product Information ................................................. xlix
Related Documents ..................................................................... l
Online Technical Documentation ............................................... li
Accessing Documentation From VisualDSP++ ....................... lii
Accessing Documentation From Windows ............................. lii
Accessing Documentation From the Web .............................. liii
Printed Manuals ....................................................................... liii
VisualDSP++ Documentation Set ......................................... liii
Hardware Tools Manuals ...................................................... liv
Processor Manuals ................................................................ liv
Data Sheets .......................................................................... liv
Contents
iv ADSP-BF537 Blackfin Processor Hardware Reference
Conventions .................................................................................... lv
Register Diagram Conventions .................................................. lvi
INTRODUCTION
Peripherals .................................................................................... 1-1
Memory Architecture .................................................................... 1-4
Internal Memory ..................................................................... 1-6
External Memory .................................................................... 1-6
I/O Memory Space .................................................................. 1-7
DMA Support .............................................................................. 1-7
External Bus Interface Unit ........................................................... 1-9
PC133 SDRAM Controller ..................................................... 1-9
Asynchronous Controller ........................................................ 1-9
Ports .......................................................................................... 1-10
General-Purpose I/O (GPIO) ................................................ 1-10
Two-Wire Interface ..................................................................... 1-11
Controller Area Network ............................................................ 1-12
Ethernet MAC ............................................................................ 1-14
Parallel Peripheral Interface ......................................................... 1-14
SPORT Controllers .................................................................... 1-16
Serial Peripheral Interface (SPI) Port ........................................... 1-18
Timers ....................................................................................... 1-18
UART Ports ............................................................................... 1-19
Real-Time Clock ........................................................................ 1-20
Watchdog Timer ......................................................................... 1-21
ADSP-BF537 Blackfin Processor Hardware Reference v
Contents
Clock Signals .............................................................................. 1-22
Dynamic Power Management ...................................................... 1-23
Full On Mode (Maximum Performance) ................................ 1-23
Active Mode (Moderate Power Savings) .................................. 1-23
Sleep Mode (High Power Savings) .......................................... 1-23
Deep Sleep Mode (Maximum Power Savings) ......................... 1-24
Hibernate State ..................................................................... 1-24
Voltage Regulation ...................................................................... 1-24
Boot Modes ................................................................................ 1-25
Instruction Set Description ......................................................... 1-27
Development Tools ..................................................................... 1-29
CHIP BUS HIERARCHY
Overview ...................................................................................... 2-1
Interface Overview ........................................................................ 2-3
Internal Clocks ........................................................................ 2-4
Core Bus Overview .................................................................. 2-4
Peripheral Access Bus (PAB) ..................................................... 2-6
PAB Arbitration .................................................................. 2-6
PAB Agents (Masters, Slaves) ............................................... 2-6
PAB Performance ................................................................ 2-7
DMA Access Bus (DAB), DMA Core Bus (DCB),
DMA External Bus (DEB) .................................................... 2-8
DAB Arbitration ................................................................. 2-8
DAB Bus Agents (Masters) .................................................. 2-9
DAB, DCB, and DEB Performance ................................... 2-10
Contents
vi ADSP-BF537 Blackfin Processor Hardware Reference
External Access Bus (EAB) .................................................... 2-10
Arbitration of the External Bus .............................................. 2-11
DEB/EAB Performance ......................................................... 2-11
MEMORY
Memory Architecture .................................................................... 3-1
L1 Instruction SRAM ................................................................... 3-5
L1 Data SRAM ............................................................................ 3-7
L1 Data Cache ............................................................................. 3-8
Boot ROM ................................................................................... 3-8
External Memory .......................................................................... 3-8
Processor-Specific MMRs .............................................................. 3-8
DMEM_CONTROL Register ................................................. 3-9
DTEST_COMMAND Register ............................................ 3-10
SYSTEM INTERRUPTS
Overview ...................................................................................... 4-1
Features .................................................................................. 4-1
Interfaces ...................................................................................... 4-2
Description of Operation .............................................................. 4-2
Events and Sequencing ............................................................ 4-2
System Peripheral Interrupts .................................................... 4-7
Programming Model ................................................................... 4-14
System Interrupt Initialization ............................................... 4-14
System Interrupt Processing Summary ................................... 4-14
ADSP-BF537 Blackfin Processor Hardware Reference vii
Contents
System Interrupt Controller Registers .......................................... 4-16
SIC_IARx Registers ............................................................... 4-18
SIC_IMASK Register ............................................................ 4-20
SIC_ISR Register .................................................................. 4-21
SIC_IWR Register ................................................................. 4-22
Programming Examples ............................................................... 4-23
Clearing Interrupt Requests ................................................... 4-23
DIRECT MEMORY ACCESS
Overview and Features .................................................................. 5-1
DMA Controller Overview ............................................................ 5-5
External Interfaces ................................................................... 5-6
Internal Interfaces ................................................................... 5-6
Peripheral DMA ...................................................................... 5-7
Memory DMA ........................................................................ 5-9
Handshaked Memory DMA Mode .................................... 5-11
Modes of Operation .................................................................... 5-12
Register-based DMA Operation ............................................. 5-12
Stop Mode ........................................................................ 5-13
Autobuffer Mode .............................................................. 5-14
Two-Dimensional DMA Operation ........................................ 5-14
Examples of Two-Dimensional DMA ................................ 5-15
Descriptor-based DMA Operation ......................................... 5-16
Descriptor List Mode ........................................................ 5-17
Descriptor Array Mode ..................................................... 5-18
Contents
viii ADSP-BF537 Blackfin Processor Hardware Reference
Variable Descriptor Size .................................................... 5-18
Mixing Flow Modes .......................................................... 5-19
Functional Description ............................................................... 5-20
DMA Operation Flow ........................................................... 5-20
DMA Startup ................................................................... 5-20
DMA Refresh ................................................................... 5-25
Work Unit Transitions ...................................................... 5-27
DMA Transmit and MDMA Source .............................. 5-28
DMA Receive ............................................................... 5-30
Stopping DMA Transfers .................................................. 5-31
DMA Errors (Aborts) ............................................................ 5-32
DMA Control Commands .................................................... 5-34
Restrictions ...................................................................... 5-38
Transmit Restart or Finish ............................................. 5-38
Receive Restart or Finish ............................................... 5-39
Handshaked Memory DMA Operation .................................. 5-40
Pipelining DMA Requests ................................................. 5-41
HMDMA Interrupts ......................................................... 5-43
DMA Performance ................................................................ 5-44
DMA Throughput ............................................................ 5-45
Memory DMA Timing Details .......................................... 5-48
Static Channel Prioritization ............................................. 5-48
Temporary DMA Urgency ................................................ 5-50
Memory DMA Priority and Scheduling ............................. 5-51
Traffic Control ................................................................. 5-53
ADSP-BF537 Blackfin Processor Hardware Reference ix
Contents
Programming Model ................................................................... 5-55
Synchronization of Software and DMA .................................. 5-56
Single-buffer DMA Transfers ............................................. 5-58
Continuous Transfers Using Autobuffering ........................ 5-58
Descriptor Structures ........................................................ 5-60
Descriptor Queue Management ......................................... 5-61
Descriptor Queue Using Interrupts on Every Descriptor 5-62
Descriptor Queue Using Minimal Interrupts .................. 5-63
Software Triggered Descriptor Fetches ............................... 5-65
DMA Registers ........................................................................... 5-67
DMA Channel Registers ........................................................ 5-68
DMAx_PERIPHERAL_MAP/
MDMA_yy_PERIPHERAL_MAP Registers ................... 5-71
DMAx_CONFIG/MDMA_yy_CONFIG Registers ........... 5-74
DMAx_IRQ_STATUS/
MDMA_yy_IRQ_STATUS Registers .............................. 5-78
DMAx_START_ADDR/
MDMA_yy_START_ADDR Registers ............................ 5-82
DMAx_CURR_ADDR/MDMA_yy_CURR_ADDR
Registers ........................................................................ 5-83
DMAx_X_COUNT/MDMA_yy_X_COUNT Registers .... 5-85
DMAx_CURR_X_COUNT/
MDMA_yy_CURR_X_COUNT Registers ..................... 5-86
DMAx_X_MODIFY/
MDMA_yy_X_MODIFY Registers ................................ 5-88
Contents
x ADSP-BF537 Blackfin Processor Hardware Reference
DMAx_Y_COUNT/
MDMA_yy_Y_COUNT Registers ................................. 5-90
DMAx_CURR_Y_COUNT/
MDMA_yy_CURR_Y_COUNT Registers ..................... 5-91
DMAx_Y_MODIFY/MDMA_yy_Y_MODIFY
Registers ........................................................................ 5-93
DMAx_NEXT_DESC_PTR/
MDMA_yy_NEXT_DESC_PTR Registers ..................... 5-94
DMAx_CURR_DESC_PTR/
MDMA_yy_CURR_DESC_PTR Registers .................... 5-96
HMDMA Registers ............................................................... 5-98
HMDMAx_CONTROL Registers .................................... 5-99
HMDMAx_BCINIT Registers ........................................ 5-101
HMDMAx_BCOUNT Registers .................................... 5-101
HMDMAx_ECOUNT Registers ..................................... 5-102
HMDMAx_ECINIT Registers ........................................ 5-103
HMDMAx_ECURGENT Registers ................................ 5-104
HMDMAx_ECOVERFLOW Registers ........................... 5-104
DMA Traffic Control Registers ............................................ 5-105
DMA_TC_PER Register ................................................ 5-105
DMA_TC_CNT Register ............................................... 5-106
Programming Examples ............................................................ 5-107
Register-Based 2D Memory DMA ....................................... 5-107
Initializing Descriptors in Memory ...................................... 5-111
Software-Triggered Descriptor Fetch Example ...................... 5-114
Handshaked Memory DMA Example .................................. 5-116
ADSP-BF537 Blackfin Processor Hardware Reference xi
Contents
EXTERNAL BUS INTERFACE UNIT
EBIU Overview ............................................................................ 6-1
Block Diagram ........................................................................ 6-4
Internal Memory Interfaces ...................................................... 6-5
Registers .................................................................................. 6-6
Shared Pins ............................................................................. 6-6
System Clock .......................................................................... 6-7
Error Detection ....................................................................... 6-7
Bus Request and Grant ............................................................ 6-8
Operation ............................................................................... 6-8
AMC Overview and Features ......................................................... 6-9
Features ................................................................................... 6-9
Asynchronous Memory Interface .............................................. 6-9
Asynchronous Memory Address Decode ............................ 6-10
AMC Pin Description ................................................................. 6-10
AMC Description of Operation ................................................... 6-11
Avoiding Bus Contention ...................................................... 6-11
External Access Extension .................................................. 6-12
AMC Functional Description ...................................................... 6-12
Programmable Timing Characteristics .................................... 6-12
Asynchronous Reads ......................................................... 6-13
Asynchronous Writes ......................................................... 6-14
Adding External Access Extension ..................................... 6-16
Byte Enables .......................................................................... 6-18
Contents
xii ADSP-BF537 Blackfin Processor Hardware Reference
AMC Programming Model ......................................................... 6-18
AMC Registers ........................................................................... 6-21
EBIU_AMGCTL Register ..................................................... 6-21
EBIU_AMBCTL0 and EBIU_AMBCTL1 Registers ............... 6-21
AMC Programming Examples ..................................................... 6-24
SDC Overview and Features ....................................................... 6-25
Features ................................................................................ 6-25
SDRAM Configurations Supported ....................................... 6-26
SDRAM External Bank Size .................................................. 6-27
SDC Address Mapping .......................................................... 6-27
Internal SDRAM Bank Select ................................................ 6-29
Parallel Connection of SDRAMs ........................................... 6-29
SDC Interface Overview ............................................................. 6-30
SDC Pin Description ............................................................ 6-30
SDRAM Performance ........................................................... 6-31
SDC Description of Operation ................................................... 6-32
Definition of SDRAM Architecture Terms ............................. 6-32
Refresh ............................................................................. 6-32
Row Activation ................................................................. 6-32
Column Read/Write ......................................................... 6-32
Row Precharge .................................................................. 6-33
Internal Bank ................................................................... 6-33
External Bank ................................................................... 6-33
Memory Size .................................................................... 6-33
ADSP-BF537 Blackfin Processor Hardware Reference xiii
Contents
Burst Length ..................................................................... 6-33
Burst Type ........................................................................ 6-34
CAS Latency ..................................................................... 6-34
Data I/O Mask Function ................................................... 6-34
SDRAM Commands ......................................................... 6-34
Mode Register Set (MRS) command .................................. 6-34
Extended Mode Register Set (EMRS) command ................ 6-34
Bank Activate command .................................................... 6-35
Read/Write command ....................................................... 6-35
Precharge/Precharge All Command .................................... 6-35
Auto-refresh command ...................................................... 6-35
Enter Self-Refresh Mode ................................................... 6-35
Exit Self-Refresh Mode ...................................................... 6-36
SDC Timing Specs ................................................................ 6-36
tMRD .............................................................................. 6-36
tRAS ................................................................................ 6-36
CL .................................................................................... 6-37
tRCD ............................................................................... 6-37
tRRD ............................................................................... 6-37
tWR ................................................................................. 6-37
tRP ................................................................................... 6-38
tRC .................................................................................. 6-38
tRFC ................................................................................ 6-38
Contents
xiv ADSP-BF537 Blackfin Processor Hardware Reference
tXSR ................................................................................ 6-38
tREF ................................................................................ 6-39
tREFI ............................................................................... 6-39
SDC Functional Description ....................................................... 6-39
SDC Operation .................................................................... 6-39
SDC Address Muxing ....................................................... 6-42
Multibank Operation ........................................................ 6-43
Core and DMA Arbitration .............................................. 6-44
Changing System Clock During Runtime .......................... 6-44
Changing Power Management During Runtime ................ 6-46
Deep Sleep Mode .......................................................... 6-46
Hibernate State ............................................................. 6-46
Shared SDRAM ................................................................ 6-46
SDC Commands ................................................................... 6-47
Mode Register Set Command ............................................ 6-49
Extended Mode Register Set Command
(Mobile SDRAM) .......................................................... 6-50
Bank Activation Command ............................................... 6-51
Read/Write Command ...................................................... 6-51
Write Command With Data Mask .................................... 6-51
Single Precharge Command .............................................. 6-52
Precharge All Command ................................................... 6-52
Auto-Refresh Command ................................................... 6-52
ADSP-BF537 Blackfin Processor Hardware Reference xv
Contents
Self-Refresh Mode ............................................................. 6-53
Self-Refresh Entry Command ................................... 6-53
Self-Refresh Exit Command ..................................... 6-54
No Operation Command .................................................. 6-54
SDC SA10 Pin ...................................................................... 6-55
SDC Programming Model ........................................................... 6-55
SDC Configuration ............................................................... 6-56
Example SDRAM System Block Diagrams ............................. 6-58
SDC Register Definitions ............................................................ 6-60
EBIU_SDRRC Register ......................................................... 6-60
EBIU_SDBCTL Register ....................................................... 6-62
Using SDRAMs With Systems Smaller than 16M byte ....... 6-65
EBIU_SDGCTL Register ...................................................... 6-67
EBIU_SDSTAT Register ........................................................ 6-78
SDC Programming Examples ...................................................... 6-79
PARALLEL PERIPHERAL INTERFACE
Overview ...................................................................................... 7-1
Features ........................................................................................ 7-1
Interface Overview ........................................................................ 7-2
Description of Operation .............................................................. 7-5
Functional Description ................................................................. 7-6
ITU-R 656 Modes ................................................................... 7-6
ITU-R 656 Background ...................................................... 7-6
ITU-R 656 Input Modes ................................................... 7-10
Contents
xvi ADSP-BF537 Blackfin Processor Hardware Reference
Entire Field .................................................................. 7-10
Active Video Only ........................................................ 7-11
Vertical Blanking Interval (VBI) only ............................ 7-11
ITU-R 656 Output Mode ................................................. 7-12
Frame Synchronization in ITU-R 656 Modes .................... 7-12
General-Purpose PPI Modes .................................................. 7-13
Data Input (RX) Modes .................................................... 7-15
No Frame Syncs ............................................................ 7-16
1, 2, or 3 External Frame Syncs ..................................... 7-16
2 or 3 Internal Frame Syncs .......................................... 7-17
Data Output (TX) Modes ................................................. 7-18
No Frame Syncs ............................................................ 7-18
1 or 2 External Frame Syncs .......................................... 7-18
1, 2, or 3 Internal Frame Syncs ..................................... 7-19
Frame Synchronization in GP Modes ................................ 7-20
Modes With Internal Frame Syncs ................................. 7-20
Modes With External Frame Syncs ................................ 7-21
Programming Model ................................................................... 7-23
DMA Operation ................................................................... 7-23
PPI Registers .............................................................................. 7-26
PPI_CONTROL Register ..................................................... 7-26
PPI_STATUS Register .......................................................... 7-30
PPI_DELAY Register ............................................................ 7-34
PPI_COUNT Register .......................................................... 7-34
PPI_FRAME Register ........................................................... 7-35
ADSP-BF537 Blackfin Processor Hardware Reference xvii
Contents
Programming Examples ............................................................... 7-36
Data Transfer Scenarios ......................................................... 7-39
ETHERNET MAC
Overview ...................................................................................... 8-1
Features ................................................................................... 8-1
Interface Overview ........................................................................ 8-2
External Interface .................................................................... 8-4
Clocking ............................................................................. 8-4
Pins .................................................................................... 8-5
Internal Interface ..................................................................... 8-6
Power Management ............................................................. 8-7
Description of Operation .............................................................. 8-7
Protocol .................................................................................. 8-7
MII Management Interface .................................................. 8-7
Operation ............................................................................. 8-10
MII Management Interface Operation ............................... 8-10
Receive DMA Operation ................................................... 8-11
Frame Reception and Filtering ....................................... 8-13
RX Automatic Pad Stripping ......................................... 8-17
RX DMA Data Alignment ............................................. 8-18
RX DMA Buffer Structure ............................................. 8-18
RX Frame Status Buffer ................................................. 8-19
RX Frame Status Classification ...................................... 8-20
Contents
xviii ADSP-BF537 Blackfin Processor Hardware Reference
RX IP Frame Checksum Calculation ............................. 8-21
RX DMA Direction Errors ............................................ 8-22
Transmit DMA Operation ................................................ 8-24
Flexible Descriptor Structure ......................................... 8-27
TX DMA Data Alignment ............................................ 8-27
Late Collisions .............................................................. 8-28
TX Frame Status Classification ..................................... 8-29
TX DMA Direction Errors ............................................ 8-30
Power Management .......................................................... 8-31
Ethernet Operation in the Sleep State ............................ 8-33
Magic Packet Detection ................................................ 8-34
Remote Wake-up Filters ................................................ 8-35
Ethernet Event Interrupts ................................................. 8-38
RX/TX Frame Status Interrupt Operation ..................... 8-42
RX Frame Status Register Operation at
Startup and Shutdown ............................................... 8-43
TX Frame Status Register Operation at
Startup and Shutdown ............................................... 8-43
MAC Management Counters ............................................ 8-43
Programming Model ................................................................... 8-46
Configure MAC Pins ............................................................ 8-46
Multiplexing Scheme ........................................................ 8-47
CLKBUF ......................................................................... 8-47
Configure Interrupts ............................................................. 8-47
ADSP-BF537 Blackfin Processor Hardware Reference xix
Contents
Configure MAC Registers ...................................................... 8-48
MAC Address ................................................................... 8-48
MII Station Management .................................................. 8-48
Configure PHY ..................................................................... 8-50
Receive and Transmit Data .................................................... 8-50
Receiving Data .................................................................. 8-51
Transmitting Data ............................................................. 8-51
Ethernet MAC Register Definitions ............................................. 8-51
Control-Status Register Group ............................................... 8-63
EMAC_OPMODE Register .............................................. 8-64
EMAC_ADDRLO Register ............................................... 8-70
EMAC_ADDRHI Register ................................................ 8-71
EMAC_HASHLO and EMAC_HASHHI Registers ........... 8-72
EMAC_STAADD Register ................................................ 8-76
EMAC_STADAT Register ................................................. 8-78
EMAC_FLC Register ........................................................ 8-78
EMAC_VLAN1 and EMAC_VLAN2 Registers ................. 8-80
EMAC_WKUP_CTL Register .......................................... 8-81
EMAC_WKUP_FFMSK0, EMAC_WKUP_FFMSK1,
EMAC_WKUP_FFMSK2, and EMAC_WKUP_FFMSK3
Registers ........................................................................ 8-84
EMAC_WKUP_FFCMD Register .................................... 8-89
EMAC_WKUP_FFOFF Register ...................................... 8-91
EMAC_WKUP_FFCRC0 and
EMAC_WKUP_FFCRC1 Registers ................................ 8-92
Contents
xx ADSP-BF537 Blackfin Processor Hardware Reference
System Interface Register Group ............................................ 8-93
EMAC_SYSCTL Register ................................................. 8-93
EMAC_SYSTAT Register ................................................. 8-95
Ethernet MAC Frame Status Registers ................................... 8-97
EMAC_RX_STAT Register ............................................... 8-97
EMAC_RX_STKY Register ............................................ 8-103
EMAC_RX_IRQE Register ............................................. 8-107
EMAC_TX_STAT Register ............................................. 8-108
EMAC_TX_STKY Register ............................................ 8-112
EMAC_TX_IRQE Register ............................................ 8-114
EMAC_MMC_RIRQS Register ...................................... 8-115
EMAC_MMC_RIRQE Register ..................................... 8-117
EMAC_MMC_TIRQS Register ...................................... 8-119
EMAC_MMC_TIRQE Register ..................................... 8-121
MAC Management Counter Registers .................................. 8-123
EMAC_MMC_CTL Register .......................................... 8-124
Programming Examples ............................................................ 8-125
Ethernet Structures ............................................................. 8-126
MAC Address Setup ............................................................ 8-129
PHY Control Routines ........................................................ 8-130
CAN MODULE
Overview ...................................................................................... 9-1
Interface Overview ....................................................................... 9-2
CAN Mailbox Area ................................................................. 9-4
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