Analog Devices ADSP-BF56x Blackfin Reference

a

ADSP-BF53x/BF56x Blackfin

®

Processor

Programming Reference

Revision 1.2, February 2007

Part Number

82-000556-01

Analog Devices, Inc.

One Technology Way

Norwood, Mass. 02062-9106

Copyright Information

ment may not be reproduced in any form without prior, express written

consent from Analog Devices, Inc.

Printed in the USA.

Disclaimer

Analog Devices, Inc. reserves the right to change this product without

prior notice. Information furnished by Analog Devices is believed to be

accurate and reliable. However, no responsibility is assumed by Analog

Devices for its use; nor for any infringement of patents or other rights of

third parties which may result from its use. No license is granted by impli-

cation or otherwise under the patent rights of Analog Devices, Inc.

Trademark and Service Mark Notice

The Analog Devices logo, Blackfin, EZ-KIT Lite, SHARC, TigerSHARC,

and VisualDSP++ are registered trademarks of Analog Devices, Inc.

All other brand and product names are trademarks or service marks of

their respective owners.

ADSP-BF53x/BF56x Blackfin Processor Programming Reference iii

CONTENTS

PREFACE

Purpose of This Manual ................................................................ xxv

Intended Audience ........................................................................ xxv

Manual Contents ......................................................................... xxvi

What’s New in This Manual ........................................................ xxvii

Technical or Customer Support .................................................. xxviii

Supported Processors .................................................................... xxix

Product Information .................................................................... xxix

MyAnalog.com ........................................................................ xxx

Processor Product Information ................................................. xxx

Related Documents ................................................................ xxxi

Online Technical Documentation .......................................... xxxii

Accessing Documentation From VisualDSP++ .................. xxxiii

Accessing Documentation From Windows ........................ xxxiii

Accessing Documentation From the Web .......................... xxxiv

Contents

iv ADSP-BF53x/BF56x Blackfin Processor Programming Reference

Printed Manuals .................................................................... xxxiv

VisualDSP++ Documentation Set ...................................... xxxv

Hardware Tools Manuals ................................................... xxxv

Processor Manuals ............................................................. xxxv

Data Sheets ....................................................................... xxxv

Conventions ............................................................................... xxxvi

INTRODUCTION

Core Architecture ......................................................................... 1-1

Memory Architecture .................................................................... 1-4

Internal Memory ..................................................................... 1-5

External Memory .................................................................... 1-6

I/O Memory Space .................................................................. 1-6

Event Handling ............................................................................ 1-6

Core Event Controller (CEC) .................................................. 1-8

System Interrupt Controller (SIC) ........................................... 1-8

Syntax Conventions ...................................................................... 1-8

Case Sensitivity ....................................................................... 1-8

Free Format ............................................................................ 1-9

Instruction Delimiting ............................................................ 1-9

Comments ............................................................................ 1-10

Notation Conventions ................................................................ 1-10

Behavior Conventions ................................................................. 1-12

ADSP-BF53x/BF56x Blackfin Processor Programming Reference v

Contents

Glossary ...................................................................................... 1-13

Register Names ...................................................................... 1-13

Functional Units ................................................................... 1-14

Arithmetic Status Flags .......................................................... 1-15

Fractional Convention ........................................................... 1-16

Saturation ............................................................................. 1-17

Rounding and Truncating ...................................................... 1-19

Automatic Circular Addressing .............................................. 1-21

COMPUTATIONAL UNITS

Using Data Formats ...................................................................... 2-4

Binary String ........................................................................... 2-4

Unsigned ................................................................................. 2-4

Signed Numbers: Two’s-Complement ....................................... 2-5

Fractional Representation: 1.15 ................................................ 2-5

Register Files ................................................................................. 2-6

Data Register File .................................................................... 2-7

Accumulator Registers ............................................................. 2-8

Register File Instruction Summary ........................................... 2-9

Data Types .................................................................................. 2-11

Endianess .............................................................................. 2-13

ALU Data Types .................................................................... 2-14

Multiplier Data Types ............................................................ 2-14

Shifter Data Types ................................................................. 2-15

Arithmetic Formats Summary ................................................ 2-16

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vi ADSP-BF53x/BF56x Blackfin Processor Programming Reference

Using Multiplier Integer and Fractional Formats .................... 2-17

Rounding Multiplier Results ................................................. 2-19

Unbiased Rounding .......................................................... 2-20

Biased Rounding .............................................................. 2-22

Truncation ....................................................................... 2-23

Special Rounding Instructions ............................................... 2-24

Using Computational Status ....................................................... 2-24

ASTAT Register .......................................................................... 2-25

Arithmetic Logic Unit (ALU) ...................................................... 2-26

ALU Operations ................................................................... 2-26

Single 16-Bit Operations .................................................. 2-27

Dual 16-Bit Operations .................................................... 2-27

Quad 16-Bit Operations ................................................... 2-28

Single 32-Bit Operations .................................................. 2-29

Dual 32-Bit Operations .................................................... 2-29

ALU Instruction Summary .................................................... 2-30

ALU Division Support Features ............................................. 2-34

Special SIMD Video ALU Operations ................................... 2-35

Multiply Accumulators (Multipliers) ........................................... 2-35

Multiplier Operation ............................................................. 2-36

Placing Multiplier Results in Multiplier

Accumulator Registers .................................................... 2-37

Rounding or Saturating Multiplier Results ........................ 2-37

Saturating Multiplier Results on Overflow ............................. 2-38

ADSP-BF53x/BF56x Blackfin Processor Programming Reference vii

Contents

Multiplier Instruction Summary ............................................ 2-38

Multiplier Instruction Options .......................................... 2-40

Multiplier Data Flow Details ................................................. 2-42

Multiply Without Accumulate ............................................... 2-44

Special 32-Bit Integer MAC Instruction ................................. 2-46

Dual MAC Operations .......................................................... 2-47

Barrel Shifter (Shifter) ................................................................. 2-48

Shifter Operations ................................................................. 2-48

Two-Operand Shifts .......................................................... 2-49

Immediate Shifts ........................................................... 2-49

Register Shifts ............................................................... 2-50

Three-Operand Shifts ....................................................... 2-50

Immediate Shifts ........................................................... 2-50

Register Shifts ............................................................... 2-51

Bit Test, Set, Clear, Toggle ................................................ 2-52

Field Extract and Field Deposit ......................................... 2-52

Shifter Instruction Summary .................................................. 2-53

OPERATING MODES AND STATES

User Mode .................................................................................... 3-3

Protected Resources and Instructions ....................................... 3-4

Protected Memory ................................................................... 3-5

Entering User Mode ................................................................ 3-5

Example Code to Enter User Mode Upon Reset ................... 3-5

Return Instructions That Invoke User Mode ........................ 3-5

Contents

viii ADSP-BF53x/BF56x Blackfin Processor Programming Reference

Supervisor Mode .......................................................................... 3-7

Non-OS Environments ........................................................... 3-7

Example Code for Supervisor Mode Coming

Out of Reset .................................................................... 3-8

Emulation Mode .......................................................................... 3-9

Idle State ...................................................................................... 3-9

Example Code for Transition to Idle State .............................. 3-10

Reset State .................................................................................. 3-10

System Reset and Powerup .......................................................... 3-12

Hardware Reset ..................................................................... 3-13

SYSCR Register .................................................................... 3-14

Software Resets and Watchdog Timer .................................... 3-14

SWRST Register ................................................................... 3-15

Core-Only Software Reset ..................................................... 3-16

Core and System Reset .......................................................... 3-16

PROGRAM SEQUENCER

Introduction ................................................................................. 4-1

Sequencer Related Registers ..................................................... 4-5

Instruction Pipeline ...................................................................... 4-7

Branches .................................................................................... 4-10

Direct Short and Long Jumps ................................................ 4-11

Direct Call ............................................................................ 4-12

Indirect Branch and Call ....................................................... 4-12

PC-Relative Indirect Branch and Call .................................... 4-13

ADSP-BF53x/BF56x Blackfin Processor Programming Reference ix

Contents

Subroutines ........................................................................... 4-13

Stack Variables and Parameter Passing ................................ 4-15

Condition Code Flag ............................................................. 4-18

Conditional Branches ........................................................ 4-19

Conditional Register Move ................................................ 4-20

Branch Prediction .................................................................. 4-20

Hardware Loops .......................................................................... 4-21

Two-Dimensional Loops ........................................................ 4-24

Loop Unrolling ..................................................................... 4-26

Saving and Resuming Loops .................................................. 4-27

Example Code for Using Hardware Loops in an ISR .......... 4-28

Events and Interrupts .................................................................. 4-29

System Interrupt Processing ................................................... 4-31

System Peripheral Interrupts .................................................. 4-33

SIC_IWR Register ................................................................. 4-34

SIC_ISR Register .................................................................. 4-35

SIC_IMASK Register ............................................................ 4-36

System Interrupt Assignment Registers (SIC_IARx) ................ 4-37

Core Event Controller Registers ............................................. 4-38

IMASK Register ................................................................ 4-38

ILAT Register ................................................................... 4-39

IPEND Register ................................................................ 4-40

Event Vector Table ................................................................ 4-41

Contents

x ADSP-BF53x/BF56x Blackfin Processor Programming Reference

Return Registers and Instructions .......................................... 4-42

Executing RTX, RTN, or RTE in a Lower

Priority Event ................................................................ 4-45

Emulation Interrupt .............................................................. 4-45

Reset Interrupt ...................................................................... 4-46

NMI (Nonmaskable Interrupt) .............................................. 4-46

Exceptions ............................................................................ 4-47

Hardware Error Interrupt ...................................................... 4-47

Core Timer Interrupt ............................................................ 4-47

General-purpose Interrupts (IVG7-IVG15) ............................ 4-47

Interrupt Processing .................................................................... 4-48

Global Enabling/Disabling of Interrupts ................................ 4-48

Servicing Interrupts ............................................................... 4-48

Software Interrupts ............................................................... 4-50

Nesting of Interrupts ............................................................. 4-51

Non-nested Interrupts ...................................................... 4-51

Nested Interrupts ............................................................. 4-51

Example Prolog Code for Nested Interrupt

Service Routine .......................................................... 4-53

Example Epilog Code for Nested Interrupt

Service Routine .......................................................... 4-54

Logging of Nested Interrupt Requests ........................... 4-55

Self-Nesting of Core Interrupts ......................................... 4-55

ADSP-BF53x/BF56x Blackfin Processor Programming Reference xi

Contents

Additional Usability Issues ................................................ 4-56

Allocating the System Stack ........................................... 4-56

Latency in Servicing Events ................................................... 4-56

Hardware Errors and Exception Handling .................................... 4-58

SEQSTAT Register ................................................................ 4-59

Hardware Error Interrupt ...................................................... 4-59

Exceptions ............................................................................. 4-61

Exceptions While Executing an Exception Handler ............ 4-66

Exceptions and the Pipeline ............................................... 4-67

Deferring Exception Processing ......................................... 4-68

Example Code for an Exception Handler ........................... 4-68

Example Code for an Exception Routine ........................... 4-70

ADDRESS ARITHMETIC UNIT

Addressing With the AAU ............................................................. 5-5

Pointer Register File ................................................................ 5-6

Frame and Stack Pointers .................................................... 5-6

DAG Register Set .................................................................... 5-8

Indexed Addressing With Index & Pointer Registers ................. 5-8

Loads With Zero or Sign Extension ..................................... 5-9

Indexed Addressing With Immediate Offset ....................... 5-10

Auto-increment and Auto-decrement Addressing .................... 5-10

Pre-modify Stack Pointer Addressing ...................................... 5-11

Post-modify Addressing ......................................................... 5-11

Contents

xii ADSP-BF53x/BF56x Blackfin Processor Programming Reference

Addressing Circular Buffers ................................................... 5-12

Addressing With Bit-reversed Addresses ................................. 5-15

Modifying DAG and Pointer Registers ........................................ 5-15

Memory Address Alignment ........................................................ 5-16

AAU Instruction Summary ......................................................... 5-19

MEMORY

Memory Architecture .................................................................... 6-2

Overview of On-Chip Level 1 (L1) Memory ............................ 6-2

Overview of Scratchpad Data SRAM ....................................... 6-4

Overview of On-Chip Level 2 (L2) Memory ............................ 6-4

L1 Instruction Memory ................................................................ 6-5

IMEM_CONTROL Register .................................................. 6-5

L1 Instruction SRAM ............................................................. 6-7

L1 Instruction Cache ............................................................ 6-10

Cache Lines ...................................................................... 6-10

Cache Hits and Misses .................................................. 6-13

Cache Line Fills ............................................................ 6-14

Line Fill Buffer ............................................................. 6-15

Cache Line Replacement ............................................... 6-15

Instruction Cache Management ........................................ 6-16

Instruction Cache Locking by Line ................................ 6-16

Instruction Cache Locking by Way ................................ 6-17

Instruction Cache Invalidation ...................................... 6-18

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Contents

Instruction Test Registers ............................................................ 6-19

ITEST_COMMAND Register ............................................... 6-21

ITEST_DATA1 Register ........................................................ 6-22

ITEST_DATA0 Register ........................................................ 6-23

L1 Data Memory ........................................................................ 6-24

DMEM_CONTROL Register ............................................... 6-24

L1 Data SRAM ..................................................................... 6-27

L1 Data Cache ...................................................................... 6-29

Example of Mapping Cacheable Address Space .................. 6-30

Data Cache Access ............................................................ 6-33

Cache Write Method ......................................................... 6-35

IPRIO Register and Write Buffer Depth ............................ 6-35

Data Cache Control Instructions ....................................... 6-37

Data Cache Invalidation .................................................... 6-38

Data Test Registers ...................................................................... 6-38

DTEST_COMMAND Register ............................................. 6-39

DTEST_DATA1 Register ...................................................... 6-41

DTEST_DATA0 Register ...................................................... 6-42

On-chip Level 2 (L2) Memory .................................................... 6-43

On-chip L2 Bank Access ........................................................ 6-43

Latency ................................................................................. 6-44

Contents

xiv ADSP-BF53x/BF56x Blackfin Processor Programming Reference

Memory Protection and Properties .............................................. 6-45

Memory Management Unit ................................................... 6-45

Memory Pages ....................................................................... 6-48

Memory Page Attributes ................................................... 6-48

Page Descriptor Table ............................................................ 6-50

CPLB Management ............................................................... 6-50

MMU Application ................................................................ 6-52

Examples of Protected Memory Regions ................................ 6-54

ICPLB_DATAx Registers ...................................................... 6-55

DCPLB_DATAx Registers ..................................................... 6-57

DCPLB_ADDRx Registers .................................................... 6-59

ICPLB_ADDRx Registers ..................................................... 6-60

DCPLB_STATUS and ICPLB_STATUS Registers ................. 6-61

DCPLB_FAULT_ADDR and ICPLB_FAULT_ADDR

Registers ............................................................................ 6-63

Memory Transaction Model ........................................................ 6-65

Load/Store Operation ................................................................. 6-66

Interlocked Pipeline .............................................................. 6-66

Ordering of Loads and Stores ................................................ 6-67

Synchronizing Instructions .................................................... 6-68

Speculative Load Execution ................................................... 6-69

Conditional Load Behavior ................................................... 6-70

Working With Memory .............................................................. 6-71

Alignment ............................................................................. 6-71

Cache Coherency .................................................................. 6-71

ADSP-BF53x/BF56x Blackfin Processor Programming Reference xv

Contents

Atomic Operations ................................................................ 6-72

Memory-mapped Registers .................................................... 6-72

Core MMR Programming Code Example ............................... 6-73

Terminology ............................................................................... 6-74

PROGRAM FLOW CONTROL

Jump ............................................................................................ 7-2

IF CC JUMP ................................................................................ 7-5

Call .............................................................................................. 7-8

RTS, RTI, RTX, RTN, RTE (Return) ......................................... 7-10

LSETUP, LOOP ......................................................................... 7-13

LOAD / STORE

Load Immediate ............................................................................ 8-3

Load Pointer Register .................................................................... 8-7

Load Data Register ...................................................................... 8-10

Load Half-Word – Zero-Extended ............................................... 8-15

Load Half-Word – Sign-Extended ................................................ 8-19

Load High Data Register Half ..................................................... 8-23

Load Low Data Register Half ...................................................... 8-27

Load Byte – Zero-Extended ......................................................... 8-31

Load Byte – Sign-Extended ......................................................... 8-34

Store Pointer Register .................................................................. 8-37

Store Data Register ..................................................................... 8-40

Store High Data Register Half ..................................................... 8-45

Contents

xvi ADSP-BF53x/BF56x Blackfin Processor Programming Reference

Store Low Data Register Half ...................................................... 8-49

Store Byte ................................................................................... 8-54

MOVE

Move Register ............................................................................... 9-2

Move Conditional ........................................................................ 9-8

Move Half to Full Word – Zero-Extended ................................... 9-10

Move Half to Full Word – Sign-Extended .................................... 9-13

Move Register Half ..................................................................... 9-15

Move Byte – Zero-Extended ....................................................... 9-23

Move Byte – Sign-Extended ........................................................ 9-25

STACK CONTROL

--SP (Push) ................................................................................. 10-2

--SP (Push Multiple) ................................................................... 10-5

SP++ (Pop) ................................................................................. 10-8

SP++ (Pop Multiple) ................................................................. 10-12

LINK, UNLINK ...................................................................... 10-17

CONTROL CODE BIT MANAGEMENT

Compare Data Register ............................................................... 11-2

Compare Pointer ........................................................................ 11-6

Compare Accumulator ................................................................ 11-9

Move CC ................................................................................. 11-12

Negate CC ............................................................................... 11-15

ADSP-BF53x/BF56x Blackfin Processor Programming Reference xvii

Contents

LOGICAL OPERATIONS

& (AND) ................................................................................... 12-2

~ (NOT One’s-Complement) ...................................................... 12-4

| (OR) ........................................................................................ 12-6

^ (Exclusive-OR) ........................................................................ 12-8

BXORSHIFT, BXOR ................................................................ 12-10

BIT OPERATIONS

BITCLR ..................................................................................... 13-2

BITSET ...................................................................................... 13-4

BITTGL ..................................................................................... 13-6

BITTST ..................................................................................... 13-8

DEPOSIT ................................................................................ 13-10

EXTRACT ............................................................................... 13-16

BITMUX .................................................................................. 13-21

ONES (One’s-Population Count) .............................................. 13-26

SHIFT/ROTATE OPERATIONS

Add with Shift ............................................................................ 14-2

Shift with Add ............................................................................ 14-5

Arithmetic Shift .......................................................................... 14-7

Logical Shift ............................................................................. 14-14

ROT (Rotate) ........................................................................... 14-21

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xviii ADSP-BF53x/BF56x Blackfin Processor Programming Reference

ARITHMETIC OPERATIONS

ABS ........................................................................................... 15-3

Add ............................................................................................ 15-6

Add/Subtract – Prescale Down .................................................. 15-10

Add/Subtract – Prescale Up ....................................................... 15-13

Add Immediate ......................................................................... 15-16

DIVS, DIVQ (Divide Primitive) ............................................... 15-19

EXPADJ ................................................................................... 15-26

MAX ........................................................................................ 15-30

MIN ........................................................................................ 15-32

Modify – Decrement ................................................................ 15-34

Modify – Increment .................................................................. 15-37

Multiply 16-Bit Operands ......................................................... 15-43

Multiply 32-Bit Operands ......................................................... 15-51

Multiply and Multiply-Accumulate to Accumulator ................... 15-53

Multiply and Multiply-Accumulate to Half-Register .................. 15-58

Multiply and Multiply-Accumulate to Data Register .................. 15-67

Negate (Two’s-Complement) ..................................................... 15-73

RND (Round to Half-Word) .................................................... 15-77

Saturate .................................................................................... 15-80

SIGNBITS ............................................................................... 15-83

Subtract ................................................................................... 15-86

Subtract Immediate .................................................................. 15-90

ADSP-BF53x/BF56x Blackfin Processor Programming Reference xix

Contents

EXTERNAL EVENT MANAGEMENT

Idle ............................................................................................. 16-3

Core Synchronize ........................................................................ 16-5

System Synchronize ..................................................................... 16-8

EMUEXCPT (Force Emulation) ............................................... 16-11

Disable Interrupts ..................................................................... 16-13

Enable Interrupts ...................................................................... 16-15

RAISE (Force Interrupt / Reset) ................................................ 16-17

EXCPT (Force Exception) ......................................................... 16-20

Test and Set Byte (Atomic) ........................................................ 16-22

No Op ...................................................................................... 16-25

CACHE CONTROL

PREFETCH ............................................................................... 17-3

FLUSH ....................................................................................... 17-5

FLUSHINV ................................................................................ 17-7

IFLUSH ..................................................................................... 17-9

VIDEO PIXEL OPERATIONS

ALIGN8, ALIGN16, ALIGN24 .................................................. 18-3

DISALGNEXCPT ...................................................................... 18-6

BYTEOP3P (Dual 16-Bit Add / Clip) ......................................... 18-8

Dual 16-Bit Accumulator Extraction with Addition ................... 18-13

BYTEOP16P (Quad 8-Bit Add) ................................................ 18-15

BYTEOP1P (Quad 8-Bit Average – Byte) .................................. 18-19

Contents

xx ADSP-BF53x/BF56x Blackfin Processor Programming Reference

BYTEOP2P (Quad 8-Bit Average – Half-Word) ........................ 18-24

BYTEPACK (Quad 8-Bit Pack) ................................................ 18-30

BYTEOP16M (Quad 8-Bit Subtract) ........................................ 18-32

SAA (Quad 8-Bit Subtract-Absolute-Accumulate) ...................... 18-36

BYTEUNPACK (Quad 8-Bit Unpack) ...................................... 18-41

VECTOR OPERATIONS

Add on Sign ............................................................................... 19-3

VIT_MAX (Compare-Select) ...................................................... 19-8

Vector ABS ............................................................................... 19-15

Vector Add / Subtract ............................................................... 19-18

Vector Arithmetic Shift ............................................................. 19-23

Vector Logical Shift .................................................................. 19-28

Vector MAX ............................................................................. 19-32

Vector MIN .............................................................................. 19-35

Vector Multiply ........................................................................ 19-38

Vector Multiply and Multiply-Accumulate ................................ 19-41

Vector Negate (Two’s-Complement) .......................................... 19-46

Vector PACK ............................................................................ 19-48

Vector SEARCH ....................................................................... 19-50

ISSUING PARALLEL INSTRUCTIONS

Supported Parallel Combinations ................................................ 20-1

Parallel Issue Syntax .................................................................... 20-2

32-Bit ALU/MAC Instructions ................................................... 20-3

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