Analog Devices ADSP-BF59x Blackfin Hardware Reference Manual

a

ADSP-BF59x Blackfin

®

Processor

Hardware Reference

Revision 1.0, May 2011

Part Number

82-100102-01

Analog Devices, Inc.

One Technology Way

Norwood, Mass. 02062-9106

Copyright Information

ment may not be reproduced in any form without prior, express written

consent from Analog Devices, Inc.

Printed in the USA.

Disclaimer

Analog Devices, Inc. reserves the right to change this product without

prior notice. Information furnished by Analog Devices is believed to be

accurate and reliable. However, no responsibility is assumed by Analog

Devices for its use; nor for any infringement of patents or other rights of

third parties which may result from its use. No license is granted by impli-

cation or otherwise under the patent rights of Analog Devices, Inc.

Trademark and Service Mark Notice

The Analog Devices logo, Blackfin, EZ-KIT Lite, SHARC, TigerSHARC,

and VisualDSP++ are registered trademarks of Analog Devices, Inc.

All other brand and product names are trademarks or service marks of

their respective owners.

ADSP-BF59x Blackfin Processor Hardware Reference i

CONTENTS

PREFACE

Purpose of This Manual ............................................................. xxxi

Intended Audience ....................................................................... xxxi

Manual Contents ........................................................................ xxxii

What’s New in This Manual ....................................................... xxxiv

Technical or Customer Support .................................................. xxxiv

Registration for MyAnalog.com ............................................. xxxv

EngineerZone ........................................................................ xxxv

Social Networking Web Sites ................................................ xxxvi

Supported Processors .................................................................. xxxvi

Product Information ................................................................. xxxvii

Analog Devices Web Site ..................................................... xxxvii

VisualDSP++ Online Documentation ................................ xxxviii

Technical Library CD ......................................................... xxxviii

Notation Conventions ................................................................ xxxix

INTRODUCTION

General Description of Processor ................................................... 1-1

Portable Low-Power Architecture ............................................. 1-2

Contents

ii ADSP-BF59x Blackfin Processor Hardware Reference

Peripherals .................................................................................... 1-3

Memory Architecture .................................................................... 1-4

Internal Memory ..................................................................... 1-5

I/O Memory Space .................................................................. 1-5

DMA Support .............................................................................. 1-6

General-Purpose I/O (GPIO) ........................................................ 1-7

Two-Wire Interface ....................................................................... 1-8

Parallel Peripheral Interface ........................................................... 1-9

SPORT Controllers .................................................................... 1-11

Serial Peripheral Interface (SPI) Ports .......................................... 1-13

Timers ....................................................................................... 1-13

UART Port ................................................................................. 1-14

Watchdog Timer ......................................................................... 1-15

Clock Signals .............................................................................. 1-16

Dynamic Power Management ..................................................... 1-16

Full-On Mode (Maximum Performance) ................................ 1-17

Active Mode (Moderate Power Savings) ................................. 1-17

Sleep Mode (High Power Savings) ......................................... 1-17

Deep Sleep Mode (Maximum Power Savings) ........................ 1-18

Hibernate State .................................................................... 1-18

Instruction Set Description ......................................................... 1-18

Development Tools ..................................................................... 1-19

ADSP-BF59x Blackfin Processor Hardware Reference iii

Contents

MEMORY

Memory Architecture .................................................................... 2-1

L1 Instruction SRAM ................................................................... 2-2

L1 Instruction ROM ..................................................................... 2-3

L1 Data SRAM ............................................................................. 2-3

Boot ROM ................................................................................... 2-4

External Memory .......................................................................... 2-4

Processor-Specific MMRs .............................................................. 2-4

DTEST_COMMAND Register ............................................... 2-5

ITEST_COMMAND Register ................................................. 2-6

DMEM_CONTROL Register ................................................. 2-7

IMEM_CONTROL Register ................................................... 2-7

DCPLB_DATAx Registers ....................................................... 2-8

ICPLB_DATAx Registers ......................................................... 2-9

CHIP BUS HIERARCHY

Chip Bus Hierarchy Overview ....................................................... 3-1

Interface Overview ........................................................................ 3-2

Internal Clocks ........................................................................ 3-3

Core Bus Overview .................................................................. 3-3

Peripheral Access Bus (PAB) ..................................................... 3-4

PAB Arbitration .................................................................. 3-5

PAB Agents (Masters, Slaves) ............................................... 3-5

PAB Performance ................................................................ 3-6

Contents

iv ADSP-BF59x Blackfin Processor Hardware Reference

DMA Access Bus (DAB), DMA Core Bus (DCB) .................... 3-6

DAB and DCB Arbitration ................................................. 3-6

DAB Bus Agents (Masters) .................................................. 3-7

DAB and DCB Performance ............................................... 3-8

SYSTEM INTERRUPTS

Specific Information for the ADSP-BF59x .................................... 4-1

Overview ...................................................................................... 4-1

Features .................................................................................. 4-2

Description of Operation .............................................................. 4-2

Events and Sequencing ............................................................ 4-2

System Peripheral Interrupts .................................................... 4-4

Programming Model ..................................................................... 4-7

System Interrupt Initialization ................................................. 4-7

System Interrupt Processing Summary ..................................... 4-8

System Interrupt Controller Registers .......................................... 4-10

System Interrupt Assignment (SIC_IAR) Register .................. 4-10

System Interrupt Mask (SIC_IMASK) Register ...................... 4-12

System Interrupt Status (SIC_ISR) Register ........................... 4-12

System Interrupt Wakeup-Enable (SIC_IWR) Register ........... 4-12

Programming Examples .............................................................. 4-13

Clearing Interrupt Requests ................................................... 4-13

Unique Information for the ADSP-BF59x Processor .................... 4-15

Interfaces .............................................................................. 4-15

System Peripheral Interrupts .................................................. 4-17

ADSP-BF59x Blackfin Processor Hardware Reference v

Contents

DIRECT MEMORY ACCESS

Specific Information for the ADSP-BF59x ..................................... 5-1

Overview and Features .................................................................. 5-2

DMA Controller Overview ............................................................ 5-4

External Interfaces ................................................................... 5-4

Internal Interfaces ................................................................... 5-4

Peripheral DMA ...................................................................... 5-5

Memory DMA ........................................................................ 5-6

Handshaked Memory DMA (HMDMA) Mode ................... 5-8

Modes of Operation ...................................................................... 5-9

Register-Based DMA Operation ............................................... 5-9

Stop Mode ........................................................................ 5-11

Autobuffer Mode .............................................................. 5-11

Two-Dimensional DMA Operation ........................................ 5-11

Examples of Two-Dimensional DMA ................................ 5-12

Descriptor-based DMA Operation ......................................... 5-13

Descriptor List Mode ........................................................ 5-14

Descriptor Array Mode ..................................................... 5-15

Variable Descriptor Size .................................................... 5-15

Mixing Flow Modes .......................................................... 5-16

Functional Description ............................................................... 5-17

DMA Operation Flow ........................................................... 5-17

DMA Startup .................................................................... 5-17

DMA Refresh ................................................................... 5-22

Contents

vi ADSP-BF59x Blackfin Processor Hardware Reference

Work Unit Transitions ...................................................... 5-24

DMA Transmit and MDMA Source .............................. 5-25

DMA Receive ............................................................... 5-26

Stopping DMA Transfers .................................................. 5-28

DMA Errors (Aborts) ............................................................ 5-28

DMA Control Commands .................................................... 5-31

Restrictions ...................................................................... 5-34

Transmit Restart or Finish ............................................. 5-34

Receive Restart or Finish ............................................... 5-35

Handshaked Memory DMA Operation .................................. 5-36

Pipelining DMA Requests ................................................. 5-37

HMDMA Interrupts ......................................................... 5-39

DMA Performance ................................................................ 5-40

DMA Throughput ............................................................ 5-41

Memory DMA Timing Details .......................................... 5-44

Static Channel Prioritization ............................................ 5-44

Temporary DMA Urgency ................................................ 5-44

Memory DMA Priority and Scheduling ............................. 5-46

Traffic Control ................................................................. 5-48

Programming Model .................................................................. 5-50

Synchronization of Software and DMA .................................. 5-50

Single-Buffer DMA Transfers ............................................ 5-52

Continuous Transfers Using Autobuffering ........................ 5-53

Descriptor Structures ........................................................ 5-55

ADSP-BF59x Blackfin Processor Hardware Reference vii

Contents

Descriptor Queue Management ......................................... 5-56

Descriptor Queue Using Interrupts on Every Descriptor 5-57

Descriptor Queue Using Minimal Interrupts .................. 5-58

Software Triggered Descriptor Fetches ............................... 5-60

DMA Registers ........................................................................... 5-62

DMA Channel Registers ........................................................ 5-62

DMA Peripheral Map Registers DMAx_PERIPHERAL_MAP/

MDMA_yy_PERIPHERAL_MAP) ................................ 5-66

DMA Configuration Registers

(DMAx_CONFIG/MDMA_yy_CONFIG) ................... 5-67

DMA Interrupt Status Registers

(DMAx_IRQ_STATUS/MDMA_yy_IRQ_STATUS) ...... 5-71

DMA Start Address Registers

(DMAx_START_ADDR/MDMA_yy_START_ADDR) .. 5-74

DMA Current Address Registers

(DMAx_CURR_ADDR/MDMA_yy_CURR_ADDR) .... 5-74

DMA Inner Loop Count Registers

(DMAx_X_COUNT/MDMA_yy_X_COUNT) ............. 5-75

DMA Current Inner Loop Count Registers

(DMAx_CURR_X_COUNT

/MDMA_yy_CURR_X_COUNT) ................................. 5-76

DMA Inner Loop Address Increment Registers

(DMAx_X_MODIFY/MDMA_yy_X_MODIFY) ........... 5-77

DMA Outer Loop Count Registers

(DMAx_Y_COUNT/MDMA_yy_Y_COUNT) .............. 5-78

DMA Current Outer Loop Count Registers

(DMAx_CURR_Y_COUNT/

MDMA_yy_CURR_Y_COUNT) .................................. 5-78

Contents

viii ADSP-BF59x Blackfin Processor Hardware Reference

DMA Outer Loop Address Increment Registers

(DMAx_Y_MODIFY/MDMA_yy_Y_MODIFY) ........... 5-79

DMA Next Descriptor Pointer Registers

(DMAx_NEXT_DESC_PTR/

MDMA_yy_NEXT_DESC_PTR) .................................. 5-80

DMA Current Descriptor Pointer Registers

(DMAx_CURR_DESC_PTR/

MDMA_yy_CURR_DESC_PTR) ................................. 5-81

HMDMA Registers ............................................................... 5-82

Handshake MDMA Control Registers

(HMDMAx_CONTROL) ............................................. 5-82

Handshake MDMA Initial Block Count Registers

(HMDMAx_BCINIT) ................................................... 5-84

Handshake MDMA Current Block Count Registers

(HMDMAx_BCOUNT) ............................................... 5-84

Handshake MDMA Current Edge Count Registers

(HMDMAx_ECOUNT) ............................................... 5-85

Handshake MDMA Initial Edge Count Registers

(HMDMAx_ECINIT) ................................................... 5-86

Handshake MDMA Edge Count Urgent Registers

(HMDMAx_ECURGENT) ........................................... 5-87

Handshake MDMA Edge Count Overflow Interrupt

Registers (HMDMAx_ECOVERFLOW) ........................ 5-87

DMA Traffic Control Registers

(DMA_TC_PER and DMA_TC_CNT) ............................. 5-88

DMA_TC_PER Register .................................................. 5-88

DMA_TC_CNT Register ................................................. 5-88

Programming Examples .............................................................. 5-90

ADSP-BF59x Blackfin Processor Hardware Reference ix

Contents

Register-Based 2-D Memory DMA ........................................ 5-90

Initializing Descriptors in Memory ........................................ 5-93

Software-Triggered Descriptor Fetch Example ........................ 5-96

Handshaked Memory DMA Example ..................................... 5-99

Unique Information for the ADSP-BF59x Processor .................. 5-101

Static Channel Prioritization ............................................... 5-101

DYNAMIC POWER MANAGEMENT

Phase Locked Loop and Clock Control .......................................... 6-1

PLL Overview ......................................................................... 6-2

PLL Clock Multiplier Ratios .................................................... 6-3

Core Clock/System Clock Ratio Control ............................. 6-5

Dynamic Power Management Controller ....................................... 6-7

Operating Modes ..................................................................... 6-7

Dynamic Power Management Controller States ........................ 6-8

Full-On Mode ................................................................... 6-8

Active Mode ...................................................................... 6-8

Sleep Mode ........................................................................ 6-9

Deep Sleep Mode ............................................................... 6-9

Hibernate State ................................................................ 6-10

Operating Mode Transitions .................................................. 6-10

Programming Operating Mode Transitions ............................. 6-13

Dynamic Supply Voltage Control ........................................... 6-15

Power Supply Management .................................................... 6-15

Changing Voltage .............................................................. 6-15

Contents

x ADSP-BF59x Blackfin Processor Hardware Reference

Powering Down the Core (Hibernate State) ....................... 6-17

PLL and VR Registers ................................................................. 6-18

PLL_DIV Register ................................................................ 6-19

PLL_CTL Register ................................................................ 6-20

PLL_STAT Register .............................................................. 6-20

PLL_LOCKCNT Register ..................................................... 6-21

VR_CTL Register ................................................................. 6-21

System Control ROM Function .................................................. 6-22

Programming Model ............................................................. 6-24

Accessing the System Control ROM Function in C/C++ ........ 6-24

Accessing the System Control ROM Function in Assembly .... 6-25

Programming Examples .............................................................. 6-28

Full-on Mode to Active Mode and Back ................................. 6-30

Transition to Sleep Mode or Deep Sleep Mode ....................... 6-32

Set Wakeup Events and Enter Hibernate State ........................ 6-33

Perform a System Reset or Soft-Reset ..................................... 6-35

In Full-on Mode, Change VCO Frequency, Core Clock

Frequency, and System Clock Frequency ............................. 6-36

Changing Voltage Levels ....................................................... 6-38

GENERAL-PURPOSE PORTS

Overview ...................................................................................... 7-1

Features ........................................................................................ 7-1

Interface Overview ....................................................................... 7-2

External Interface .................................................................... 7-3

ADSP-BF59x Blackfin Processor Hardware Reference xi

Contents

Port F Structure .................................................................. 7-3

Port G Structure ................................................................. 7-4

Additional Considerations ................................................... 7-5

Internal Interfaces ................................................................... 7-6

Performance/Throughput ........................................................ 7-6

Description of Operation .............................................................. 7-7

Operation ............................................................................... 7-7

General-Purpose I/O Modules ................................................. 7-8

GPIO Interrupt Processing .................................................... 7-11

Programming Model ................................................................... 7-17

GPIO Schmitt Trigger Control .................................................... 7-19

PORTx Pad Control Registers ................................................ 7-19

Memory-Mapped GPIO Registers ............................................... 7-20

Port Multiplexer Control Register (PORTx_MUX) ................ 7-21

Function Enable Registers (PORTx_FER) .............................. 7-22

GPIO Direction Registers (PORTxIO_DIR) .......................... 7-22

GPIO Input Enable Registers (PORTxIO_INEN) .................. 7-23

GPIO Data Registers (PORTxIO) .......................................... 7-23

GPIO Set Registers (PORTxIO_SET) .................................... 7-24

GPIO Clear Registers (PORTxIO_CLEAR) ........................... 7-24

GPIO Toggle Registers (PORTxIO_TOGGLE) ...................... 7-25

GPIO Polarity Registers (PORTxIO_POLAR) ....................... 7-25

Interrupt Sensitivity Registers (PORTxIO_EDGE) ................. 7-26

GPIO Set on Both Edges Registers (PORTxIO_BOTH) ......... 7-26

Contents

xii ADSP-BF59x Blackfin Processor Hardware Reference

GPIO Mask Interrupt Registers (PORTxIO_MASKA/B) ....... 7-27

GPIO Mask Interrupt Set Registers

(PORTxIO_MASKA/B_SET) ............................................ 7-28

GPIO Mask Interrupt Clear Registers

(PORTxIO_MASKA/B_CLEAR) ....................................... 7-30

GPIO Mask Interrupt Toggle Registers

(PORTxIO_MASKA/B_TOGGLE) .................................... 7-32

Programming Examples .............................................................. 7-33

GENERAL-PURPOSE TIMERS

Specific Information for the ADSP-BF59x .................................... 8-1

Overview ...................................................................................... 8-2

External Interface .................................................................... 8-3

Internal Interface .................................................................... 8-4

Description of Operation .............................................................. 8-4

Interrupt Processing ................................................................ 8-5

Illegal States ............................................................................ 8-7

Modes of Operation ................................................................... 8-10

Pulse Width Modulation (PWM_OUT) Mode ...................... 8-10

Output Pad Disable .......................................................... 8-12

Single Pulse Generation .................................................... 8-12

Pulse Width Modulation Waveform Generation ................ 8-13

PULSE_HI Toggle Mode .................................................. 8-15

Externally Clocked PWM_OUT ....................................... 8-20

Using PWM_OUT Mode With the PPI ............................ 8-21

Stopping the Timer in PWM_OUT Mode ........................ 8-21

ADSP-BF59x Blackfin Processor Hardware Reference xiii

Contents

Pulse Width Count and Capture (WDTH_CAP) Mode ......... 8-23

Autobaud Mode ................................................................ 8-31

External Event (EXT_CLK) Mode ......................................... 8-32

Programming Model ................................................................... 8-33

Timer Registers ........................................................................... 8-34

Timer Enable Register (TIMER_ENABLE) ............................ 8-35

Timer Disable Register (TIMER_DISABLE) .......................... 8-36

Timer Status Register (TIMER_STATUS) .............................. 8-38

Timer Configuration Register (TIMER_CONFIG) ................ 8-40

Timer Counter Register (TIMER_COUNTER) ..................... 8-41

Timer Period (TIMER_PERIOD) and Timer

Width (TIMER_WIDTH) Registers ................................... 8-42

Summary .............................................................................. 8-45

Programming Examples ............................................................... 8-47

Unique Information for the ADSP-BF59x Processor .................... 8-56

Interface Overview ................................................................ 8-57

External Interface .............................................................. 8-58

CORE TIMER

Specific Information for the ADSP-BF59x ..................................... 9-1

Overview and Features .................................................................. 9-1

Timer Overview ............................................................................ 9-2

External Interfaces ................................................................... 9-2

Internal Interfaces ................................................................... 9-3

Description of Operation .............................................................. 9-3

Contents

xiv ADSP-BF59x Blackfin Processor Hardware Reference

Interrupt Processing ................................................................ 9-3

Core Timer Registers .................................................................... 9-4

Core Timer Control Register (TCNTL) ................................... 9-5

Core Timer Count Register (TCOUNT) ................................. 9-5

Core Timer Period Register (TPERIOD) ................................. 9-6

Core Timer Scale Register (TSCALE) ...................................... 9-7

Programming Examples ................................................................ 9-7

Unique Information for the ADSP-BF59x Processor ...................... 9-9

WATCHDOG TIMER

Specific Information for the ADSP-BF59x .................................. 10-1

Overview and Features ................................................................ 10-1

Interface Overview ..................................................................... 10-3

External Interface .................................................................. 10-3

Internal Interface .................................................................. 10-3

Description of Operation ............................................................ 10-4

Register Definitions .................................................................... 10-5

Watchdog Count (WDOG_CNT) Register ........................... 10-5

Watchdog Status (WDOG_STAT) Register ........................... 10-6

Watchdog Control (WDOG_CTL) Register .......................... 10-7

Programming Examples .............................................................. 10-8

Unique Information for the ADSP-BF59x Processor .................. 10-10

UART PORT CONTROLLERS

Specific Information for the ADSP-BF59x .................................. 11-1

ADSP-BF59x Blackfin Processor Hardware Reference xv

Contents

Overview .................................................................................... 11-2

Features ...................................................................................... 11-2

Interface Overview ...................................................................... 11-3

External Interface .................................................................. 11-3

Internal Interface ................................................................... 11-4

Description of Operation ............................................................ 11-5

UART Transfer Protocol ........................................................ 11-5

UART Transmit Operation .................................................... 11-6

UART Receive Operation ...................................................... 11-7

IrDA Transmit Operation ...................................................... 11-8

IrDA Receive Operation ........................................................ 11-9

Interrupt Processing ............................................................ 11-11

Bit Rate Generation ............................................................. 11-12

Autobaud Detection ............................................................ 11-13

Programming Model ................................................................. 11-15

Non-DMA Mode ................................................................ 11-15

DMA Mode ........................................................................ 11-17

Mixing Modes ..................................................................... 11-18

UART Registers ........................................................................ 11-19

UART Line Control (UART_LCR) Register ......................... 11-21

UART Modem Control (UART_MCR) Register .................. 11-23

UART Line Status (UART_LSR) Register ............................ 11-24

UART Transmit Holding (UART_THR) Register ................ 11-25

UART Receive Buffer (UART_RBR) Register ...................... 11-26

Contents

xvi ADSP-BF59x Blackfin Processor Hardware Reference

UART Interrupt Enable (UART_IER) Register .................... 11-26

UART Interrupt Identification (UART_IIR) Register ........... 11-28

UART Divisor Latch

(UART_DLL and UART_DLH) Registers ........................ 11-29

UART Scratch (UART_SCR) Register ................................. 11-30

UART Global Control (UART_GCTL) Register .................. 11-31

Programming Examples ............................................................ 11-32

Unique Information for the ADSP-BF59x Processor .................. 11-41

TWO WIRE INTERFACE CONTROLLER

Specific Information for the ADSP-BF59x .................................. 12-1

Overview .................................................................................... 12-2

Interface Overview ..................................................................... 12-3

External Interface .................................................................. 12-4

Serial Clock Signal (SCL) ................................................. 12-4

Serial Data Signal (SDA) .................................................. 12-4

TWI Pins ......................................................................... 12-5

Internal Interfaces ................................................................. 12-5

Description of Operation ............................................................ 12-6

TWI Transfer Protocols ......................................................... 12-6

Clock Generation and Synchronization ............................. 12-7

Bus Arbitration ................................................................. 12-8

Start and Stop Conditions ................................................. 12-8

General Call Support ........................................................ 12-9

Fast Mode ...................................................................... 12-10

ADSP-BF59x Blackfin Processor Hardware Reference xvii

Contents

Functional Description ............................................................. 12-10

General Setup ...................................................................... 12-10

Slave Mode .......................................................................... 12-11

Master Mode Clock Setup ................................................... 12-12

Master Mode Transmit ........................................................ 12-12

Master Mode Receive ........................................................... 12-14

Repeated Start Condition ................................................ 12-15

Transmit/Receive Repeated Start Sequence ................... 12-15

Receive/Transmit Repeated Start Sequence ................... 12-16

Clock Stretching ............................................................. 12-17

Clock Stretching During FIFO Underflow ....................... 12-17

Clock Stretching During FIFO Overflow ......................... 12-19

Clock Stretching During Repeated Start Condition .......... 12-20

Programming Model ................................................................. 12-22

Register Descriptions ................................................................ 12-24

TWI CONTROL Register (TWI_CONTROL) ................... 12-24

SCL Clock Divider Register (TWI_CLKDIV) ...................... 12-25

TWI Slave Mode Control Register (TWI_SLAVE_CTL) ...... 12-26

TWI Slave Mode Address Register (TWI_SLAVE_ADDR) ... 12-28

TWI Slave Mode Status Register (TWI_SLAVE_STAT) ....... 12-28

TWI Master Mode Control Register

(TWI_MASTER_CTL) .................................................... 12-29

TWI Master Mode Address Register

(TWI_MASTER_ADDR) ................................................ 12-32

Contents

xviii ADSP-BF59x Blackfin Processor Hardware Reference

TWI Master Mode Status Register

(TWI_MASTER_STAT) .................................................. 12-33

TWI FIFO Control Register (TWI_FIFO_CTL) ................. 12-36

TWI FIFO Status Register (TWI_FIFO_STAT) .................. 12-38

TWI FIFO Status ........................................................... 12-38

TWI Interrupt Mask Register (TWI_INT_MASK) .............. 12-39

TWI Interrupt Status Register (TWI_INT_STAT) .............. 12-40

TWI FIFO Transmit Data Single Byte

Register (TWI_XMT_DATA8) ......................................... 12-43

TWI FIFO Transmit Data Double Byte

Register (TWI_XMT_DATA16) ....................................... 12-43

TWI FIFO Receive Data Single Byte

Register (TWI_RCV_DATA8) ......................................... 12-44

TWI FIFO Receive Data Double Byte

Register (TWI_RCV_DATA16) ........................................ 12-45

Programming Examples ............................................................ 12-46

Master Mode Setup ............................................................. 12-46

Slave Mode Setup ................................................................ 12-50

Electrical Specifications ............................................................ 12-56

Unique Information for the ADSP-BF59x Processor .................. 12-56

SPI-COMPATIBLE PORT CONTROLLER

Specific Information for the ADSP-BF59x .................................. 13-1

Overview .................................................................................... 13-2

Features ...................................................................................... 13-2

Interface Overview ..................................................................... 13-3

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Analog Devices ADSP-BF59x Blackfin Hardware Reference Manual

Analog Devices ADSP-BF59x Blackfin Hardware Reference Manual

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