Hitachi SH7750R User manual

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User manual

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Hitachi SuperHï›› RISC engine
SH7750 Series
SH7750, SH7750S, SH7750R
Hardware Manual
ADE-602-124E
Rev. 6.0
7/10/2002
Hitachi, Ltd.
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s
patent, copyright, trademark, or other intellectual property rights for information contained in
this document. Hitachi bears no responsibility for problems that may arise with third party’s
rights, including intellectual property rights, in connection with use of the information
contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you
have received the latest product standards or specifications before final design, purchase or
use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability.
However, contact Hitachi’s sales office before using the product in an application that
demands especially high quality and reliability or where its failure or malfunction may directly
threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear
power, combustion control, transportation, traffic, safety equipment or medical equipment for
life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi
particularly for maximum rating, operating supply voltage range, heat radiation characteristics,
installation conditions and other characteristics. Hitachi bears no responsibility for failure or
damage when used beyond the guaranteed ranges. Even within the guaranteed ranges,
consider normally foreseeable failure rates or failure modes in semiconductor devices and
employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi
product does not cause bodily injury, fire or other consequential damage due to operation of
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6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document
without written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi
semiconductor products.
Rev. 6.0, 07/02, page iii of I
Preface
The SH-4 (SH7750 Series: SH7750, SH7750S, SH7750R) microprocessor incorporates the 32-bit
SH-4 CPU and is also equipped with peripheral functions necessary for configuring a user system.
The SH7750 Series is built in with a variety of peripheral functions such as cache memory,
memory management unit (MMU), interrupt controller, timers, two serial communication
interfaces (SCI, SCIF), real-time clock (RTC), user break controller (UBC), bus state controller
(BSC) and smart card interface. This series can be used in a wide range of multimedia equipment.
The bus controller is compatible with ROM, SRAM, DRAM, synchronous DRAM and PCMCIA,
as well as 64-bit synchronous DRAM 4-bank system and 64-bit data bus.
Target Readers:
This manual is designed for use by people who design application systems using
the SH7750, SH7750S, or SH7750R.
To use this manual, basic knowledge of electric circuits, logic circuits and microcomputers is
required.
Purpose:
This manual provides the information of the hardware functions and electrical
characteristics of the SH7750, SH7750S, and SH7750R.
The SH-4 Programming Manual contains detailed information of executable instructions. Please
read the Programming Manual together with this manual.
How to Use the Book:
• To understand general functions
→ Read the manual from the beginning.
The manual explains the CPU, system control functions, peripheral functions and electrical
characteristics in that order.
• To understanding CPU functions
→ Refer to the separate SH-4 Programming Manual.
Explanatory Note:
Bit sequence: upper bit at left, and lower bit at right
List of Related Documents:
The latest documents are available on our Web site. Please make
sure that you have the latest version.
(http://www.hitachisemiconductor.com/)
• User manuals for SH7750, SH7750S, and SH7750R
Name of Document Document No.
SH7750 Series Hardware Manual This manual
SH-4 Programming Manual ADE-602-156
Rev. 6.0, 07/02, page iv of I
• User manuals for development tools
Name of Document Document No.
C/C++ Compiler, Assembler, Optimizing Linkage Editor User’s Manual ADE-702-246
Simulator/Debugger User’s Manual ADE-702-186
Hitachi Embedded Workshop User’s Manual ADE-702-201
Rev. 6.0, 07/02, page v of I
List of Items Revised or Added for This Version
Section Page Item Description
1.1 SH7750 Series (SH7750,
SH7750S, SH7750R)
Features
1 Description amended
and added
4 to 8 Table 1.1 SH7750 Series
Features
Description added for
LSI, and description
and Note added for
Clock pulse generator
(CPG)
SH7750 and SH7750S
added to cache memory
Cache memory
[SH7750R] added to
table
Description added for
Direct memory access
controller (DMAC) and
Timer unit (TMU)
SH7750R table added
to Product lineup
Notes 1, 2, 3 added
1.2 Block Diagram 9 Figure 1.1 Block Diagram of
SH7750 Series Functions
I cache 8 KB and 0
cache 16 KB deleted
from table
1.3 Pin Arrangement 10 to 12 Figure 1.2 to 1.4 SH7750R added, and
description amended
1.4 Pin Functions 13 to 40 Table 1.2 to 1.4 Table and note
amended
2.7 Processor Modes 55 Description deleted
3.2 Register Descriptions 61 Figure 3.2 MMU-Related
Registers
Amended
62 3. Page table entry
assistance register (PTEA)
SH7750R added after
SH7750S
62 1. Page table entry high
register (PTEH),
6. MMU control register
(MMUCR)
Description added
3.3.1 Physical Address
Space
64 to 67 Description added
Rev. 6.0, 07/02, page vi of I
Section Page Item Description
3.3.3 Virtual Address Space 68, 69 Description changed
3.3.4 On-Chip RAM Space 69 Description changed
3.3.7 Address Space
Identifier (ASID)
70 Note added
4.1.1 Features Completely revised
95 Table 4.1 Cache Features
(SH7750, SH7750S)
Completely revised
95 Table 4.2 Cache Features
(SH7750R)
Newly added
96 Table 4.3 Features of Store
Queues
Description added
4.2 Register Descriptions 97 Figure 4.1 Cache and Store
Queue Control Registers
Figure changed and
Note added
97 (1) Cache Control Register
(CCR)
Description added and
amended
4.3.1 Configuration Description added
101 Figure 4.3 Configuration of
Operand Cache (SH7750R)
Newly added
4.3.6 RAM Mode 106 to
107
Description amended
and added
4.3.7 OC Index Mode 107 Description added
4.4.1 Configuration 109 Figure 4.5 amended to
figure 4.6, description
added and amended
110 Figure 4.7 Configuration of
Instruction Cache (SH7750R)
Newly added
4.6 Memory-Mapped Cache
Configuration (SH7750R)
116 Newly added
4.7 Store Queues 122 Description amended
and added
4.7.3 Transfer to External
Memory
122, 123 Description added
4.7.4 SQ Protection 124 Description added
4.7.5 Reading the SQs
(SH7750R Only)
124 Newly added
4.7.6 SQ Usage Notes 125 Newly added
5.2 Register Descriptions 128 Description amended
5.4 Exception Types and
Priorities
130 to
132
Table 5.2 Exceptions Description and note
added
Rev. 6.0, 07/02, page vii of I
Section Page Item Description
5.6.3 Interrupts 157 (3) Peripheral Module
Interrupts
Description changed
7.3 Instruction Set 186 Table 7.7 Branch Instructions Description added
8.3 Execution Cycles and
Pipeline Stalling
204 to
206
Description amended
Note changed9.1.1 Types of Power-Down
Modes
222 Table 9.1 Status of CPU and
Peripheral Modules in Power-
Down Modes
Hardware standby
(SH7750S, SH7750R)
added to table,
description amended
9.1.2 Register Configuration 223 Table 9.2 Power-Down Mode
Registers
Description and Note
added to table
9.1.3 Pin Configuration 223 Table 9.3 Power-Down Mode
Pins
Description added to
Function in table and
amended
9.2.2 Peripheral Module Pin
High Impedance Control
226 Other information Description amended
9.2.3 Peripheral Module Pin
Pull-Up Control
226 Other Information Added
9.2.4 Standby Control
Register 2 (STBCR2)
227 Bit table Bit 6 amended to STHZ
and bit 1 to MSTP6,
note added
227 Bit 6, Bits 1 and 0 Description added
9.2.5 Clock-Stop Register 00
(CLKSTP00) (SH7750R Only)
228, 229 Newly added
9.2.6 Clock-Stop Clear
Register 00 (CLKSTPCLR00)
(SH7750R Only)
229 Added
9.4.1 Transition to Deep
Sleep Mode
230 Description amended,
Note added
9.5.2 Exit from Standby
Mode
232 Exit by Interrupt Note added
9.6.1 Transition to Module
Standby Function
234 Text amended
Table description and
note added
9.6.2 Exit from Module
Standby Function
234 Description amended
Note deleted
9.7 Hardware Standby Mode
(SH7750S, SH7750R Only)
235 SH7750R added
Rev. 6.0, 07/02, page viii of I
Section Page Item Description
9.8.5 Hardware Standby
Mode Timing (SH7750S,
SH7750R Only)
244 to
246
Figures 9.12, 9.13, 9.15 Figures changed
Notes added
10.2.1 Block Diagram of
CPG
249 Figure 10.1 (1) Block
Diagram of CPG (SH7750,
SH7750S)
Amended
250 Figure 10.1 (2) Block
Diagram of CPG (SH7750R)
Newly added
10.2.2 CPG Pin
Configuration
252 Table 10.1 CPG Pins Table and Note
amended
10.2.3 CPG Register
Configuration
252 Table 10.2 CPG Register Description added
10.3 Clock Operating Modes Description added and
amended
253 Table 10.3 (1) Clock
Operating Modes (SH7750,
SH7750S)
Table amended and
Note amended and
added
253 Table 10.3 (2) Clock
Operating Modes (SH7750R)
Newly added
254 Table 10.4 FRQCR Settings
and Internal Clock
Frequencies
Table and Note
amended
10.8.2 Watchdog Timer
Control/Status Register
(WTCSR)
261 Description amended
10.10 Notes on Board
Design
265 When Using a PLL Oscillator
Circuit
Description amended
266 Figure 10.5 Points for
Attention when Using PLL
Oscillator Circuit
Amended
11.1.1 Features 267 Description added for
Alarm interrupts
11.1.2 Block Diagram 268 Figure 11.1 Block Diagram
of RTC
Figure amended and
Note added
11.1.3 Pin Configuration 269 Table 11.1 RTC Pins Table amended
11.1.4 Register Configuration 270 Table 11.2 RTC Registers RTC control register 3
and Year alarm register
added to table, and
Note added
Rev. 6.0, 07/02, page ix of I
Section Page Item Description
11.2.2 Second Counter
(RSECCNT)
271 Description amended
11.2.17 RTC Control
Register 3 (RCR3) and Year-
Alarm Register (RYRAR)
(SH7750R Only)
283 Newly added
11.3.3 Alarm Function 288 Description added
11.5.2 Carry Flag and
Interrupt Flag in Standby
Mode
289 Added
11.5.3 Crystal Oscillator
Circuit
290 Figure 11.5 Example of
Crystal Oscillator Circuit
Connection
Note amended
12.1.1 Features 291 Description amended
and added
12.1.2 Block Diagram 292 Figure 12.1 Block Diagram of TMU,
amended
12.1.4 Register Configuration 293,
294
Table 12.2 TMU Registers Description and Note
added
12.2.3 Timer Start Register
2 (TSTR2)
297 Added
12.2.4 Timer Constant
Registers (TCOR)
298 Description amended
and added
12.2.5 Timer Counters
(TCNT)
298,
299
Description amended
and added
12.2.6 Timer Control
Registers (TCR)
299 Description amended
and added
12.3.1 Counter Operation 304 Description added
12.4 Interrupts 308 Description amended
and added
309 Table 12.3 TMU Interrupt
Sources
Channels 3 and 4
added to table
Note added
13.1.1 Features 312 Burst ROM interface Description amended
and added, and Note
added
13.1.2 Block Diagram 313 Figure 13.1 Block Diagram
of BSC
Figure amended and
add Note added
Rev. 6.0, 07/02, page x of I
Section Page Item Description
13.1.4 Register Configuration 318 Table 13.2 BSC Registers Bus control register 3
and 4 added to table,
and Note added
13.1.5 Overview of Areas 320 Table 13.3 External Memory
Space Map
64
*
7
added to Area 0, 5,
6 Settable Bus Widths,
and Note 7 added
319 Space Divisions Description amended
320 Table 13.3 External Memory
Space Map
Table amended, and
Notes amended and
added
321, 322 Memory Bus Width Description added
13.2.1 Bus Control Register
1 (BCR1)
326 Bit table Bit 18 amended and
note added
327 Bit 31, Bit 30, Bit 29 Description added
328 Bit 26
330 Bit 16
Description and notes
added
330 Bit 15, Bit 14 Description amended
331 Bits 13 to 11
332 Bits 10 to 8
333 Bits 7 to 5
Table amended and
note added
334 Bit 0 Description amended
13.2.2 Bus Control Register
2 (BCR2)
335 Bits 15, 14 Description added
337 Newly added13.2.3 Bus Control Register
3 (BCR3) (SH7750R Only)
338 Bits 12 to 1—Reserved Description added
13.2.4 Bus Control Register
4 (BCR4)
338,
339
Newly added
13.2.5 Wait Control Register
1 (WCR1)
342 Note amended
13.2.6 Wait Control Register
2 (WCR2)
344 to
349
Bits 31 to 29, Bits 25 to 23,
Bits 19 to 17, Bits 15 to 13,
Bits 11 to 9, Bits 8 to 6,
Bits 5 to 3, and Bits 2 to 0
Description added and
amended
13.2.7 Wait Control Register
3 (WCR3)
351 Bit table Bits 19 and 7 changed,
and Note added
351 Description added
Rev. 6.0, 07/02, page xi of I
Section Page Item Description
13.2.8 Memory Control
Register (MCR)
355 Bits 15 to 13—Write
Precharge Delay (TRWL2–
TRWL0)
Description added
358 For Synchronous DRAM
Interface
AMX6 description and
Notes amended
13.2.10 Synchronous DRAM
Mode Register (SDMR)
362 to
364
Description amended,
and Note added
370 Description amended13.3.1 Endian/Access Size
and Data Alignment
371 Data Configuration Quadword partially
amended
13.3.2 Areas 382 Area 0, Area 1 Description added and
amended
13.3.3 SRAM Interface 387 Basic interface changed
to SRAM interface
387 Basic Timing Description amended
388, 393
to 395
Figures 13.6, 13.11 to 13.13 Notes added
395 Read-Strobe Negate Timing
(Setting Only Possible in the
SH7750R)
Description added and
amended
13.3.4 DRAM Interface 400 to 408 Figures 13.17 to 13.22 Notes added
13.3.5 Synchronous DRAM
Interface
413 Connection of Synchronous
DRAM
Description added
415 Address Multiplexing Description amended
417 to
428
Figure 13.28 to 13.37 Note added
435 Power-On Sequence Newly added
438 Notes on Changing the Burst
Length (Variation Only
Possible in the SH7750R)
Newly added
440 Connecting a 128-Mbit/256-
Mbit Synchronous DRAM with
64-bit Bus Width
Newly added
13.3.6 Burst ROM Interface 441, 442 Description amended
442 to 444 Figure 13.46 to 13.48 Notes added
Rev. 6.0, 07/02, page xii of I
Section Page Item Description
13.3.7 PCMCIA Interface 444, 445 Description amended
and added
446 Table 13.18 Relationship
between Address and CE
when Using PCMCIA
Interface
Table amended
449, 452
to 454
Figures 13.50, 13.53 to 13.55 Notes added
450 Figure 13.51 Wait Timing for
PCMCIA Memory Card
Interface
SH7750R added to
Note
451 Figure 13.52 PCMCIA Space
Allocation
Amended
13.3.8 MPX Interface 455 Description added and
amended
471 Figure 13.71 MPX Interface
Timing 7
Amended
457 to 472 Figures 13.57 to 13.72 Notes added
473 Description amended13.3.9 Byte Control SRAM
Interface
475 to 477 Figures 13.74 to 13.76 Notes added
13.3.10 Waits between
Access Cycles
479 Figure 13.77 Waits between
Access Cycles
Replaced
13.3.11 Bus Arbitration 480, 481 Description added and
amended
13.3.16 Notes on Usage 487 Refresh, Bus Arbitration Description amended
487 Synchronous DRAM Mode
Register Setting (SH7750,
SH7750R Only)
Newly added
14.1 Overview 489 Description added and
amended
14.1.1 Features 489 to 491 Description amended
492 Title amended14.1.2 Block Diagram
(SH7750, SH7750S)
492 Figure 14.1 Block Diagram
of DMAC
Amended
14.2 Register Descriptions
(SH7750, SH7750S)
496 Title amended
Rev. 6.0, 07/02, page xiii of I
Section Page Item Description
14.2.1 DMA Source Address
Registers 0–3 (SAR0–SAR3)
496 Description amended
14.2.2 DMA Destination
Address Registers 0–3
(DAR0–DAR3)
497 Description amended
14.2.3 DMA Transfer Count
Registers 0–3 (DMATCR0–
DMATCR3)
498 Description amended
499 Description of DDT
mode added
502, 503 Bits 19 to 16 Initial value changed
503 Bits 15, 14 and Bits 13, 12 Description amended
14.2.4 DMA Channel Control
Registers 0–3 (CHCR0–
CHCR3)
505 Bits 6 to 4 Description added
14.2.5 DMA Operation
Register (DMAOR)
508 Bit 4 Description amended
14.3.2 DMA Transfer
Requests
513 • External Request
Acceptance Conditions
Description added
14.3.4 Types of DMA
Transfer
526 Table 14.9 External Request
Transfer Sources and
Destinations in DDT Mode
Usable DMAC channels
changed
525 (a) Normal DMA Mode Description amendment
14.3.5 Number of Bus Cycle
States and DREQ Pin
Sampling Timing
533 to
535
Figure 14.15 to 14.17 Figure description
added
14.5 On-Demand Data
Transfer Mode (DDT Mode)
545 Description
amendments
14.5.2 Pins in DDT Mode 547 BAVL: Data bus D63–D0
release signal
Description added
551, 552 Figures 14.26, 14.27 Title amended14.5.3 Transfer Request
Acceptance on Each Channel
553 Figure 14.28 Newly added
554 Figure 14.29 Amended
554, 555 Figure 14.30, 14.31 Errors corrected
14.5.4 Notes on Use of DDT
Module
572 c. of 3. Handshake protocol
using the data bus (valid on
channel 0 only)
Description amended
573 b. of 8. Data transfer end
request
Added
573 12. Confirming DMA transfer
requests and number of
transfers executed
Description amended
Rev. 6.0, 07/02, page xiv of I
Section Page Item Description
14.6 Configuration of the
DMAC (SH7750R)
574 Newly added
14.7 Register Descriptions
(SH7750R)
579 Newly added
14.8 Operation (SH7750R) 586 Added
14.9 Usage Notes 591 4. Description amended
592 9. Newly added
15.2.8 Serial Port Register
(SCSPTR1)
609 Bit 7 Description amended
16.1.2 Block Diagram 659 Figure 16.1 Block Diagram
of SCIF
Amended
16.1.3 Pin Configuration 660 Table 16.1 SCIF Pins Note changed
16.2.6 Serial Control
Register (SCSCR2)
667 Bit 1 Description amended
16.2.7 Serial Status Register
(SCFSR2)
669 Bit 7—Receive Error (ER) Note description
changed
672 Bit 3—Framing Error (FER) Description changed
672 Bit 2—Parity Error (PER) Description changed
16.2.9 FIFO Control Register
(SCFCR2)
676 Bits 10 to 8 SH7750R added
16.2.11 Serial Port Register
(SCSPTR2)
Figure 16.6 MRESET/SCK2
Pin
Deleted
16.3.2 Serial Operation 689 Figure 16.6 Sample SCIF
Initialization Flowchart
Amended
696 Serial Data Reception Description added to 5.
17.1 Overview 703 Description amended
17.3.2 Pin Connections 711 Description deleted
18.1.3 Pin Configuration 740 Table 18.3 SCIF I/O Port
Pins
Amended
19.1.2 Block Diagram 752 Figure 19.1 Block Diagram
of INTC
Amended
19.1.4 Register Configuration 753 Table 19.2 INTC Registers Description added to
table, Notes added and
amended
19.2.3 On-Chip Peripheral
Module Interrupts
757, 758 Description added and
amended
Rev. 6.0, 07/02, page xv of I
Section Page Item Description
758 Description added
19.2.4 Interrupt Exception
Handling and Priority
759 to
761
Table 19.5 Interrupt
Exception Handling Sources
and Priority Order
Description added to
table, Notes added and
amended
19.3.1 Interrupt Priority
Registers A to D (IPRA–
IPRD)
762 Table 19.6 Interrupt Request
Sources and IPRA–IPRD
Registers
SH7750R added to
Note 3
19.3.3 Interrupt-Priority-Level
Setting Register 00
(INTPRI00)
764 Newly added
19.3.4 Interrupt Source
Register 00 (INTREQ00)
(SH7750R Only)
765 Newly added
19.3.5 Interrupt Mask
Register 00 (INTMSK00)
(SH7750R Only)
766 Newly added
19.3.6 Interrupt Mask Clear
Register 00 (INTMSKCLR00)
(SH7750R Only)
767 Newly added
19.3.7 Bit Assignments of
INTREQ00, INTMSK00, and
INTMSKCLR00 (SH7750R
Only)
767 19.3.4 moved to 19.3.7
19.4.1 Interrupt Operation
Sequence
768 Note 3 added
19.5 Interrupt Response
Time
771 Note amended
20.2.4 Break Address Mask
Register (BAMRA)
778, 779 Bit 2, and Bits 3, 1, and 0 Description added
20.2.10 Break Data Mask
Register B (BDMRB)
783 Bits 31 to 0 Description added
20.3.7 Program Counter
(PC) Value Saved
791 20.3.7 Program Counter
(PC) Value Saved
4. Description added
20.4 User Break Debug
Support Function
794 Figure 20.2 User Break
Debug Support Function
Flowchart
Amended
21.1.1 Features 799 Description amended
21.1.2 Block Diagram 800 Figure 21.1 Block Diagram
of H-UDI Circuit
Figure changed and
Note added
Rev. 6.0, 07/02, page xvi of I
Section Page Item Description
21.1.3 Pin Configuration 801 Table 21.1 H-UDI Pins Table amended and
Note 3 added
21.1.4 Register Configuration 802 Table 21.2 H-UDI Registers Description added to
table and Notes 3 and 4
added
21.2.1 Instruction Register
(SDIR)
804 [SH7750R] description
added
21.2.4 Interrupt Source
Register (SDINT)
806 Newly added
21.2.5 Boundary Scan
Register (SDBSR)
806 Newly added
808, 809 Table 21.3 Configuration of
the Boundary Scan Register
(2), (3)
Newly added
21.3.3 H-UDI Interrupt 811 Description changed
21.3.4 BYPASS Deleted
21.3.4 Boundary Scan
(EXTEST, SAMPLE/
PRELOAD, BYPASS)
812 Newly added
21.4 Usage Notes 812 5. Description added
22.1 Absolute Maximum
Ratings
813 Table 22.1 Absolute
Maximum Ratings
Table amended and
notes amended
22.2 DC Characteristics 814, 815 Table 22.2
DC Characteristics
(HD6417750RBP240)
Newly added
816, 817 Table 22.3
DC Characteristics
(HD6417750RF240)
Newly added
818, 819 Table 22.4
DC Characteristics
(HD6417750RBP200)
Newly added
820, 821 Table 22.5
DC Characteristics
(HD6417750RF200)
Newly added
822, 823 Table 22.6
DC Characteristics
(HD6417750SBP200)
Amended
826, 827 Table 22.8
DC Characteristics
(HD6417750BP200M)
Amended
Rev. 6.0, 07/02, page xvii of I
Section Page Item Description
22.2 DC Characteristics 836, 837 Table 22.13
DC Characteristics
(HD6417750SVF133)
Amended
838, 839 Table 22.14
DC Characteristics
(HD6417750SVBT133)
Amended
840, 841 Table 22.15
DC Characteristics
(HD6417750VF128)
Amended
22.3 AC Characteristics 842 Table 22.17 Clock Timing
(HD6417750RBP240)
Newly added
842 Table 22.18 Clock Timing
(HD6417750RF240)
Newly added
842 Table 22.19 Clock Timing
(HD6417750BP200M,
HD6417750SBP200,
HD6417750RBP200)
HD6417750RBP200
clock timing added
842 Table 22.20 Clock Timing
(HD6417750RF200)
Newly added
842 Table 22.21 Clock Timing
(HD6417750SF200)
Amended
843 Table 22.22 Clock Timing
(HD6417750F167,
HD6417750F167I,
HD6417750SF167,
HD6417750SF167I)
Amended
843 Table 22.23 Clock Timing
(HD6417750SVF133,
HD6417750SVBT133)
Amended
843 Table 22.24 Clock Timing
(HD6417750VF128)
Amended
22.3.1 Clock and Control
Signal Timing
844, 845 Table 22.25 Clock and
Control Signal Timing
(HD6417750RBP240)
Newly added
846, 847 Table 22.26 Clock and
Control Signal Timing
(HD6417750RF240)
Newly added
848, 849 Table 22.27 Clock and
Control Signal Timing
(HD6417750RBP200)
Newly added
Rev. 6.0, 07/02, page xviii of I
Section Page Item Description
22.3.1 Clock and Control
Signal Timing
850, 851 Table 22.28 Clock and
Control Signal Timing
(HD6417750RF200)
Newly added
852, 853 Table 22.29 Clock and
Control Signal Timing
(HD6417750BP200M,
HD6417750SBP200)
Newly added
854, 855 Table 22.30 Clock and
Control Signal Timing
(HD6417750SF200)
Amended
856, 857 Table 22.31 Clock and
Control Signal Timing
(HD6417750F167,
HD6417750F167I,
HD6417750SF167,
HD6417750SF167I)
Amended
858, 859 Table 22.32 Clock and
Control Signal Timing
(HD6417750SVF133,
HD6417750SVBT133)
Amended
860, 861 Table 22.33 Clock and
Control Signal Timing
(HD6417750VF128)
Amended
864 Figure 22.6 Standby Return
Oscillation Settling Time
(Return by RESET)
Amended
865 Figure 22.8 Standby Return
Oscillation Settling Time
(Return by IRL3–IRL0)
Amended
866 Figure 22.10 PLL
Synchronization Settling Time
in Case of IRL Interrupt
Amended
22.3.2 Control Signal Timing 868 Table 22.34 Control Signal
Timing (1)
Table newly added
22.3.3 Bus Timing 880 Figure 22.18 SRAM Bus
Cycle: Basic Bus Cycle (No
Wait, Address Setup/Hold
Time Insertion, AnS = 1,
AnH = 1)
Figure changed and
Note added
881 Figure 22.19 Burst ROM
Bus Cycle (No Wait)
Amended
871, 872 Table 22.35 Bus Timing (1) Table newly added
Rev. 6.0, 07/02, page xix of I
Section Page Item Description
22.3.4 Peripheral Module
Signal Timing
924, 925 Table 22.36 Peripheral
Module Signal Timing (1)
Table newly added
900 to
921, 923
Figures 22.37 to 22.58,
Figure 22.60
Titles amended
930 Figure 22.62 RTC Oscillation
Settling Time at Power-On
Amended
932 Figure 22.66(b) DBREQ/TR
Input Timing and BAVL
Output Timing
Newly added
Appendix A Address List 937 to
942
Table A.1 Address List BCR4, RCR3, RYRAR,
SDINT and Notes
added
BCR3 area 7 address
amended
DMAC, INTC, CPG,
TMU table added
Appendix B Package
Dimensions
943, 944 Figure B.1 Package
Dimensions (256-Pin BGA)
Figure B.2 Package
Dimensions (208-Pin QFP)
Amended
Appendix C Mode Pin
Settings
946 Clock Modes Table 10.3 (1), (2)
inserted
947 Area 0 Bus Width Area 0 memory type
deleted and data
integrated into area 0
bus width table
Appendix D CKIO2ENB Pin
Configuration
948 Figure D.1 CKIO2ENB Pin
Configuration
Amended
Appendix E Pin Functions 950 to
952
Table E.1 Pin States in
Reset, Power-Down State,
and Bus-Released State
Sleep row deleted
D40–D51 deleted
Notes added
Appendix F Synchronous
DRAM Address
Multiplexing Tables
970, 971 (17) BUS 64
(128M: 4M × 8b × 4) × 8
(SH7750R only)
(18) BUS 64
(256M: 4M × 16b × 4) × 4
(SH7750R only)
Newly added
Rev. 6.0, 07/02, page xx of I
Section Page Item Description
Appendix F Synchronous
DRAM Address
Multiplexing Tables
972, 973 (19) BUS 32
(128M: 4M × 8b × 4) × 4
(SH7750S and SH7750R
only)
(20) BUS 32
(256M: 4M × 16b × 4) × 2
(SH7750S and SH7750R
only)
SH7750R added
Appendix H Power-On and
Power-Off Procedures
977 to
979
Newly added
Appendix I Product Code
Lineup
980 Table I.1 SH7750 Series
Product Code Lineup
SH7750R added
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Hitachi SH7750R User manual

Type
User manual
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