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K21 Sub-Family Reference Manual
Supports: MK21FX512AVLQ12, MK21FN1M0AVLQ12,
MK21FX512AVMD12, MK21FN1M0AVMD12
Document Number: K21P144M120SF5V2RM
Rev. 3, May 2014
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Contents
Section number Title Page
Chapter 1
About This Document
1.1 Overview.......................................................................................................................................................................55
1.1.1 Purpose.........................................................................................................................................................55
1.1.2 Audience......................................................................................................................................................55
1.2 Conventions..................................................................................................................................................................55
1.2.1 Numbering systems......................................................................................................................................55
1.2.2 Typographic notation...................................................................................................................................56
1.2.3 Special terms................................................................................................................................................56
Chapter 2
Introduction
2.1 Overview.......................................................................................................................................................................57
2.2 Module Functional Categories......................................................................................................................................57
2.2.1 ARM® Cortex®-M4 based core modules...................................................................................................58
2.2.2 System Modules...........................................................................................................................................59
2.2.3 Memories and Memory Interfaces...............................................................................................................60
2.2.4 Clocks...........................................................................................................................................................61
2.2.5 Security and Integrity modules....................................................................................................................61
2.2.6 Analog modules...........................................................................................................................................62
2.2.7 Timer modules.............................................................................................................................................62
2.2.8 Communication interfaces...........................................................................................................................63
2.2.9 Human-machine interfaces..........................................................................................................................64
2.3 Orderable part numbers.................................................................................................................................................64
Chapter 3
Chip Configuration
3.1 Introduction...................................................................................................................................................................67
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3.2 Core modules................................................................................................................................................................67
3.2.1 ARM Cortex-M4 Core Configuration..........................................................................................................67
3.2.2 Nested Vectored Interrupt Controller (NVIC) Configuration......................................................................69
3.2.3 Asynchronous Wake-up Interrupt Controller (AWIC) Configuration.........................................................75
3.2.4 JTAG Controller Configuration...................................................................................................................77
3.3 System modules............................................................................................................................................................77
3.3.1 SIM Configuration.......................................................................................................................................77
3.3.2 System Mode Controller (SMC) Configuration...........................................................................................78
3.3.3 PMC Configuration......................................................................................................................................79
3.3.4 Low-Leakage Wake-up Unit (LLWU) Configuration.................................................................................79
3.3.5 MCM Configuration....................................................................................................................................81
3.3.6 Crossbar Switch Configuration....................................................................................................................82
3.3.7 Memory Protection Unit (MPU) Configuration...........................................................................................84
3.3.8 Peripheral Bridge Configuration..................................................................................................................87
3.3.9 DMA request multiplexer configuration......................................................................................................88
3.3.10 DMA Controller Configuration...................................................................................................................90
3.3.11 External Watchdog Monitor (EWM) Configuration....................................................................................91
3.3.12 Watchdog Configuration..............................................................................................................................93
3.4 Clock modules..............................................................................................................................................................94
3.4.1 MCG Configuration.....................................................................................................................................94
3.4.2 OSC Configuration......................................................................................................................................95
3.4.3 RTC OSC configuration...............................................................................................................................96
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3.5 Memories and memory interfaces.................................................................................................................................96
3.5.1 Flash Memory Configuration.......................................................................................................................96
3.5.2 Flash Memory Controller Configuration.....................................................................................................100
3.5.3 SRAM Configuration...................................................................................................................................101
3.5.4 System Register File Configuration.............................................................................................................105
3.5.5 VBAT Register File Configuration..............................................................................................................105
3.5.6 EzPort Configuration...................................................................................................................................106
3.5.7 FlexBus Configuration.................................................................................................................................107
3.6 Security.........................................................................................................................................................................110
3.6.1 CRC Configuration......................................................................................................................................110
3.6.2 MMCAU Configuration...............................................................................................................................111
3.6.3 RNG Configuration......................................................................................................................................112
3.6.4 DryIce (tamper detect and secure storage) configuration............................................................................112
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3.7 Analog...........................................................................................................................................................................113
3.7.1 16-bit SAR ADC Configuration..................................................................................................................113
3.7.2 CMP Configuration......................................................................................................................................119
3.7.3 12-bit DAC Configuration...........................................................................................................................121
3.7.4 VREF Configuration....................................................................................................................................122
3.8 Timers...........................................................................................................................................................................123
3.8.1 PDB Configuration......................................................................................................................................123
3.8.2 FlexTimer Configuration.............................................................................................................................127
3.8.3 PIT Configuration........................................................................................................................................131
3.8.4 Low-power timer configuration...................................................................................................................132
3.8.5 CMT Configuration......................................................................................................................................134
3.8.6 RTC configuration.......................................................................................................................................135
3.9 Communication interfaces............................................................................................................................................136
3.9.1 Universal Serial Bus (USB) FS Subsystem.................................................................................................136
3.9.2 CAN Configuration......................................................................................................................................142
3.9.3 SPI configuration.........................................................................................................................................144
3.9.4 I2C Configuration........................................................................................................................................148
3.9.5 UART Configuration...................................................................................................................................148
3.9.6 SDHC Configuration....................................................................................................................................151
3.9.7 I2S configuration..........................................................................................................................................152
3.10 Human-machine interfaces...........................................................................................................................................155
3.10.1 GPIO configuration......................................................................................................................................155
Chapter 4
Memory Map
4.1 Introduction...................................................................................................................................................................157
4.2 System memory map.....................................................................................................................................................157
4.2.1 Aliased bit-band regions..............................................................................................................................158
4.3 Flash Memory Map.......................................................................................................................................................159
4.3.1 Alternate Non-Volatile IRC User Trim Description....................................................................................160
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4.4 SRAM memory map.....................................................................................................................................................161
4.5 Peripheral bridge (AIPS-Lite0 and AIPS-Lite1) memory map....................................................................................161
4.5.1 Read-after-write sequence and required serialization of memory operations..............................................161
4.5.2 Peripheral Bridge 0 (AIPS-Lite 0) Memory Map........................................................................................162
4.5.3 Peripheral Bridge 1 (AIPS-Lite 1) Memory Map........................................................................................166
4.6 Private Peripheral Bus (PPB) memory map..................................................................................................................169
Chapter 5
Clock Distribution
5.1 Introduction...................................................................................................................................................................171
5.2 Programming model......................................................................................................................................................171
5.3 High-Level device clocking diagram............................................................................................................................171
5.4 Clock definitions...........................................................................................................................................................172
5.4.1 Device clock summary.................................................................................................................................173
5.5 Internal clocking requirements.....................................................................................................................................175
5.5.1 Clock divider values after reset....................................................................................................................175
5.5.2 VLPR mode clocking...................................................................................................................................176
5.6 Clock Gating.................................................................................................................................................................176
5.7 Module clocks...............................................................................................................................................................176
5.7.1 PMC 1-kHz LPO clock................................................................................................................................178
5.7.2 WDOG clocking..........................................................................................................................................178
5.7.3 Debug trace clock.........................................................................................................................................179
5.7.4 PORT digital filter clocking.........................................................................................................................179
5.7.5 LPTMR clocking..........................................................................................................................................180
5.7.6 USB FS OTG Controller clocking...............................................................................................................180
5.7.7 FlexCAN clocking.......................................................................................................................................181
5.7.8 UART clocking............................................................................................................................................181
5.7.9 SDHC clocking............................................................................................................................................182
5.7.10 I2S/SAI clocking..........................................................................................................................................182
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Chapter 6
Reset and Boot
6.1 Introduction...................................................................................................................................................................185
6.2 Reset..............................................................................................................................................................................186
6.2.1 Power-on reset (POR)..................................................................................................................................186
6.2.2 System reset sources....................................................................................................................................186
6.2.3 MCU Resets.................................................................................................................................................190
6.2.4 Reset Pin .....................................................................................................................................................192
6.2.5 Debug resets.................................................................................................................................................192
6.3 Boot...............................................................................................................................................................................193
6.3.1 Boot sources.................................................................................................................................................193
6.3.2 Boot options.................................................................................................................................................194
6.3.3 FOPT boot options.......................................................................................................................................194
6.3.4 Boot sequence..............................................................................................................................................195
Chapter 7
Power Management
7.1 Introduction...................................................................................................................................................................197
7.2 Power Modes Description.............................................................................................................................................197
7.3 Entering and exiting power modes...............................................................................................................................199
7.4 Power mode transitions.................................................................................................................................................200
7.5 Power modes shutdown sequencing.............................................................................................................................201
7.6 Module Operation in Low Power Modes......................................................................................................................202
7.7 Clock Gating.................................................................................................................................................................205
Chapter 8
Security
8.1 Introduction...................................................................................................................................................................207
8.2 Flash Security...............................................................................................................................................................207
8.3 Security Interactions with other Modules.....................................................................................................................208
8.3.1 Security interactions with FlexBus..............................................................................................................208
8.3.2 Security Interactions with EzPort................................................................................................................208
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8.3.3 Security Interactions with Debug.................................................................................................................208
Chapter 9
Debug
9.1 Introduction...................................................................................................................................................................211
9.1.1 References....................................................................................................................................................213
9.2 The Debug Port.............................................................................................................................................................213
9.2.1 JTAG-to-SWD change sequence.................................................................................................................214
9.2.2 JTAG-to-cJTAG change sequence...............................................................................................................214
9.3 Debug Port Pin Descriptions.........................................................................................................................................215
9.4 System TAP connection................................................................................................................................................215
9.4.1 IR Codes.......................................................................................................................................................215
9.5 JTAG status and control registers.................................................................................................................................216
9.5.1 MDM-AP Control Register..........................................................................................................................217
9.5.2 MDM-AP Status Register............................................................................................................................219
9.6 Debug Resets................................................................................................................................................................220
9.7 AHB-AP........................................................................................................................................................................221
9.8 ITM...............................................................................................................................................................................222
9.9 Core Trace Connectivity...............................................................................................................................................222
9.10 Embedded Trace Macrocell v3.5 (ETM)......................................................................................................................222
9.11 Coresight Embedded Trace Buffer (ETB)....................................................................................................................223
9.11.1 Performance Profiling with the ETB...........................................................................................................223
9.11.2 ETB Counter Control...................................................................................................................................224
9.12 TPIU..............................................................................................................................................................................224
9.13 DWT.............................................................................................................................................................................224
9.14 Debug in Low Power Modes........................................................................................................................................225
9.14.1 Debug Module State in Low Power Modes.................................................................................................226
9.15 Debug & Security.........................................................................................................................................................226
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Chapter 10
Signal Multiplexing and Signal Descriptions
10.1 Introduction...................................................................................................................................................................227
10.2 Signal Multiplexing Integration....................................................................................................................................227
10.2.1 Port control and interrupt module features..................................................................................................228
10.2.2 Port control and interrupt summary.............................................................................................................228
10.2.3 PCRn reset values for port A.......................................................................................................................229
10.2.4 Clock gating.................................................................................................................................................229
10.2.5 Signal multiplexing constraints....................................................................................................................229
10.3 Pinout............................................................................................................................................................................230
10.3.1 K21 Signal Multiplexing and Pin Assignments...........................................................................................230
10.3.2 K21 Pinouts..................................................................................................................................................236
10.4 Module Signal Description Tables................................................................................................................................238
10.4.1 Core Modules...............................................................................................................................................239
10.4.2 System Modules...........................................................................................................................................239
10.4.3 Clock Modules.............................................................................................................................................240
10.4.4 Memories and Memory Interfaces...............................................................................................................240
10.4.5 Security Modules.........................................................................................................................................243
10.4.6 Analog..........................................................................................................................................................243
10.4.7 Timer Modules.............................................................................................................................................245
10.4.8 Communication Interfaces...........................................................................................................................247
10.4.9 Human-Machine Interfaces (HMI)..............................................................................................................251
Chapter 11
Port Control and Interrupts (PORT)
11.1 Introduction...................................................................................................................................................................253
11.2 Overview.......................................................................................................................................................................253
11.2.1 Features........................................................................................................................................................253
11.2.2 Modes of operation......................................................................................................................................254
11.3 External signal description............................................................................................................................................255
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11.4 Detailed signal description............................................................................................................................................255
11.5 Memory map and register definition.............................................................................................................................255
11.5.1 Pin Control Register n (PORTx_PCRn).......................................................................................................262
11.5.2 Global Pin Control Low Register (PORTx_GPCLR)..................................................................................264
11.5.3 Global Pin Control High Register (PORTx_GPCHR).................................................................................265
11.5.4 Interrupt Status Flag Register (PORTx_ISFR)............................................................................................266
11.5.5 Digital Filter Enable Register (PORTx_DFER)...........................................................................................266
11.5.6 Digital Filter Clock Register (PORTx_DFCR)............................................................................................267
11.5.7 Digital Filter Width Register (PORTx_DFWR)..........................................................................................267
11.6 Functional description...................................................................................................................................................268
11.6.1 Pin control....................................................................................................................................................268
11.6.2 Global pin control........................................................................................................................................269
11.6.3 External interrupts........................................................................................................................................269
11.6.4 Digital filter..................................................................................................................................................270
Chapter 12
System Integration Module (SIM)
12.1 Introduction...................................................................................................................................................................273
12.1.1 Features........................................................................................................................................................273
12.2 Memory map and register definition.............................................................................................................................274
12.2.1 System Options Register 1 (SIM_SOPT1)..................................................................................................275
12.2.2 SOPT1 Configuration Register (SIM_SOPT1CFG)....................................................................................277
12.2.3 System Options Register 2 (SIM_SOPT2)..................................................................................................278
12.2.4 System Options Register 4 (SIM_SOPT4)..................................................................................................280
12.2.5 System Options Register 5 (SIM_SOPT5)..................................................................................................283
12.2.6 System Options Register 7 (SIM_SOPT7)..................................................................................................285
12.2.7 System Device Identification Register (SIM_SDID)...................................................................................287
12.2.8 System Clock Gating Control Register 1 (SIM_SCGC1)............................................................................288
12.2.9 System Clock Gating Control Register 2 (SIM_SCGC2)............................................................................289
12.2.10 System Clock Gating Control Register 3 (SIM_SCGC3)............................................................................291
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12.2.11 System Clock Gating Control Register 4 (SIM_SCGC4)............................................................................293
12.2.12 System Clock Gating Control Register 5 (SIM_SCGC5)............................................................................295
12.2.13 System Clock Gating Control Register 6 (SIM_SCGC6)............................................................................297
12.2.14 System Clock Gating Control Register 7 (SIM_SCGC7)............................................................................300
12.2.15 System Clock Divider Register 1 (SIM_CLKDIV1)...................................................................................300
12.2.16 System Clock Divider Register 2 (SIM_CLKDIV2)...................................................................................303
12.2.17 Flash Configuration Register 1 (SIM_FCFG1)...........................................................................................304
12.2.18 Flash Configuration Register 2 (SIM_FCFG2)...........................................................................................307
12.2.19 Unique Identification Register High (SIM_UIDH).....................................................................................308
12.2.20 Unique Identification Register Mid-High (SIM_UIDMH)..........................................................................309
12.2.21 Unique Identification Register Mid Low (SIM_UIDML)...........................................................................309
12.2.22 Unique Identification Register Low (SIM_UIDL)......................................................................................310
12.3 Functional description...................................................................................................................................................310
Chapter 13
Reset Control Module (RCM)
13.1 Introduction...................................................................................................................................................................311
13.2 Reset memory map and register descriptions...............................................................................................................311
13.2.1 System Reset Status Register 0 (RCM_SRS0)............................................................................................312
13.2.2 System Reset Status Register 1 (RCM_SRS1)............................................................................................313
13.2.3 Reset Pin Filter Control register (RCM_RPFC)..........................................................................................315
13.2.4 Reset Pin Filter Width register (RCM_RPFW)...........................................................................................316
13.2.5 Mode Register (RCM_MR).........................................................................................................................317
Chapter 14
System Mode Controller (SMC)
14.1 Introduction...................................................................................................................................................................319
14.2 Modes of operation.......................................................................................................................................................319
14.3 Memory map and register descriptions.........................................................................................................................321
14.3.1 Power Mode Protection register (SMC_PMPROT).....................................................................................322
14.3.2 Power Mode Control register (SMC_PMCTRL).........................................................................................323
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14.3.3 VLLS Control register (SMC_VLLSCTRL)...............................................................................................325
14.3.4 Power Mode Status register (SMC_PMSTAT)...........................................................................................326
14.4 Functional description...................................................................................................................................................326
14.4.1 Power mode transitions................................................................................................................................326
14.4.2 Power mode entry/exit sequencing..............................................................................................................329
14.4.3 Run modes....................................................................................................................................................332
14.4.4 Wait modes..................................................................................................................................................333
14.4.5 Stop modes...................................................................................................................................................334
14.4.6 Debug in low power modes.........................................................................................................................337
Chapter 15
Power Management Controller (PMC)
15.1 Introduction...................................................................................................................................................................339
15.2 Features.........................................................................................................................................................................339
15.3 Low-voltage detect (LVD) system................................................................................................................................339
15.3.1 LVD reset operation.....................................................................................................................................340
15.3.2 LVD interrupt operation...............................................................................................................................340
15.3.3 Low-voltage warning (LVW) interrupt operation.......................................................................................340
15.4 I/O retention..................................................................................................................................................................341
15.5 Memory map and register descriptions.........................................................................................................................341
15.5.1 Low Voltage Detect Status And Control 1 register (PMC_LVDSC1)........................................................342
15.5.2 Low Voltage Detect Status And Control 2 register (PMC_LVDSC2)........................................................343
15.5.3 Regulator Status And Control register (PMC_REGSC)..............................................................................344
Chapter 16
Low-Leakage Wakeup Unit (LLWU)
16.1 Introduction...................................................................................................................................................................347
16.1.1 Features........................................................................................................................................................347
16.1.2 Modes of operation......................................................................................................................................348
16.1.3 Block diagram..............................................................................................................................................349
16.2 LLWU signal descriptions............................................................................................................................................350
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16.3 Memory map/register definition...................................................................................................................................351
16.3.1 LLWU Pin Enable 1 register (LLWU_PE1)................................................................................................352
16.3.2 LLWU Pin Enable 2 register (LLWU_PE2)................................................................................................353
16.3.3 LLWU Pin Enable 3 register (LLWU_PE3)................................................................................................354
16.3.4 LLWU Pin Enable 4 register (LLWU_PE4)................................................................................................355
16.3.5 LLWU Module Enable register (LLWU_ME)............................................................................................356
16.3.6 LLWU Flag 1 register (LLWU_F1).............................................................................................................358
16.3.7 LLWU Flag 2 register (LLWU_F2).............................................................................................................359
16.3.8 LLWU Flag 3 register (LLWU_F3).............................................................................................................361
16.3.9 LLWU Pin Filter 1 register (LLWU_FILT1)..............................................................................................363
16.3.10 LLWU Pin Filter 2 register (LLWU_FILT2)..............................................................................................364
16.3.11 LLWU Reset Enable register (LLWU_RST)...............................................................................................365
16.4 Functional description...................................................................................................................................................366
16.4.1 LLS mode.....................................................................................................................................................366
16.4.2 VLLS modes................................................................................................................................................366
16.4.3 Initialization.................................................................................................................................................367
Chapter 17
Miscellaneous Control Module (MCM)
17.1 Introduction...................................................................................................................................................................369
17.1.1 Features........................................................................................................................................................369
17.2 Memory map/register descriptions...............................................................................................................................369
17.2.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)................................................................370
17.2.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC)............................................................371
17.2.3 Control Register (MCM_CR)......................................................................................................................372
17.2.4 Interrupt Status Register (MCM_ISCR)......................................................................................................374
17.2.5 ETB Counter Control register (MCM_ETBCC)..........................................................................................377
17.2.6 ETB Reload register (MCM_ETBRL).........................................................................................................378
17.2.7 ETB Counter Value register (MCM_ETBCNT)..........................................................................................378
17.2.8 Process ID register (MCM_PID).................................................................................................................379
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17.3 Functional description...................................................................................................................................................379
17.3.1 Interrupts......................................................................................................................................................379
Chapter 18
Crossbar Switch (AXBS)
18.1 Introduction...................................................................................................................................................................381
18.1.1 Features........................................................................................................................................................381
18.2 Memory Map / Register Definition...............................................................................................................................382
18.2.1 Priority Registers Slave (AXBS_PRSn)......................................................................................................383
18.2.2 Control Register (AXBS_CRSn).................................................................................................................385
18.2.3 Master General Purpose Control Register (AXBS_MGPCRn)...................................................................387
18.3 Functional Description..................................................................................................................................................388
18.3.1 General operation.........................................................................................................................................388
18.3.2 Register coherency.......................................................................................................................................389
18.3.3 Arbitration....................................................................................................................................................389
18.4 Initialization/application information...........................................................................................................................392
Chapter 19
Memory Protection Unit (MPU)
19.1 Introduction...................................................................................................................................................................393
19.2 Overview.......................................................................................................................................................................393
19.2.1 Block diagram..............................................................................................................................................393
19.2.2 Features........................................................................................................................................................394
19.3 Memory map/register definition...................................................................................................................................395
19.3.1 Control/Error Status Register (MPU_CESR)..............................................................................................398
19.3.2 Error Address Register, slave port n (MPU_EARn)....................................................................................399
19.3.3 Error Detail Register, slave port n (MPU_EDRn).......................................................................................400
19.3.4 Region Descriptor n, Word 0 (MPU_RGDn_WORD0)..............................................................................401
19.3.5 Region Descriptor n, Word 1 (MPU_RGDn_WORD1)..............................................................................402
19.3.6 Region Descriptor n, Word 2 (MPU_RGDn_WORD2)..............................................................................402
19.3.7 Region Descriptor n, Word 3 (MPU_RGDn_WORD3)..............................................................................405
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19.3.8 Region Descriptor Alternate Access Control n (MPU_RGDAACn)...........................................................406
19.4 Functional description...................................................................................................................................................408
19.4.1 Access evaluation macro..............................................................................................................................408
19.4.2 Putting it all together and error terminations...............................................................................................410
19.4.3 Power management......................................................................................................................................410
19.5 Initialization information..............................................................................................................................................411
19.6 Application information................................................................................................................................................411
Chapter 20
Peripheral Bridge (AIPS-Lite)
20.1 Introduction...................................................................................................................................................................415
20.1.1 Features........................................................................................................................................................415
20.1.2 General operation.........................................................................................................................................415
20.2 Functional description...................................................................................................................................................416
20.2.1 Access support.............................................................................................................................................416
Chapter 21
Direct Memory Access Multiplexer (DMAMUX)
21.1 Introduction...................................................................................................................................................................417
21.1.1 Overview......................................................................................................................................................417
21.1.2 Features........................................................................................................................................................418
21.1.3 Modes of operation......................................................................................................................................418
21.2 External signal description............................................................................................................................................419
21.3 Memory map/register definition...................................................................................................................................419
21.3.1 Channel Configuration register (DMAMUX_CHCFGn)............................................................................420
21.4 Functional description...................................................................................................................................................421
21.4.1 DMA channels with periodic triggering capability......................................................................................421
21.4.2 DMA channels with no triggering capability...............................................................................................423
21.4.3 Always-enabled DMA sources....................................................................................................................423
21.5 Initialization/application information...........................................................................................................................425
21.5.1 Reset.............................................................................................................................................................425
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21.5.2 Enabling and configuring sources................................................................................................................425
Chapter 22
Enhanced Direct Memory Access (eDMA)
22.1 Introduction...................................................................................................................................................................429
22.1.1 eDMA system block diagram......................................................................................................................429
22.1.2 Block parts...................................................................................................................................................430
22.1.3 Features........................................................................................................................................................431
22.2 Modes of operation.......................................................................................................................................................433
22.3 Memory map/register definition...................................................................................................................................433
22.3.1 TCD memory...............................................................................................................................................433
22.3.2 TCD initialization........................................................................................................................................434
22.3.3 TCD structure...............................................................................................................................................434
22.3.4 Reserved memory and bit fields...................................................................................................................436
22.3.1 Control Register (DMA_CR).......................................................................................................................446
22.3.2 Error Status Register (DMA_ES)................................................................................................................449
22.3.3 Enable Request Register (DMA_ERQ).......................................................................................................451
22.3.4 Enable Error Interrupt Register (DMA_EEI)...............................................................................................453
22.3.5 Clear Enable Error Interrupt Register (DMA_CEEI)..................................................................................455
22.3.6 Set Enable Error Interrupt Register (DMA_SEEI)......................................................................................456
22.3.7 Clear Enable Request Register (DMA_CERQ)...........................................................................................457
22.3.8 Set Enable Request Register (DMA_SERQ)...............................................................................................458
22.3.9 Clear DONE Status Bit Register (DMA_CDNE)........................................................................................459
22.3.10 Set START Bit Register (DMA_SSRT)......................................................................................................460
22.3.11 Clear Error Register (DMA_CERR)............................................................................................................461
22.3.12 Clear Interrupt Request Register (DMA_CINT).........................................................................................462
22.3.13 Interrupt Request Register (DMA_INT)......................................................................................................463
22.3.14 Error Register (DMA_ERR)........................................................................................................................465
22.3.15 Hardware Request Status Register (DMA_HRS)........................................................................................468
22.3.16 Channel n Priority Register (DMA_DCHPRIn)..........................................................................................471
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22.3.17 TCD Source Address (DMA_TCDn_SADDR)...........................................................................................472
22.3.18 TCD Signed Source Address Offset (DMA_TCDn_SOFF)........................................................................472
22.3.19 TCD Transfer Attributes (DMA_TCDn_ATTR).........................................................................................473
22.3.20 TCD Minor Byte Count (Minor Loop Disabled) (DMA_TCDn_NBYTES_MLNO).................................474
22.3.21 TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
(DMA_TCDn_NBYTES_MLOFFNO).......................................................................................................475
22.3.22 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
(DMA_TCDn_NBYTES_MLOFFYES).....................................................................................................476
22.3.23 TCD Last Source Address Adjustment (DMA_TCDn_SLAST).................................................................477
22.3.24 TCD Destination Address (DMA_TCDn_DADDR)...................................................................................478
22.3.25 TCD Signed Destination Address Offset (DMA_TCDn_DOFF)................................................................478
22.3.26 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
(DMA_TCDn_CITER_ELINKYES)...........................................................................................................479
22.3.27 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
(DMA_TCDn_CITER_ELINKNO)............................................................................................................480
22.3.28 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCDn_DLASTSGA)..........481
22.3.29 TCD Control and Status (DMA_TCDn_CSR)............................................................................................482
22.3.30 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
(DMA_TCDn_BITER_ELINKYES)...........................................................................................................484
22.3.31 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
(DMA_TCDn_BITER_ELINKNO)............................................................................................................485
22.4 Functional description...................................................................................................................................................486
22.4.1 eDMA basic data flow.................................................................................................................................486
22.4.2 Fault reporting and handling........................................................................................................................489
22.4.3 Channel preemption.....................................................................................................................................491
22.4.4 Performance.................................................................................................................................................491
22.5 Initialization/application information...........................................................................................................................496
22.5.1 eDMA initialization.....................................................................................................................................496
22.5.2 Programming errors.....................................................................................................................................498
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22.5.3 Arbitration mode considerations..................................................................................................................498
22.5.4 Performing DMA transfers..........................................................................................................................499
22.5.5 Monitoring transfer descriptor status...........................................................................................................503
22.5.6 Channel Linking...........................................................................................................................................505
22.5.7 Dynamic programming................................................................................................................................506
Chapter 23
External Watchdog Monitor (EWM)
23.1 Introduction...................................................................................................................................................................511
23.1.1 Features........................................................................................................................................................511
23.1.2 Modes of Operation.....................................................................................................................................512
23.1.3 Block Diagram.............................................................................................................................................513
23.2 EWM Signal Descriptions............................................................................................................................................514
23.3 Memory Map/Register Definition.................................................................................................................................514
23.3.1 Control Register (EWM_CTRL).................................................................................................................514
23.3.2 Service Register (EWM_SERV)..................................................................................................................515
23.3.3 Compare Low Register (EWM_CMPL)......................................................................................................515
23.3.4 Compare High Register (EWM_CMPH).....................................................................................................516
23.4 Functional Description..................................................................................................................................................517
23.4.1 The EWM_out Signal..................................................................................................................................517
23.4.2 The EWM_in Signal....................................................................................................................................518
23.4.3 EWM Counter..............................................................................................................................................518
23.4.4 EWM Compare Registers............................................................................................................................518
23.4.5 EWM Refresh Mechanism...........................................................................................................................519
23.4.6 EWM Interrupt.............................................................................................................................................519
Chapter 24
Watchdog Timer (WDOG)
24.1 Introduction...................................................................................................................................................................521
24.2 Features.........................................................................................................................................................................521
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24.3 Functional overview......................................................................................................................................................523
24.3.1 Unlocking and updating the watchdog.........................................................................................................524
24.3.2 Watchdog configuration time (WCT)..........................................................................................................525
24.3.3 Refreshing the watchdog..............................................................................................................................526
24.3.4 Windowed mode of operation......................................................................................................................526
24.3.5 Watchdog disabled mode of operation.........................................................................................................526
24.3.6 Debug modes of operation...........................................................................................................................527
24.4 Testing the watchdog....................................................................................................................................................527
24.4.1 Quick test.....................................................................................................................................................528
24.4.2 Byte test........................................................................................................................................................528
24.5 Backup reset generator..................................................................................................................................................529
24.6 Generated resets and interrupts.....................................................................................................................................530
24.7 Memory map and register definition.............................................................................................................................530
24.7.1 Watchdog Status and Control Register High (WDOG_STCTRLH)...........................................................531
24.7.2 Watchdog Status and Control Register Low (WDOG_STCTRLL)............................................................533
24.7.3 Watchdog Time-out Value Register High (WDOG_TOVALH).................................................................533
24.7.4 Watchdog Time-out Value Register Low (WDOG_TOVALL)..................................................................534
24.7.5 Watchdog Window Register High (WDOG_WINH)..................................................................................534
24.7.6 Watchdog Window Register Low (WDOG_WINL)...................................................................................535
24.7.7 Watchdog Refresh register (WDOG_REFRESH).......................................................................................535
24.7.8 Watchdog Unlock register (WDOG_UNLOCK).........................................................................................535
24.7.9 Watchdog Timer Output Register High (WDOG_TMROUTH).................................................................536
24.7.10 Watchdog Timer Output Register Low (WDOG_TMROUTL)..................................................................536
24.7.11 Watchdog Reset Count register (WDOG_RSTCNT)..................................................................................537
24.7.12 Watchdog Prescaler register (WDOG_PRESC)..........................................................................................537
24.8 Watchdog operation with 8-bit access..........................................................................................................................537
24.8.1 General guideline.........................................................................................................................................537
24.8.2 Refresh and unlock operations with 8-bit access.........................................................................................538
24.9 Restrictions on watchdog operation..............................................................................................................................539
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