SCF5250 User’s Manual
Document Number: SCF5250UM
Rev. 4.1
07/2006
How to Reach Us:
Home Page:
www.freescale.com
E-mail:
suppor[email protected]
USA/Europe or Locations Not Listed:
Freescale Semiconductor
Technical Information Center, CH370
1300 N. Alma School Road
Chandler, Arizona 85224
+1-800-521-6274 or +1-480-768-2130
suppor[email protected]
Europe, Middle East, and Africa:
Freescale Halbleiter Deutschland GmbH
Technical Information Center
Schatzbogen 7
81829 Muenchen, Germany
+44 1296 380 456 (English)
+46 8 52200080 (English)
+49 89 92103 559 (German)
+33 1 69 35 48 48 (French)
suppor[email protected]
Japan:
Freescale Semiconductor Japan Ltd.
Headquarters
ARCO Tower 15F
1-8-1, Shimo-Meguro, Meguro-ku,
Tokyo 153-0064, Japan
0120 191014 or +81 3 5437 9125
suppor[email protected]
Asia/Pacific:
Freescale Semiconductor Hong Kong Ltd.
Technical Information Center
2 Dai King Street
Tai Po Industrial Estate
Tai Po, N.T., Hong Kong
+800 26668334
suppor[email protected]
For Literature Requests Only:
Freescale Semiconductor Literature Distribution Center
P.O. Box 5405
Denver, Colorado 80217
1-800-441-2447 or 303-675-2140
Fax: 303-675-2150
LDCForFreescaleSemiconductor@hibbertgroup.com
Information in this document is provided solely to enable system and
software implementers to use Freescale Semiconductor products. There are
no express or implied copyright licenses granted hereunder to design or
fabricate any integrated circuits or integrated circuits based on the
information in this document.
Freescale Semiconductor reserves the right to make changes without further
notice to any products herein. Freescale Semiconductor makes no warranty,
representation or guarantee regarding the suitability of its products for any
particular purpose, nor does Freescale Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation consequential or
incidental damages. “Typical” parameters that may be provided in Freescale
Semiconductor data sheets and/or specifications can and do vary in different
applications and actual performance may vary over time. All operating
parameters, including “Typicals”, must be validated for each customer
application by customer’s technical experts. Freescale Semiconductor does
not convey any license under its patent rights nor the rights of others.
Freescale Semiconductor products are not designed, intended, or authorized
for use as components in systems intended for surgical implant into the body,
or other applications intended to support or sustain life, or for any other
application in which the failure of the Freescale Semiconductor product could
create a situation where personal injury or death may occur. Should Buyer
purchase or use Freescale Semiconductor products for any such unintended
or unauthorized application, Buyer shall indemnify and hold Freescale
Semiconductor and its officers, employees, subsidiaries, affiliates, and
distributors harmless against all claims, costs, damages, and expenses, and
reasonable attorney fees arising out of, directly or indirectly, any claim of
personal injury or death associated with such unintended or unauthorized
use, even if such claim alleges that Freescale Semiconductor was negligent
regarding the design or manufacture of the part.
Freescale™ and the Freescale logo are trademarks of Freescale
Semiconductor, Inc. All other product or service names are the property
of their respective owners.© Freescale Semiconductor, Inc. 2005. All rights
reserved.
Document Number: SCF5250UM
Rev. 4.1
07/2006
SCF5250 User’s Manual, Rev. 4.1
Freescale Semiconductor TOC-1
TABLE OF CONTENTS
SECTION 1
SCF5250 INTRODUCTION
1.1 SCF5250 Overview ........................................................................................................ 1-1
1.2 SCF5250 Feature Introduction ....................................................................................... 1-1
1.3 SCF5250 Block Diagram ................................................................................................ 1-2
1.4 SCF5250 Feature Details ............................................................................................... 1-3
1.5 SCF5250 Functional Overview ...................................................................................... 1-5
1.5.1 ColdFire V2 Core ...................................................................................................... 1-5
1.5.2 DMA Controller ......................................................................................................... 1-5
1.5.3 Enhanced Multiply and Accumulate Module (EMAC) ............................................... 1-5
1.5.4 Instruction Cache ...................................................................................................... 1-6
1.5.5 Internal 128-KB SRAM .............................................................................................. 1-6
1.5.6 DRAM Controller ....................................................................................................... 1-6
1.5.7 System Interface ....................................................................................................... 1-6
1.5.8 External Bus Interface ............................................................................................... 1-6
1.5.9 Serial Audio Interfaces .............................................................................................. 1-6
1.5.10 IEC958 Digital Audio Interfaces ................................................................................ 1-6
1.5.11 Audio Bus .................................................................................................................. 1-7
1.5.12 CD-ROM Encoder/Decoder ...................................................................................... 1-7
1.5.13 Dual UART Module ................................................................................................... 1-7
1.5.14 Queued Serial Peripheral Interface QSPI ................................................................. 1-7
1.5.15 Timer Module ............................................................................................................ 1-8
1.5.16 IDE Interface ............................................................................................................. 1-8
1.5.17 Analog/Digital Converter (ADC) ................................................................................ 1-8
1.5.18 Flash Memory Card Interface ................................................................................... 1-8
1.5.19 I
2
C Module ................................................................................................................ 1-8
1.5.20 Chip-Selects .............................................................................................................. 1-8
1.5.21 GPIO Interface .......................................................................................................... 1-8
1.5.22 Interrupt Controller .................................................................................................... 1-9
1.5.23 JTAG ......................................................................................................................... 1-9
1.5.24 System Debug Interface ........................................................................................... 1-9
1.5.25 On-chip Crystal oscillator and On-chip PLL .............................................................. 1-9
1.5.26 Sleep mode / WAKE-UP ........................................................................................... 1-9
1.5.27 Bootloader ................................................................................................................. 1-9
1.5.28 Internal Voltage Regulator ......................................................................................... 1-9
SECTION 2
SIGNAL DESCRIPTION 1
2.1 Introduction .................................................................................................................... 2-1
2.2 GPIO .............................................................................................................................. 2-5
2.3 SCF5250 Bus Signals .................................................................................................... 2-5
2.3.1 Address Bus .............................................................................................................. 2-5
2.3.2 Read-Write Control ................................................................................................... 2-5
2.3.3 Output Enable ........................................................................................................... 2-5
SCF5250 User’s Manual, Rev. 4.1
TOC-2 Freescale Semiconductor
2.3.4 Data Bus ................................................................................................................... 2-5
2.3.5 Transfer Acknowledge .............................................................................................. 2-5
2.4 SDRAM Controller Signals ............................................................................................. 2-5
2.5 CHIP Selects .................................................................................................................. 2-6
2.6 ISA Bus .......................................................................................................................... 2-6
2.7 Bus Buffer Signals ..........................................................................................................2-6
2.8 I
2
C Module Signals ........................................................................................................ 2-7
2.9 Serial Module Signals .................................................................................................... 2-7
2.10 Timer Module Signals .................................................................................................... 2-8
2.11 Serial Audio Interface Signals ........................................................................................ 2-8
2.12 Digital Audio Interface Signals ....................................................................................... 2-9
2.13 Subcode Interface ..........................................................................................................2-9
2.14 Analog to Digital Converter (ADC) ................................................................................. 2-9
2.15 Secure Digital/ MemoryStick card Interface ................................................................. 2-10
2.16 Queued Serial Peripheral Interface (QSPI) .................................................................. 2-10
2.17 Crystal Trim .................................................................................................................. 2-11
2.18 Clock Out ..................................................................................................................... 2-11
2.19 Debug and Test Signals ............................................................................................... 2-11
2.19.1 Test Mode ............................................................................................................... 2-11
2.19.2 High Impedance ...................................................................................................... 2-11
2.19.3 Processor Clock Output .......................................................................................... 2-11
2.19.4 Debug Data ............................................................................................................. 2-11
2.19.5 Processor Status ..................................................................................................... 2-11
2.20 BDM/JTAG Signals ...................................................................................................... 2-12
2.21 Clock and Reset signals ............................................................................................... 2-12
2.21.1 Reset In ................................................................................................................... 2-13
2.21.2 System Bus input .................................................................................................... 2-13
2.22 Wake-Up Signal ........................................................................................................... 2-13
2.23 On-chip Linear Regulator ............................................................................................. 2-13
SECTION 3
COLDFIRE® CORE
3.1 Processor Pipelines ....................................................................................................... 3-1
3.2 Processor Register Description ...................................................................................... 3-2
3.2.1 User Programming Model ......................................................................................... 3-2
3.2.1.1 Data Registers (D0–D7) ...................................................................................... 3-2
3.2.1.2 Address Registers (A0–A6) ................................................................................. 3-2
3.2.1.3 Stack Pointer (A7,SP) .......................................................................................... 3-2
3.2.1.4 Program Counter (PC) ......................................................................................... 3-3
3.2.1.5 Condition Code Register (CCR) .......................................................................... 3-3
3.2.2 Enhanced Multiply Accumulate Module (EMAC) User Programming Model ............ 3-4
3.2.2.1 EMAC Instruction Set Summary .......................................................................... 3-4
3.2.3 Supervisor Programming Model ............................................................................... 3-5
3.2.3.1 Status Register (SR) ............................................................................................ 3-6
3.2.3.2 Vector Base Register (VBR) ................................................................................ 3-6
3.3 Exception Processing Overview ..................................................................................... 3-7
3.4 Exception Stack Frame Definition .................................................................................. 3-8
3.5 Processor Exceptions .................................................................................................... 3-9
3.5.1 Access Error Exception ............................................................................................. 3-9
3.5.2 Address Error Exception ......................................................................................... 3-10
3.5.3 Illegal Instruction Exception .................................................................................... 3-10
Table of Contents
SCF5250 User’s Manual, Rev. 4.1
Freescale Semiconductor TOC-3
3.5.4 Divide By Zero ........................................................................................................ 3-10
3.5.5 Privilege Violation ................................................................................................... 3-10
3.5.6 Trace Exception ...................................................................................................... 3-10
3.5.7 Debug Interrupt ....................................................................................................... 3-11
3.5.8 RTE and Format Error Exceptions .......................................................................... 3-11
3.5.9 TRAP Instruction Exceptions .................................................................................. 3-11
3.5.10 Interrupt Exception .................................................................................................. 3-11
3.5.11 Fault-on-Fault Halt .................................................................................................. 3-11
3.5.12 Reset Exception ...................................................................................................... 3-12
3.6 Instruction Execution Timing ........................................................................................ 3-12
3.6.1 Timing Assumptions ................................................................................................ 3-12
3.6.2 MOVE Instruction Execution Times ........................................................................ 3-13
3.7 Standard One Operand Instruction Execution Times ................................................... 3-14
3.8 Standard Two Operand Instruction Execution Times ................................................... 3-15
3.9 Miscellaneous Instruction Execution Times ................................................................. 3-16
3.10 Branch Instruction Execution Times ............................................................................. 3-18
SECTION 4
PHASE-LOCKED LOOP AND CLOCK DIVIDERS
4.1 PLL Features .................................................................................................................. 4-1
4.2 PLL Programming .......................................................................................................... 4-2
4.2.1 PLL Operation ........................................................................................................... 4-4
4.2.2 PLL Lock-in Time ...................................................................................................... 4-4
4.2.3 PLL Electrical Limits .................................................................................................. 4-4
4.3 Audio Clock Generation ................................................................................................. 4-4
4.4 Reduced Power Mode .................................................................................................... 4-5
4.5 Sleep / wake-up mode ................................................................................................... 4-6
4.6 Selecting Audio_Clock Input .......................................................................................... 4-6
4.7 Recommended Settings ................................................................................................. 4-6
SECTION 5
INSTRUCTION CACHE
5.1 Instruction Cache Features ............................................................................................ 5-1
5.2 Instruction Cache Physical Organization ....................................................................... 5-1
5.3 Instruction Cache Operation .......................................................................................... 5-2
5.3.1 Interaction with Other Modules ................................................................................. 5-2
5.3.2 Memory Reference Attributes ................................................................................... 5-3
5.3.3 Cache Coherency and Invalidation ........................................................................... 5-3
5.3.4 Reset ......................................................................................................................... 5-3
5.3.5 Cache Miss Fetch Algorithm/Line Fills ...................................................................... 5-3
5.4 Instruction Cache Programming Model .......................................................................... 5-5
5.4.1 Instruction Cache Registers Memory Map ................................................................ 5-5
5.4.2 Instruction Cache Register ........................................................................................ 5-5
5.4.2.1 Cache Control Register ....................................................................................... 5-5
5.4.2.2 Access Control Registers .................................................................................... 5-7
SCF5250 User’s Manual, Rev. 4.1
TOC-4 Freescale Semiconductor
SECTION 6
STATIC RAM (SRAM)
6.1 SRAM Features .............................................................................................................. 6-1
6.2 SRAM Operation ............................................................................................................ 6-1
6.1 SRAM Programming Model ........................................................................................... 6-1
6.3.1 SRAM Base Address Register .................................................................................. 6-1
6.3.2 SRAM Initialization .................................................................................................... 6-4
6.3.3 SRAM Initialization Code .......................................................................................... 6-4
6.3.4 Power Management .................................................................................................. 6-4
SECTION 7
SYNCHRONOUS DRAM CONTROLLER MODULE
7.1 SDRAM Features ........................................................................................................... 7-1
7.1.1 Definitions ................................................................................................................. 7-1
7.1.2 Block Diagram and Major Components .................................................................... 7-1
7.2 DRAM Controller Operation ........................................................................................... 7-3
7.2.1 DRAM Controller Registers ....................................................................................... 7-3
7.3 Synchronous Operation ................................................................................................. 7-3
7.3.1 DRAM Controller Signals in Synchronous Mode ...................................................... 7-4
7.3.2 Synchronous Register Set ........................................................................................ 7-5
4.3.2.1 DRAM Control Register (DCR) (Synchronous Mode) .......................................... 7-5
7.3.2.2 DRAM Address and Control (DACR0) (Synchronous Mode) .............................. 7-6
7.3.2.3 DRAM Controller Mask Registers (DMR0) .......................................................... 7-8
7.3.3 General Synchronous Operation Guidelines ............................................................ 7-9
7.3.3.1 Address Multiplexing ............................................................................................ 7-9
7.3.3.2 Interfacing Example ........................................................................................... 7-11
7.3.3.3 Burst Page Mode ............................................................................................... 7-11
7.3.3.4 Continuous Page Mode ..................................................................................... 7-13
7.3.3.5 Auto-Refresh Operation ..................................................................................... 7-15
7.3.3.6 Self-Refresh Operation ...................................................................................... 7-16
7.3.4 Initialization Sequence ............................................................................................ 7-17
7.3.4.1 Mode Register Settings ..................................................................................... 7-17
7.4 SDRAM Example ......................................................................................................... 7-19
7.4.1 SDRAM Interface Configuration .............................................................................. 7-19
7.4.2 DCR Initialization .................................................................................................... 7-19
7.4.3 DACR Initialization .................................................................................................. 7-20
7.4.4 DMR Initialization .................................................................................................... 7-21
7.4.5 Mode Register Initialization ..................................................................................... 7-22
7.4.6 Initialization Code .................................................................................................... 7-24
SECTION 8
BUS OPERATION
8.1 Bus Features .................................................................................................................. 8-1
8.2 Bus and Control Signals ................................................................................................. 8-1
8.2.1 Address Bus .............................................................................................................. 8-1
8.2.2 Read/Write control .................................................................................................... 8-2
8.2.3 Transfer Acknowledge (TA) ...................................................................................... 8-2
8.2.4 Data Bus ................................................................................................................... 8-2
8.2.5 Chip Selects ..............................................................................................................8-2
Table of Contents
SCF5250 User’s Manual, Rev. 4.1
Freescale Semiconductor TOC-5
8.2.6 Output Enable ........................................................................................................... 8-3
8.3 Clock and Reset Signals ................................................................................................ 8-3
8.3.1 Reset In ..................................................................................................................... 8-3
8.3.2 System Bus Clock Output ......................................................................................... 8-3
8.4 Bus Characteristics ........................................................................................................ 8-3
8.5 Data Transfer Operation ................................................................................................ 8-4
8.5.1 Bus Cycle Execution ................................................................................................. 8-5
8.5.2 Read Cycle ............................................................................................................... 8-6
8.5.3 Write Cycle ................................................................................................................ 8-8
8.5.4 Back-to-Back Bus Cycles ........................................................................................ 8-10
8.5.5 Burst Cycles ............................................................................................................ 8-10
8.5.5.1 Line Transfers .................................................................................................... 8-11
8.5.5.2 Line Read Bus Cycles ....................................................................................... 8-11
8.6 Misaligned Operands ................................................................................................... 8-14
8.7 Reset Operation ........................................................................................................... 8-15
8.7.1 Software Watchdog Reset ...................................................................................... 8-16
SECTION 9
SYSTEM INTEGRATION MODULE
9.1 SIM Introduction ............................................................................................................. 9-1
9.1.1 SIM Features ............................................................................................................ 9-1
9.2 Programming Model ....................................................................................................... 9-1
9.2.1 SIM Register Memory Map ....................................................................................... 9-1
9.3 SIM Programming and Configuration ............................................................................. 9-3
9.3.1 Module Base Address Registers ............................................................................... 9-3
9.3.2 Device ID .................................................................................................................. 9-5
9.3.3 Interrupt Controller .................................................................................................... 9-6
9.4 Interrupt Interface ........................................................................................................... 9-7
9.4.1 Primary controller Interrupt Registers ....................................................................... 9-7
9.4.1.1 Interrupt Mask Register ....................................................................................... 9-9
9.4.1.2 Interrupt Pending Register ................................................................................... 9-9
9.4.2 Secondary Interrupt Controller Registers ................................................................ 9-10
9.4.2.1 Interrupt Level Selection .................................................................................... 9-11
9.4.2.2 Interrupt Vector Generation ............................................................................... 9-11
9.4.2.3 Spurious Vector Register ................................................................................... 9-12
9.4.2.4 Secondary Interrupt Sources ............................................................................. 9-12
9.4.3 Software interrupts .................................................................................................. 9-14
9.4.4 Interrupt Monitor ...................................................................................................... 9-14
9.5 System Protection And Reset Status ........................................................................... 9-15
9.5.1 Reset Status Register ............................................................................................. 9-15
9.5.2 Software Watchdog Timer ...................................................................................... 9-16
9.5.2.1 System Protection Control Register ................................................................... 9-18
9.5.2.2 Software Watchdog Interrupt Vector Register ................................................... 9-19
9.5.2.3 Software Watchdog Service Register ................................................................ 9-19
9.6 CPU HALT Instruction .................................................................................................. 9-20
9.7 SCF5250 Bus Arbitration Control ................................................................................. 9-20
9.7.1 Default Bus Master Park Register ........................................................................... 9-20
9.7.1.1 Internal Arbitration Operation ............................................................................. 9-20
9.7.1.2 PARK Register Bit Configuration ....................................................................... 9-21
9.8 General Purpose I/Os .................................................................................................. 9-22
9.8.1 General Purpose Inputs .......................................................................................... 9-23
SCF5250 User’s Manual, Rev. 4.1
TOC-6 Freescale Semiconductor
9.8.1.1 General Purpose Input Interrupts ...................................................................... 9-24
9.8.2 General Purpose Outputs ....................................................................................... 9-25
9.9 Multiplexed PIn Configuration ...................................................................................... 9-27
SECTIO 10
CHIP-SELECT MODULE
10.1 Introduction .................................................................................................................. 10-1
10.1.1 Chip Select Features .............................................................................................. 10-1
10.2 Chip-Select Signals ...................................................................................................... 10-1
10.2.1 Chip Selects ............................................................................................................ 10-1
10.2.1.1 CS0/CS4 ............................................................................................................ 10-1
10.2.1.2 CS1/QSPI_CS3/GPIO28 ................................................................................... 10-1
10.2.1.3 CS2 - IDE-DIOR/GPIO31 and IDE-DIOW/GPIO32 ........................................... 10-2
10.2.1.4 CS3 ....................................................................................................................10-2
10.2.1.5 Output Enable OE .............................................................................................. 10-2
10.2.2 Buffer Enable Signals - BUFENB1 and BUFENB2 ................................................. 10-2
10.2.3. IDE-IORDY - Bus Termination Signal ..................................................................... 10-2
10.3 Chip-Select Operation .................................................................................................. 10-2
10.3.1 Chip-Select Module ................................................................................................. 10-2
10.3.1.1 General Chip Select Operation .......................................................................... 10-3
10.3.1.1.1 Port Sizing .................................................................................................... 10-3
10.3.1 Global Chip-Select Operation ................................................................................. 10-3
10.4 Programming Model ..................................................................................................... 10-4
10.4.1 Chip-Select Registers Memory Map ....................................................................... 10-4
10.4.2 Chip Select Module Registers ................................................................................. 10-5
10.4.2.1 Chip Select Address Register ............................................................................ 10-5
10.4.2.2 Chip Select Mask Register ................................................................................ 10-5
10.4.2.3 Chip Select Control Register ............................................................................. 10-7
10.4.2.4 Code example .................................................................................................... 10-8
SECTION 11
TIMER MODULE
11.1 Timer Module Overview ............................................................................................... 11-1
11.2 Timer Features .............................................................................................................11-1
11.3 Timer Signals ............................................................................................................... 11-1
11.3.1 Timer Output ........................................................................................................... 11-1
11.4 General-Purpose Timer Units ...................................................................................... 11-2
11.4.1 Selecting the Prescaler ........................................................................................... 11-2
11.4.2 Configuring the Timer for Reference Compare ....................................................... 11-3
11.4.3 Configuring the Timer for Output Mode (TIMER0) .................................................. 11-3
11.5 General-Purpose Timer Registers ............................................................................... 11-3
11.5.1 Timer Mode Registers (TMR0, TMR1) .................................................................... 11-3
11.5.2 Timer Reference Registers (TRR0, TRR1) ............................................................. 11-4
11.5.3 Timer Counters (TCN0, TCN1) ............................................................................... 11-5
11.5.4 Timer Event Registers (TER0, TER1) ..................................................................... 11-5
11.5.5 Timer Initialization Example Code .......................................................................... 11-6
11.5.5.1 Timer0 (Timer Mode Register) ........................................................................... 11-6
11.5.5.2 Timer0 (Timer Reference Register0) ................................................................. 11-6
Table of Contents
SCF5250 User’s Manual, Rev. 4.1
Freescale Semiconductor TOC-7
SECTION 12
ANALOG TO DIGITAL CONVERTER (ADC)
12.1 ADC Overview .............................................................................................................. 12-1
12.2 ADC Functionality ........................................................................................................ 12-2
12.2.1 ADC Measurement Operation ................................................................................. 12-2
12.2.2 Recommendations for set-up of ADC and external components. ........................... 12-4
SECTION 13
IDE AND FLASHMEDIA INTERFACE
13.1 IDE and SmartMedia Overview .................................................................................... 13-1
13.1.1 Buffer Enables BUFENB1, BUFENB2, and Associated Logic. ............................... 13-2
13.1.2 Generation of IDE-DIOR and IDE-DIOW ................................................................ 13-4
13.1.3 Cycle Termination on CS2 (IDE-DIOR, IDE-DIOW) ............................................... 13-5
13.2 SmartMedia Interface Setup ........................................................................................ 13-6
13.2.1 SmartMedia Timing ................................................................................................. 13-7
13.3 Setting Up the IDE Interface ........................................................................................ 13-8
13.3.1 IDE Timing Diagram ................................................................................................ 13-9
13.4 FlashMedia Interface .................................................................................................. 13-10
13.4.1 FlashMedia Interface Registers ............................................................................ 13-11
13.4.1.1 FlashMedia Clock Generation and Configuration ............................................ 13-11
13.4.2 FlashMedia Interface Operation ............................................................................ 13-12
13.4.2.1 FlashMedia Command Registers in MemoryStick Mode ................................. 13-13
13.4.2.2 FlashMedia Command Register 1 in Secure Digital Mode .............................. 13-13
13.4.2.3 FLASHMEDIA COMMAND REGISTER 2 in Secure Digital Mode .................. 13-14
13.4.3 FlashMedia Data Register .................................................................................... 13-14
13.4.3.1 FlashMedia Status Register ............................................................................. 13-15
13.4.4 FlashMedia Interrupt Interface .............................................................................. 13-15
13.4.5 FlashMedia Interface Operation in MemoryStick Mode ........................................ 13-16
13.4.5.1 Reading Data From the MemoryStick .............................................................. 13-16
13.4.5.2 Writing Data to the MemoryStick ..................................................................... 13-17
13.4.5.3 Interrupt From MemoryStick ............................................................................ 13-18
13.4.6 FlashMedia interface Operation in Secure Digital (SD) mode .............................. 13-19
13.4.6.1 Send Command To Card ................................................................................. 13-19
13.4.6.2 Write Data To Card .......................................................................................... 13-20
13.4.7 Commonly Used Commands in SD Mode ............................................................ 13-22
13.4.7.1 Send Command To Card (No Data) ................................................................ 13-22
13.4.7.2 Send Command To Card (Receive Multiple Data Blocks and Status) ............. 13-23
13.4.7.3 Send Command To Card (Write Multiple Data Blocks) ................................... 13-24
SECTION 14
DMA CONTROLLER MODULE
14.1 DMA Features .............................................................................................................. 14-1
14.2 DMA Signal Description ............................................................................................... 14-1
14.2.1 DMA Request .......................................................................................................... 14-2
14.3 DMA Module Overview ................................................................................................ 14-3
14.4 DMA Programming Model ............................................................................................ 14-4
14.4.1 REQUEST Source Selection .................................................................................. 14-6
14.4.2 Source Address Register ........................................................................................ 14-7
14.4.3 Destination ADDRESS Register ............................................................................. 14-8
SCF5250 User’s Manual, Rev. 4.1
TOC-8 Freescale Semiconductor
14.4.4 Byte Count Register ................................................................................................ 14-8
14.4.5 DMA Control Register ............................................................................................. 14-9
14.4.6 DMA Status Register ............................................................................................ 14-12
14.4.7 DMA Interrupt Vector Register .............................................................................. 14-14
14.5 Transfer Request Generation ..................................................................................... 14-14
14.5.1 Cycle-Steal Mode .................................................................................................. 14-14
14.5.2 Continuous Mode .................................................................................................. 14-14
14.6 Data Transfer Modes ................................................................................................. 14-14
14.6.1 Dual-Address Transaction .................................................................................... 14-14
14.6.1.1 Dual-Address Read ......................................................................................... 14-15
14.6.1.2 Dual-Address Write .......................................................................................... 14-15
14.7 DMA Transfer Functional Description ....................................................................... 14-15
14.7.1 Channel Initialization and Startup ......................................................................... 14-15
14.7.1.1 Channel Prioritization ....................................................................................... 14-15
14.7.1.2 Programming the DMA .................................................................................... 14-16
14.7.2 Data Transfer ........................................................................................................ 14-16
14.7.2.1 Periphery Request Operation .......................................................................... 14-16
14.7.2.2 Auto Alignment ................................................................................................ 14-17
14.7.2.3 Bandwidth Control ........................................................................................... 14-17
14.7.3 Channel Termination ............................................................................................. 14-17
14.7.3.1 Error Conditions ............................................................................................... 14-17
14.7.3.2 Interrupts .......................................................................................................... 14-17
SECTION 15
UART MODULES
15-1 Module Overview ......................................................................................................... 15-1
15.1.1 Serial Communication Channel .............................................................................. 15-2
15.1.2 Baud-Rate Generator/Timer ................................................................................... 15-2
15.1.3 Interrupt Control Logic ............................................................................................ 15-2
15.2 UART Module Signal Definitions .................................................................................. 15-3
15.2.1 Transmitter Serial Data Output ............................................................................... 15-3
15.2.2 Receiver Serial Data Input ...................................................................................... 15-3
15.2.3 Request-To-Send .................................................................................................... 15-4
15.2.4 Clear-To-Send ........................................................................................................ 15-4
15.3 Operation ..................................................................................................................... 15-4
15.3.1 Baud-Rate Generator/Timer ................................................................................... 15-4
15.3.2 Transmitter and Receiver Operating Modes ........................................................... 15-4
15.3.2.1 Transmitter ......................................................................................................... 15-5
15.3.2.2 Receiver ............................................................................................................. 15-6
16.3.2.3 Receiver FIFO ................................................................................................... 15-8
15.3.3 Looping Modes ....................................................................................................... 15-9
15.3.3.1 Automatic Echo Mode ........................................................................................ 15-9
15.3.3.2 Local Loopback Mode ........................................................................................ 15-9
15.3.3.3 Remote Loopback Mode .................................................................................... 15-9
15.3.4 Multidrop Mode ..................................................................................................... 15-10
15.3.5 Bus Operation ....................................................................................................... 15-12
15.3.5.1 Read Cycles .................................................................................................... 15-12
15.3.5.2 Write Cycles ..................................................................................................... 15-12
15.3.5.3 Interrupt Acknowledge Cycles ......................................................................... 15-12
15.4 Register Description and Programming ..................................................................... 15-12
15.4.1 Register Description .............................................................................................. 15-12
Table of Contents
SCF5250 User’s Manual, Rev. 4.1
Freescale Semiconductor TOC-9
15.4.1.1 Mode Register 1 (UMR1n) ............................................................................... 15-13
15.4.1.2 Mode Register 2 (UMR2n) ............................................................................... 15-15
15.4.1.3 Status Registers (USRn) ................................................................................. 15-17
15.4.1.4 Clock-Select Registers (USCRn) ..................................................................... 15-18
15.4.1.5 Command Registers (UCRn) ........................................................................... 15-19
15.4.1.6 Miscellaneous Commands ............................................................................... 15-19
15.4.1.6.1 Reset Mode Register Pointer ..................................................................... 15-20
15.4.1.6.2 Reset Receiver ........................................................................................... 15-20
15.4.1.6.3 Reset Transmitter ....................................................................................... 15-20
15.4.1.6.4 Reset Error Status ...................................................................................... 15-20
15.4.1.6.5 Reset Break-Change Interrupt .................................................................... 15-20
15.4.1.6.6 Start Break .................................................................................................. 15-20
15.4.1.6.7 Stop Break .................................................................................................. 15-20
15.4.1.7 Transmitter Commands ................................................................................... 15-20
15.4.1.7.1 No Action Taken ......................................................................................... 15-20
15.4.1.7.2 Transmitter Enable ..................................................................................... 15-21
15.4.1.7.3 Transmitter Disable .................................................................................... 15-21
15.4.1.7.4 Do Not Use ................................................................................................. 15-21
15.4.1.8 Receiver Commands ....................................................................................... 15-21
15.4.1.8.1 No Action Taken ......................................................................................... 15-21
15.4.1.8.2 Receiver Enable ......................................................................................... 15-21
15.4.1.8.3 Receiver Disable ........................................................................................ 15-21
15.4.1.8.4 Do Not Use ................................................................................................. 15-21
15.4.1.9 Receiver Buffer Registers (UBRn) ................................................................... 15-21
15.4.1.10 Transmitter Buffer Registers (UTBn) ............................................................... 15-22
15.4.1.11 Input Port Change Registers UIPCRn) ............................................................ 15-22
15.4.1.12 Auxiliary Control Registers (UACRn) ............................................................... 15-23
15.4.1.13 Interrupt Status Registers (UISRn) ................................................................. 15-23
15.4.1.14 Interrupt Mask Registers (UIMRn) ................................................................... 15-24
15.4.1.15 Baud Rate Generator (MSB) Register (UBG1n) .............................................. 15-25
15.4.1.16 Baud Rate Generator (LSB) Register (UBG2n) ............................................... 15-25
15.4.1.17 Interrupt Vector Registers (UIVRn) .................................................................. 15-25
15.4.1.18 Input Port Registers (UIPn) .............................................................................. 15-26
15.4.1.19 Output Port Data Registers (UOP1n) .............................................................. 15-26
15.4.2 Programming ........................................................................................................ 15-27
15.4.2.1 UART Module Initialization .............................................................................. 15-27
15.4.2.2 I/O Driver Example .......................................................................................... 15-27
15.4.2.3 Interrupt Handling ............................................................................................ 15-27
15.5 UART Module Initialization Sequence ........................................................................ 15-28
SECTION 16
QUEUED SERIAL PERIPHERAL INTERFACE (QSPI) MODULE
16.1 Overview ...................................................................................................................... 16-1
16.2 Module Description ...................................................................................................... 16-1
16.2.1 Interface and Pins ................................................................................................... 16-1
16.2.2 Internal Bus Interface .............................................................................................. 16-2
16.3 Operation ..................................................................................................................... 16-3
16.3.1 QSPI RAM .............................................................................................................. 16-4
16.3.1.1 Transmit RAM .................................................................................................... 16-5
16.3.1.2 Receive RAM ..................................................................................................... 16-5
16.3.1.3 Command RAM ................................................................................................. 16-5
SCF5250 User’s Manual, Rev. 4.1
TOC-10 Freescale Semiconductor
16.3.2 Baud Rate Selection ............................................................................................... 16-5
16.3.3 Transfer Delays ....................................................................................................... 16-6
16.3.4 Transfer Length ....................................................................................................... 16-7
16.3.5 Data Transfer .......................................................................................................... 16-7
16.4 Programming Model ..................................................................................................... 16-7
16.4.1 QSPI Mode Register (QMR) ................................................................................... 16-8
16.4.2 QSPI Delay Register (QDLYR) ............................................................................. 16-10
16.4.3 QSPI Wrap Register (QWR) ................................................................................. 16-10
16.4.4 QSPI Interrupt Register (QIR) ............................................................................... 16-11
16.4.5 QSPI Address Register (QAR) .............................................................................. 16-12
16.4.6 QSPI Data Register (QDR) ................................................................................... 16-13
16.4.7 Command RAM Registers (QCR0–QCR15) ......................................................... 16-13
16.4.8 Programming Example ......................................................................................... 16-15
SECTION 17
AUDIO FUNCTIONS
17.1 Audio Interface Overview ............................................................................................. 17-1
17.1.1 Audio Interface Structure ........................................................................................ 17-2
17.1.1.1 Audio Interrupt Mask and Interrupt Status Registers ......................................... 17-3
17.2 Serial Audio Interface (IIS/EIAJ) .................................................................................. 17-5
17.2.1 IIS/EIAJ Transmitter Descriptions ........................................................................... 17-9
17.2.2 IIS/EIAJ Transmitter Interrupts ................................................................................ 17-9
17.2.3 IIS/EIAJ Receiver Descriptions ............................................................................... 17-9
17.3 Digital Audio Interface (EBU / SPDIF) ........................................................................ 17-10
17.3.1 IEC958 Receive Interface ..................................................................................... 17-13
17.3.1.1 Audio Data Reception ...................................................................................... 17-13
17.3.1.2 Control Channel Reception .............................................................................. 17-13
17.3.1.3 Control Channel Interrupt (IEC958 “C” Channel New Frame) ......................... 17-13
17.3.1.4 Validity Flag Reception .................................................................................... 17-13
17.3.1.5 IEC958 Exception Definition ............................................................................ 17-14
17.3.1.6 EBU Extracted Clock ....................................................................................... 17-14
17.3.1.7 Reception of User Channel and CD-subcode Over IEC958 Receiver ............. 17-14
17.3.1.8 U and Q Receive Register Interrupts ............................................................... 17-16
17.3.1.9 Behavior of User Channel Receive Interface (CD Data) ................................. 17-16
17.3.1.10 Behavior of User Channel Receive Interface (non-CD data) ........................... 17-18
17.3.2 IEC958 (SPDIF) Transmit Interface ...................................................................... 17-18
17.3.2.1 Transmit “C” Channel ...................................................................................... 17-18
17.3.2.2 IEC958 Transmitter Interrupt Conditions ......................................................... 17-19
17.3.2.3 IEC958-3 Ed2 and Tech 3250-E Standards Compliance ................................ 17-19
17.3.2.4 Transmission of U-Channel and CD Subcode Data ........................................ 17-19
17.3.3 CD Subcode Interrupts ......................................................................................... 17-20
17.3.3.1 Free Running Counter Synchronization ........................................................... 17-21
17.3.3.2 Controlling the SFSY Sync Position ................................................................ 17-21
17.3.4 Inserting CD User Channel Data Into IEC958 Transmit Data ............................... 17-21
17.4 Processor Interface Overview .................................................................................... 17-22
17.4.1 Data Exchange Register Descriptions .................................................................. 17-22
17.4.2 Data Exchange Register Overview ....................................................................... 17-24
17.4.2.1 Data In Selection ............................................................................................. 17-24
17.4.3 PDIR and PDOR Field Formatting ........................................................................ 17-26
17.4.4 Overrun and Underrun with PDIR and PDOR Registers ...................................... 17-26
17.4.5 Automatic Resynchronization of FIFOs ................................................................ 17-27
Table of Contents
SCF5250 User’s Manual, Rev. 4.1
Freescale Semiconductor TOC-11
17.4.6 Audio Interrupts ..................................................................................................... 17-29
17.4.6.1 AudioTick Interrupts ......................................................................................... 17-29
17.4.6.2 PDIR1, PDIR2, and PDIR3, Interrupts ............................................................. 17-29
17.4.6.3 PDOR1, PDOR2, and PDOR3 Interrupts ........................................................ 17-29
17.4.6.4 Audio Interrupt Routines and Timing ............................................................... 17-31
17.4.7 CD-ROM Block Encoder and Decoder ................................................................. 17-32
17.4.7.1 CD-ROM Decoder Interrupts ........................................................................... 17-34
17.4.7.2 CD-ROM Encoder Interrupts ........................................................................... 17-35
17.5 DMA Channel Interaction ........................................................................................... 17-35
17.6 Phase/Frequency Determination and Xtrim Function ................................................ 17-36
17.6.1 Incoming Source Frequency Measurement .......................................................... 17-36
17.6.1.2 Filtering for the Discrete Time Oscillator .......................................................... 17-38
17.6.2 XTRIM Option - Locking Xtal Clock to Incoming Signal ........................................ 17-38
17.6.3 XTRIM Internal Logic ............................................................................................ 17-39
17.7 Audio Interface Memory Map ..................................................................................... 17-40
SECTION 18
I
2
C MODULES
18.1 I
2
C Overview ................................................................................................................ 18-1
18.2 I
2
C Interface Features .................................................................................................. 18-1
18.3 I
2
C System Configuration ............................................................................................. 18-2
18.4 I
2
C Protocol .................................................................................................................. 18-3
18.4.1 START Signal ......................................................................................................... 18-3
18.4.2 Slave Address Transmission .................................................................................. 18-3
18.4.3 Data Transfer .......................................................................................................... 18-4
18.4.4 Repeated START Signal ......................................................................................... 18-4
18.4.5 STOP Signal ........................................................................................................... 18-4
18.4.6 Arbitration Procedure .............................................................................................. 18-4
18.4.7 Clock Synchronization ............................................................................................ 18-4
18.4.8 Handshaking ........................................................................................................... 18-5
18.4.9 Clock Stretching ...................................................................................................... 18-5
18.5 Programming Model ..................................................................................................... 18-5
18.5.1 I
2
C Address Registers (MADR) .............................................................................. 18-6
18.5.2 I
2
C Frequency Divider Registers (MFDR) ............................................................... 18-6
18.5.3 I
2
C Control Registers (MBCR) ................................................................................ 18-8
18.5.4 I
2
C Status Registers (MBSR) .................................................................................. 18-9
18.5.5 I
2
C Data I/O Registers (MBDR) ............................................................................ 18-11
18.6 I
2
C Programming Examples ....................................................................................... 18-11
18.6.1 Initialization Sequence .......................................................................................... 18-11
18.6.2 Generation of START ........................................................................................... 18-12
18.6.3 Post-Transfer Software Response ........................................................................ 18-12
18.6.4 Slave Mode ........................................................................................................... 18-14
18.6.5 Arbitration Lost ...................................................................................................... 18-14
SECTION 19
BOOT ROM
19.1 General description ...................................................................................................... 19-1
19.1.1 Boot modes ............................................................................................................. 19-1
19.2 Boot ROM Operation .................................................................................................... 19-2
19.2.1 Initialization ............................................................................................................. 19-2
SCF5250 User’s Manual, Rev. 4.1
TOC-12 Freescale Semiconductor
19.2.1.1 Boot ROM Memory map .................................................................................... 19-2
19.2.1.2 Internal SRAM usage ......................................................................................... 19-2
19.2.2 Boot type detection ................................................................................................. 19-3
19.2.3 Serial Boot Data Format ......................................................................................... 19-3
19.2.3.1 Command Encoding / Size Encoding: ............................................................... 19-4
19.2.3.2 Supported Commands: ...................................................................................... 19-4
19.2.4 IDE Boot DATA FORMAT ....................................................................................... 19-4
19.2.5 Boot modes ............................................................................................................. 19-5
19.2.5.1 Boot from I
2
C / SPI – master mode ................................................................... 19-5
19.2.5.2 Boot from I
2
C - slave mode ............................................................................... 19-6
19.2.5.3 Boot from UART ................................................................................................ 19-6
19.2.5.3.1 UART Protocol .............................................................................................. 19-6
19.2.5.4 Boot from IDE device ......................................................................................... 19-6
19.3 Creating appropriate Boot record files ......................................................................... 19-7
SECTION 20
DEBUG SUPPORT
20.1 Breakpoint (BKPT) ....................................................................................................... 20-1
20.1.1 Debug Support Signals ........................................................................................... 20-1
20.1.2 Debug Data (DDATA[3:0]) ...................................................................................... 20-2
20.1.3 Development Serial Clock (DSCLK) ....................................................................... 20-2
20.1.4 Development Serial Input (DSI) .............................................................................. 20-2
20.1.5 Development Serial Output (DSO) .......................................................................... 20-2
20.1.6 Processor Status (PST[2:0]) ................................................................................... 20-2
20.1.7 Processor Status Clock (PSTCLK) ......................................................................... 20-3
20.2 Real-Time Trace SUPPORT ........................................................................................ 20-4
20.2.1 Processor Status Signal Encoding .......................................................................... 20-4
20.2.1.1 Continue Execution (PST = $0) ......................................................................... 20-4
20.2.1.2 Begin Execution of an Instruction (PST = $1) .................................................... 20-4
20.2.1.3 Entry into User Mode (PST = $3) ....................................................................... 20-4
20.2.1.4 Begin Execution of PULSE or WDDATA Instructions (PST = $4) ..................... 20-4
20.2.1.5 Begin Execution of Taken Branch (PST = $5) ................................................... 20-5
20.2.1.6 Begin Execution of RTE Instruction (PST = $7) ................................................. 20-6
20.2.1.7 Begin Data Transfer (PST = $8–$B) .................................................................. 20-6
20.2.1.9 Exception Processing (PST = $C) ..................................................................... 20-6
20.2.1.10 Emulator Mode Exception Processing (PST = $D) ............................................ 20-6
20.2.1.11 Processor Stopped (PST = $E) ......................................................................... 20-6
20.2.1.12 Processor Halted (PST = $F) ............................................................................. 20-6
20.3 Background-Debug Mode (BDM) ................................................................................. 20-6
20.3.1 CPU Halt .................................................................................................................20-7
20.3.2 BDM Serial Interface ............................................................................................... 20-8
20.3.2.1 Receive Packet Format ..................................................................................... 20-8
20.3.2.2 Transmit Packet Format .................................................................................... 20-9
20.3.3 BDM Command Set ................................................................................................ 20-9
20.3.3.1 BDM Command Set Summary ........................................................................ 20-10
20.3.3.2 ColdFire BDM Commands ............................................................................... 20-11
20.3.4 Command Sequence Diagram .............................................................................. 20-12
20.3.4.1 Command Set Descriptions ............................................................................. 20-13
20.3.4.1.1 Read Address/Data Register (RAREG/RDREG) ........................................ 20-13
20.3.4.1.2 Write Address/Data Register (WAREG and WDREG) ............................... 20-14
20.3.4.1.3 Read Memory Location (READ) ................................................................. 20-15
Table of Contents
SCF5250 User’s Manual, Rev. 4.1
Freescale Semiconductor TOC-13
20.3.4.1.4 Write Memory Location (WRITE) ................................................................ 20-16
20.3.4.1.5 Dump Memory Block (DUMP) .................................................................... 20-17
20.3.4.1.6 Fill Memory Block (FILL) ............................................................................. 20-19
20.3.4.1.7 Resume Execution (GO) ............................................................................ 20-21
20.3.4.1.8 No Operation (NOP) ................................................................................... 20-21
20.3.4.1.9 Read Control Register (RCREG) ................................................................ 20-22
20.3.4.1.10 Write Control Register (WCREG) ............................................................... 20-23
20.3.4.1.11 Read Debug Module Register (RDMREG) ................................................. 20-24
20.3.4.1.12 Write Debug Module Register (WDMREG) ................................................ 20-25
20.3.4.1.13 Unassigned Opcodes ................................................................................. 20-26
20.3.4.2 BDM Accesses of the EMAC Registers ........................................................... 20-26
20.4 Real-Time Debug Support ......................................................................................... 20-27
20.4.1 Theory of Operation .............................................................................................. 20-27
20.4.1.1 Emulator Mode ................................................................................................ 20-28
20.4.1.2 Debug Module Hardware ................................................................................. 20-29
20.4.1.2.1 Reuse of Debug Module Hardware (Rev. A) .............................................. 20-29
20.4.2 Programming Model .............................................................................................. 20-29
20.4.2.1 Address Breakpoint Registers ......................................................................... 20-30
20.4.2.1.1 Address Attribute Trigger Register ............................................................. 20-31
20.4.2.2 Program Counter Breakpoint Register (PBR, PBMR) ..................................... 20-32
20.4.2.3 Data Breakpoint Registers (DBR, DBMR) ....................................................... 20-33
20.4.2.4 Trigger Definition Register (TDR) .................................................................... 20-34
20.4.2.5 Configuration/Status Register (CSR) ............................................................... 20-36
20.4.2.6 BDM Address Attribute (BAAR) ....................................................................... 20-39
20.4.3 Concurrent BDM and Processor Operation .......................................................... 20-40
20.4.4 Freescale-Recommended BDM Pinout ................................................................ 20-40
SECTION 21
IEEE 1149.1 TEST ACCESS PORT (JTAG)
21.1 JTAG Overview ............................................................................................................ 21-1
21.2 JTAG Signal Descriptions ........................................................................................... 21-2
21.2.1 Test Clock - (TCK) .................................................................................................. 21-3
21.2.2 Test Reset/Development Serial Clock - (TRST/DSCLK) ........................................ 21-3
21.2.3 Test Mode Select/ Breakpoint (TMS/BKPT) ........................................................... 21-3
21.2.4 Test Data Input/Development Serial Input - (TDI/DSI) ............................................ 21-4
21.2.5 Test Data Output/Development Serial Output - (TDO/DSO) .................................. 21-4
21.3 TAP Controller .............................................................................................................. 21-4
21.4 JTAG Registers ............................................................................................................ 21-6
21.4.1 JTAG Instruction Shift Register .............................................................................. 21-6
21.4.1.1 EXTEST Instruction ........................................................................................... 21-6
21.4.1.2 IDCODE ............................................................................................................. 21-6
21.4.1.3 SAMPLE/PRELOAD Instruction ........................................................................ 21-7
21.4.1.4 CLAMP Instruction ............................................................................................. 21-7
21.4.1.5 HIGHZ Instruction .............................................................................................. 21-7
21.4.1.6 BYPASS Instruction ........................................................................................... 21-7
21.4.2 IDcode Register ...................................................................................................... 21-8
21.4.3 JTAG Boundary Scan Register ............................................................................... 21-8
21.4.4 JTAG Bypass Register ............................................................................................ 21-9
21.5 Restrictions .................................................................................................................. 21-9
21.6 Disabling IEEE 1149.1A Standard Operation .............................................................. 21-9
21.7 SCF5250 BSDL File: 144 LQFP ................................................................................. 21-11
SCF5250 User’s Manual, Rev. 4.1
TOC-14 Freescale Semiconductor
21.8 SCF5250 BSDL File: 196 MAPBGA ........................................................................... 21-24
21.9 Obtaining the IEEE 1149.1A Standard ....................................................................... 21-38
SECTION 22
ELECTRICAL SPECIFICATIONS
22.1 IIS Module AC Timing Specifications ......................................................................... 22-17
SECTION 23
MECHANICAL DATA
23.1 144 QFP Package ........................................................................................................ 23-1
23.2 144 QFP Pin Assignments ........................................................................................... 23-5
23.3 196 MAPBGA Package............................................................................................... 23-11
23.4 196 MAPBGA Pin Assignments .................................................................................. 23-14
SCF5250 User’s Manual, Rev. 4.1
Freescale Semiconductor LOF-1
LIST OF FIGURES
Figure 1-1 SCF5250 Block Diagram ................................................................................................1-2
Figure 3-1 V2 ColdFire Processor Core Pipelines ........................................................................... 3-1
Figure 3-2 User Programming Model .............................................................................................. 3-3
Figure 3-3 Supervisor Programming Model ..................................................................................... 3-5
Figure 3-4 Vector Base Register (VBR) .......................................................................................... 3-6
Figure 3-5 Exception Stack Frame Form ......................................................................................... 3-8
Figure 4-1 Phase-Locked Loop Module Block Diagram .................................................................. 4-1
Figure 5-1 Instruction Cache Block Diagram ................................................................................... 5-2
Figure 7-1 Synchronous DRAM Controller Block Diagram .............................................................. 7-2
Figure 7-2 SCF5250 SDRAM Interface ........................................................................................... 7-4
Figure 7-3 DRAM Control Register (DCR) (Synchronous Mode) .................................................... 7-5
Figure 7-4 DACR0 (Synchronous Mode) ......................................................................................... 7-6
Figure 7-5 DRAM Controller Mask Registers (DMR0) ..................................................................... 7-8
Figure 7-6 Burst Read SDRAM Access ......................................................................................... 7-12
Figure 7-7 Burst Write SDRAM Access ......................................................................................... 7-13
Figure 7-8 Synchronous, Continuous Page-Mode Access—Consecutive Reads ......................... 7-14
Figure 7-9 Synchronous, Continuous Page-Mode Access—Read after Write .............................. 7-15
Figure 7-10 Auto-Refresh Operation ............................................................................................... 7-16
Figure 7-11 Self-Refresh Operation ................................................................................................ 7-17
Figure 7-12 Mode Register Set (mrs) Command ............................................................................ 7-18
Figure 7-13 Initialization Values for DCR ........................................................................................ 7-19
Figure 7-14 SDRAM Configuration .................................................................................................. 7-20
Figure 7-15 DACR Register Configuration ...................................................................................... 7-21
Figure 7-16 DMR0 Register ............................................................................................................. 7-22
Figure 7-17 Mode Register Mapping to SCF5250 A[31:0] .............................................................. 7-23
Figure 8-1 Signal Relationship to BCLK for Non-DRAM Access ..................................................... 8-4
Figure 8-2 Connections for External Memory Port Sizes ................................................................ 8-5
Figure 8-3 Read Cycle Flowchart .................................................................................................... 8-7
Figure 8-4 Basic Read Bus Cycle .................................................................................................... 8-7
Figure 8-5 Write Cycle Flowchart .................................................................................................... 8-9
Figure 8-6 Basic Write Bus Cycle .................................................................................................... 8-9
Figure 8-7 Back-to-Back Bus Cycle ...............................................................................................8-10
Figure 8-8 Line Read Burst (one wait cycle) ................................................................................. 8-11
Figure 8-9 Line Read Burst (no wait cycles)Line Write Bus Cycles .............................................. 8-12
Figure 8-10 Line Read Burst-Inhibited ............................................................................................. 8-12
Figure 8-11 Line Write Burst (no wait cycles ................................................................................... 8-13
Figure 8-12 Line Write Burst with One Wait State ........................................................................... 8-13
Figure 8-13 Line Write Burst-Inhibited ............................................................................................. 8-14
Figure 8-14 Misaligned Longword Transfer ..................................................................................... 8-15
Figure 8-15 Misaligned Word Transfer ............................................................................................8-15
Figure 8-16 Master Reset Timing .................................................................................................... 8-16
Figure 9-1 SCF5250 Unterminated Access Recovery ................................................................... 9-17
Figure 9-2 General-Purpose Pin Logic for Pin SCLK3/GPIO35 .................................................... 9-26
Figure 11-1 Timer Block Diagram Module Operation ...................................................................... 11-2
Figure 12-1 ADC Convertor Block Diagram and External Components .......................................... 12-2
Figure 13-1 Bus Setup with IDE and SmartMedia Interface ............................................................ 13-1
SCF5250 User’s Manual, Rev. 4.1
LOF-2 Freescale Semiconductor
Figure 13-2 Buffer Enables (BUFENB1 and BUFENB2) ................................................................. 13-2
Figure 13-3 DIOR Timing Diagram .................................................................................................. 13-5
Figure 13-4 Non-IORDY Controlled IDE/SmartMedia TA Timing .................................................... 13-6
Figure 13-5 CS2 (IDE-DIOR, IDE-DIOW) ........................................................................................ 13-6
Figure 13-6 SmartMedia Timing ...................................................................................................... 13-7
Figure 13-7 IDE Timing ................................................................................................................... 13-9
Figure 13-8 FlashMedia Block Diagram ........................................................................................ 13-10
Figure 13-9 Shift Register .............................................................................................................. 13-12
Figure 13-10 Reading Data From MemoryStick .............................................................................. 13-16
Figure 13-11 Reading Data From MemoryStick Timing .................................................................. 13-17
Figure 13-12 Writing Data To MemoryStick .................................................................................... 13-17
Figure 13-13 Writing Data to MemoryStick Timing .......................................................................... 13-18
Figure 13-14 Interrupt From MemoryStick ....................................................................................... 13-18
Figure 13-15 Interrupt From MemoryStick ....................................................................................... 13-19
Figure 13-16 Send Command To Card ........................................................................................... 13-19
Figure 13-17 Writing To Card With Busy ......................................................................................... 13-20
Figure 13-18 Writing To Card Without Busy .................................................................................... 13-21
Figure 13-19 Read Data From Card ................................................................................................ 13-22
Figure 14-1 DMA Signal Diagram. ................................................................................................... 14-2
Figure 14-2 Dual Address Transfer ................................................................................................. 14-4
Figure 15-1 UART Block Diagram ................................................................................................... 13-1
Figure 15-2 External and Internal Interface Signals ........................................................................ 13-3
Figure 15-3 Baud-Rate Timer Generator Diagram .......................................................................... 13-4
Figure 15-4 Transmitter and Receiver Functional Diagram ............................................................. 13-5
Figure 15-5 Transmitter Timing Diagram ......................................................................................... 13-6
Figure 15-6 Receiver Timing Diagram .............................................................................................13-7
Figure 15-7 Looping Modes Functional Diagram .......................................................................... 13-10
Figure 15-8 Multidrop Mode Timing Diagram ................................................................................ 13-11
Figure 15-9 UART Software Flowchart (1 of 5) ............................................................................. 13-29
Figure 15-10 UART Software Flowchart (2 of 5) ............................................................................. 13-30
Figure 15-11 UART Software Flowchart (3 of 5) ............................................................................. 13-31
Figure 15-12 UART Software Flowchart (4 of 5) ............................................................................. 13-32
Figure 15-13 UART Software Flowchart (5 of 5) ............................................................................. 13-33
Figure 16-1 QSPI Block Diagram .................................................................................................... 16-2
Figure 16-2 QSPI RAM Model ......................................................................................................... 16-4
Figure 16-3 QSPI Mode Register (QMR) ........................................................................................ 16-8
Figure 16-4 QSPI Clocking and Data Transfer Example ................................................................. 16-9
Figure 16-5 QSPI Delay Register (QDLYR) .................................................................................. 16-10
Figure 16-6 QSPI Wrap Register (QWR) ...................................................................................... 16-10
Figure 16-7 QSPI Interrupt Register (QIR) .................................................................................... 16-11
Figure 16-8 QSPI Address Register (QAR) ................................................................................... 16-13
Figure 16-9 QSPI Data Register (QDR) ........................................................................................ 16-13
Figure 16-10 Command RAM Registers (QCR0–QCR15) .............................................................. 16-13
Figure 16-11 QSPI Timing ............................................................................................................... 16-15
Figure 17-1 Audio Interface Block Diagram ..................................................................................... 17-2
Figure 17-2 IIS/EIAJ Timing Diagram (16 SCLK edges per word) .................................................. 17-9
Figure 17-3 IIS/EIAJ Timing Diagram (24 or 32 SCLK edges per word) ....................................... 17-10
Figure 17-4 CD-Subcode Interface ................................................................................................ 17-19
Figure 17-5 Data Format on CD-Subcode Interface Out ............................................................... 17-20
Figure 17-6 Processor/Audio Module Interface ............................................................................. 17-22
Figure 17-7 Automatic Resynchronization FSM of left-right FIFOs ............................................... 17-27
Figure 17-8 Audio Transmit / Receive FIFOs ................................................................................ 17-32
List of Figures
SCF5250 User’s Manual, Rev. 4.1
Freescale Semiconductor LOF-3
Figure 17-9 Block Decoder ............................................................................................................ 17-34
Figure 17-10 Block Encoder ............................................................................................................ 17-35
Figure 17-11 Frequency Measurement Circuit ................................................................................ 17-37
Figure 17-12 XTRIM External Circuit ............................................................................................... 17-39
Figure 17-13 PDM Modulator Used on Xtrim Output ....................................................................... 17-39
Figure 18-1 I
2
C Module Block Diagram ........................................................................................... 18-2
Figure 18-2 I
2
C Standard Communication Protocol ........................................................................ 18-3
Figure 18-3 Synchronized Clock SCL ............................................................................................. 18-5
Figure 18-4 Flow-Chart of Typical I2C Interrupt Routine ............................................................... 18-15
Figure 19-1 I
2
C Master Boot Mode .................................................................................................. 19-5
Figure 19-2 Boot Loader IDE Interface ............................................................................................ 19-7
Figure 20-1 Processor/Debug Module Interface .............................................................................. 20-1
Figure 20-2 Example PST/DDATA Diagram ................................................................................... 20-5
Figure 20-3 1BDM Serial Transfer ................................................................................................... 20-8
Figure 20-4 Command Sequence Diagram ................................................................................... 20-12
Figure 20-5 Command/Result Formats ......................................................................................... 20-13
Figure 20-6 Read A/D Register Command Sequence .................................................................. 20-14
Figure 20-7 Write A/D Register Command Sequence ................................................................... 20-14
Figure 20-8 WAREG/WDREG Command Format ......................................................................... 20-15
Figure 20-9 READ Command/Result Format ................................................................................ 20-15
Figure 20-10 Read Memory Location Command Sequence ........................................................... 20-16
Figure 20-11 Write Memory Location Command Sequence ........................................................... 20-17
Figure 20-12 DUMP Command/Result Format ............................................................................... 20-18
Figure 20-13 DUMP Memory Block Command Sequence .............................................................. 20-19
Figure 20-14 Fill Memory Block Command Sequence .................................................................... 20-20
Figure 20-15 Resume Execution ..................................................................................................... 20-21
Figure 20-16 No Operation Command Sequence ........................................................................... 20-22
Figure 20-17 RCREG Command/Result Formats ........................................................................... 20-22
Figure 20-18 WCREG Command Sequence ................................................................................... 20-23
Figure 20-19 Write Control Register Command Sequence ............................................................. 20-23
Figure 20-20 RDMREG Command/Result Formats ........................................................................ 20-24
Figure 20-21 Read Debug Module Register Command Sequence ................................................. 20-24
Figure 20-22 WDMREG BDM Command Format ........................................................................... 20-25
Figure 20-23 Write Debug Module Register Command Sequence ................................................. 20-26
Figure 20-24 Read Control Register Command Sequence ............................................................. 20-27
Figure 20-25 Debug Programming Mode ........................................................................................ 20-30
Figure 20-26 Recommended BDM Connector ................................................................................ 20-41
Figure 21-1 JTAG Test Logic Block Diagram .................................................................................. 21-2
Figure 21-2 JTAG TAP Controller State Machine ........................................................................... 21-5
Figure 21-3 Disabling JTAG in JTAG Mode .................................................................................... 21-9
Figure 21-4 Disabling JTAG in Debug Mode ................................................................................. 21-10
Figure 22-1 Clock Timing Definition ................................................................................................ 22-4
Figure 22-2 Input/Output Timing Definition-1 .................................................................................. 22-7
Figure 22-3 Input/Output Timing Definition-II .................................................................................. 22-8
Figure 22-4 Debug Timing Definition ............................................................................................... 22-9
Figure 22-5 Timer Module Timing Definition ................................................................................. 22-10
Figure 22-6 UART Timing Definition .............................................................................................. 22-11
Figure 22-7 I2C Timing Definition .................................................................................................. 22-13
Figure 22-8 I2C and System Clock Timing Relationship ............................................................... 22-14
Figure 22-9 General-Purpose Parallel Port Timing Definition ....................................................... 22-15
Figure 22-10 JTAG Timing .............................................................................................................. 22-16
Figure 22-11 SCLK Input, SDATA Output Timing ........................................................................... 22-17
SCF5250 User’s Manual, Rev. 4.1
LOF-4 Freescale Semiconductor
Figure 22-12 SCLK Output, SDATAO Output Timing Diagram ....................................................... 22-17
Figure 22-13 SCLK Input/Output, SDATAI Input Timing Diagram ................................................... 22-18
Figure 23-1 144 QFP Package (1 of 3) ........................................................................................... 23-2
Figure 23-2 144 QFP Package (2 of 3) ........................................................................................... 23-3
Figure 23-3 144 QFP Package (3 of 3) ........................................................................................... 23-4
Figure 23-4 196 MAPBGA Package (1 of 2) .................................................................................. 23-12
Figure 23-5 196 MAPBGA Package (2 of 2) .................................................................................. 23-13
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
-
1
-
2
-
3
-
4
-
5
-
6
-
7
-
8
-
9
-
10
-
11
-
12
-
13
-
14
-
15
-
16
-
17
-
18
-
19
-
20
-
21
-
22
-
23
-
24
-
25
-
26
-
27
-
28
-
29
-
30
-
31
-
32
-
33
-
34
-
35
-
36
-
37
-
38
-
39
-
40
-
41
-
42
-
43
-
44
-
45
-
46
-
47
-
48
-
49
-
50
-
51
-
52
-
53
-
54
-
55
-
56
-
57
-
58
-
59
-
60
-
61
-
62
-
63
-
64
-
65
-
66
-
67
-
68
-
69
-
70
-
71
-
72
-
73
-
74
-
75
-
76
-
77
-
78
-
79
-
80
-
81
-
82
-
83
-
84
-
85
-
86
-
87
-
88
-
89
-
90
-
91
-
92
-
93
-
94
-
95
-
96
-
97
-
98
-
99
-
100
-
101
-
102
-
103
-
104
-
105
-
106
-
107
-
108
-
109
-
110
-
111
-
112
-
113
-
114
-
115
-
116
-
117
-
118
-
119
-
120
-
121
-
122
-
123
-
124
-
125
-
126
-
127
-
128
-
129
-
130
-
131
-
132
-
133
-
134
-
135
-
136
-
137
-
138
-
139
-
140
-
141
-
142
-
143
-
144
-
145
-
146
-
147
-
148
-
149
-
150
-
151
-
152
-
153
-
154
-
155
-
156
-
157
-
158
-
159
-
160
-
161
-
162
-
163
-
164
-
165
-
166
-
167
-
168
-
169
-
170
-
171
-
172
-
173
-
174
-
175
-
176
-
177
-
178
-
179
-
180
-
181
-
182
-
183
-
184
-
185
-
186
-
187
-
188
-
189
-
190
-
191
-
192
-
193
-
194
-
195
-
196
-
197
-
198
-
199
-
200
-
201
-
202
-
203
-
204
-
205
-
206
-
207
-
208
-
209
-
210
-
211
-
212
-
213
-
214
-
215
-
216
-
217
-
218
-
219
-
220
-
221
-
222
-
223
-
224
-
225
-
226
-
227
-
228
-
229
-
230
-
231
-
232
-
233
-
234
-
235
-
236
-
237
-
238
-
239
-
240
-
241
-
242
-
243
-
244
-
245
-
246
-
247
-
248
-
249
-
250
-
251
-
252
-
253
-
254
-
255
-
256
-
257
-
258
-
259
-
260
-
261
-
262
-
263
-
264
-
265
-
266
-
267
-
268
-
269
-
270
-
271
-
272
-
273
-
274
-
275
-
276
-
277
-
278
-
279
-
280
-
281
-
282
-
283
-
284
-
285
-
286
-
287
-
288
-
289
-
290
-
291
-
292
-
293
-
294
-
295
-
296
-
297
-
298
-
299
-
300
-
301
-
302
-
303
-
304
-
305
-
306
-
307
-
308
-
309
-
310
-
311
-
312
-
313
-
314
-
315
-
316
-
317
-
318
-
319
-
320
-
321
-
322
-
323
-
324
-
325
-
326
-
327
-
328
-
329
-
330
-
331
-
332
-
333
-
334
-
335
-
336
-
337
-
338
-
339
-
340
-
341
-
342
-
343
-
344
-
345
-
346
-
347
-
348
-
349
-
350
-
351
-
352
-
353
-
354
-
355
-
356
-
357
-
358
-
359
-
360
-
361
-
362
-
363
-
364
-
365
-
366
-
367
-
368
-
369
-
370
-
371
-
372
-
373
-
374
-
375
-
376
-
377
-
378
-
379
-
380
-
381
-
382
-
383
-
384
-
385
-
386
-
387
-
388
-
389
-
390
-
391
-
392
-
393
-
394
-
395
-
396
-
397
-
398
-
399
-
400
-
401
-
402
-
403
-
404
-
405
-
406
-
407
-
408
-
409
-
410
-
411
-
412
-
413
-
414
-
415
-
416
-
417
-
418
-
419
-
420
-
421
-
422
-
423
-
424
-
425
-
426
-
427
-
428
-
429
-
430
-
431
-
432
-
433
-
434
-
435
-
436
-
437
-
438
-
439
-
440
-
441
-
442
-
443
-
444
-
445
-
446
-
447
-
448
-
449
-
450
-
451
-
452
-
453
-
454
-
455
-
456
-
457
-
458
-
459
-
460
-
461
-
462
-
463
-
464
-
465
-
466
-
467
-
468
-
469
-
470
-
471
-
472
NXP MCF525X User guide
- Type
- User guide
Ask a question and I''ll find the answer in the document
Finding information in a document is now easier with AI
Related papers
Other documents
-
Hitachi SH7095 Hardware User Manual
-
Freescale Semiconductor MCF52100 Reference guide
-
-
-
Panasonic MN103001G/F01K User manual
-
Motorola ColdFire MCF5282 User manual
-
hyperstone E1-16XS User manual
-
Nortek Contol WOR User manual
-
-
Intel 80C188XL User manual
