EB-GS2962
Evaluation Board User Guide
52138 - 2 February 2013
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Revision History
Contents
Revision History .................................................................................................................................................2
Overview ..............................................................................................................................................................3
1. Board User Guide ..........................................................................................................................................4
1.1 Power (J1) ............................................................................................................................................4
1.2 Switch Settings (SW8) ......................................................................................................................4
1.3 Inputs ....................................................................................................................................................6
1.3.1 Parallel Video Input .............................................................................................................6
1.4 SDI Outputs (J3 and J4) ...................................................................................................................6
1.5 Control and Status ............................................................................................................................6
1.5.1 GSPI Header (JP8) .................................................................................................................6
1.5.2 JTAG Header (JP1) ................................................................................................................6
1.5.3 Lock Status..............................................................................................................................6
1.6 Modes of Operation .........................................................................................................................7
2. Board Schematics ..........................................................................................................................................8
2.1 Top Level Schematic ........................................................................................................................8
2.2 GS2962 Schematic ............................................................................................................................9
2.3 Power Schematic ........................................................................................................................... 10
3. Board Layout................................................................................................................................................ 11
4. Bill of Materials............................................................................................................................................ 14
Version ECO Date Changes and / or Modifications
2 011325 February 2013
Corrected pins D5 and F7 in Figure 2-2:
GS2962 Schematic, and changed to Semtech
template.
1 153835 March 2010
Changed R1 to 200Ω in Figure 2-2: GS2962
Schematic and Section 4. Bill of Materials.
0 151475 February 2009 New document.
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Overview
Together with the EB-GS2962 Evaluation Board, this document serves as a guide for
evaluating the GS2962, a Semtech 3Gb/s, HD, SD SDI Transmitter. This document
contains four main sections:
1. Evaluation Board User Guide.
2. Evaluation Board Schematics.
3. Evaluation Board Layout.
4. Evaluation Board Bill of Materials.
The figure below shows a block diagram of the features and the functions of the
EB-GS2962.
The board includes a power supply, 2 SDI output ports, a GS2962 Transmitter, a parallel
video input connector, a JTAG/GSPI header, a dip switch and some status indicator
LEDs.
The GS2962 can be configured in SD-SDI, HD-SDI, 3G-SDI or DVB-ASI mode. This may
be selected manually through a DIP switch. The serialized video is available on the SDI
output BNC connectors.
The EB-GS2962 also provides a JTAG interface and access to the GS2962’s internal
registers via GSPI and USB. A GSPI dongle is included in the kit, to communicate with the
GS2962 through a USB connection.The GSPI dongle has the provision to control and
monitor an additional EB-GS2960 board connected to the EB-GS2962.
Block Diagram of the EB-GS2962
SDO
SDO
3G-SDI
3G-SDI
GS2962
(Transmitter)
Parallel
Video I/P
20-bit Video
Power
FVH/PCLK
Control
& Status
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1. Board User Guide
Figure 1-1 shows the inputs, outputs and power connections for the EB-GS2962.
Figure 1-1: GS2962 Evaluation Board (EB-GS2962)
1.1 Power (J1)
The EB-GS2962 requires a single +5V DC power supply. The board is powered through
J1, or through J29 from the EB-GS2960 board.
LED (D7) indicates the power on/off state of the board.
Through the use of JP7, the user can select the I/O voltage to be either 1.8V or 3.3V.
If the EB-GS2962 and the EB-GS2960 are connected together, one supply will power
both boards. Therefore, the +5V DC power is only required on either the EB-GS2962 or
the EB-GS2960.
1.2 Switch Settings (SW8)
A DIP switch (SW8) is populated on the board with each bit labelled on the silk-screen.
They are used to set the operation mode of GS2962.
Note: Some signals are active LOW so that you will need to switch the bit OFF to activate
the signal.
Refer to the GS2962 Data Sheet for definitions of each bit.
Power Supply Connector (J1)
Parallel Video Input Connector (J25)
DIP Switch (SW8)
H, V & F Timing Signals Connector (J27)
GSPI Connector for Interface
with the GS2960 Receiver (J29),
as well as a 5V power connection
for the GS2960.
GSPI Header (JP8)
JTAG Header (JP1)
SDI Outputs (J3 & J4)
1.8V/3.3V Jumper (JP7)
Power Status LED (D7)
Lock Status LED (U25)
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Table 1-1: SW8 Settings
Bit Name Description
TIM861 Connected to the GS2962 TIM_861 pin. Used to select external CEA-861 timing mode.
SMPTE_BYPASSn
Connected to the GS2962 SMPTE_BYPASS
pin. Used to enable/disable all forms of encoding/decoding,
scrambling and EDH insertion.
When set LOW, the device operates in Data Through mode (DVB_ASI= LOW), or in DVB_ASI mode (DVB_ASI =
HIGH). No SMPTE scrambling takes place and none of the I/O processing features of the device are available
when SMPTE_BYPASS
is set LOW.
When set HIGH, the device carries out SMPTE scrambling and I/O processing.
DVB_ASI
Connected to the GS2962 DVB_ASI pin. Used to enable/disable the DVB-ASI data transmission.
When set HIGH, the device will carry out DVB_ASI, word-alignment, I/O processing and transmission. The
SMPTE_BYPASS
pin must be set LOW.
When SMPTE_BYPASS
and DVB_ASI are both set LOW, the device operates in data-through mode.
RATE_SEL0,
RATE_SEL1
Connected to the GS2962 RATE_SEL0 and RATE_SEL1 pins. Used to configure the operating data rate.
20bit/10bitn Connected to the GS2962 20bit/10bit
pin. Used to select the input bus width.
SDO_EN/DISn
Connected to the GS2962 SDO_EN/DIS
pin. Used to enable or disable the serial digital output stage.
When SDO_EN/DIS
is LOW, the serial digital output signals SDO and SDO are disabled and become
high-impedance.
When SDO_EN/DIS is HIGH, the serial digital output signals SDO and SDO are enabled.
DETECT_TRS
Connected to the GS2962 DETECT_TRS pin. Used to select external HVF timing mode or TRS extraction timing
mode.
When DETECT_TRS is LOW, the device extracts all internal timing from the supplied H:V:F or CEA-861 timing
signals, dependent on the status of the TIM861 pin. When DETECT_TRS is HIGH, the device extracts all internal
timing from TRS signals embedded in the supplied video stream.
ANC_BLANKn
Connected to the GS2962 ANC_BLANK
pin.
When ANC_BLANK is LOW, the Luma and Chroma input data is set to the appropriate blanking levels during the
H and V blanking intervals.
When ANC_BLANK is HIGH, the Luma and Chroma data pass through the device unaltered. Only applicable in
SMPTE mode.
IOPROC_EN/DISn
Connected to the GS2962 IOPROC_EN/DIS
pin. When IOPROC_EN/DIS is HIGH, the I/O processing features of the
device are enabled. When IOPROC_EN/DIS
is LOW, the I/O processing features of the device are disabled. Only
applicable in SMPTE mode.
STANDBY
Connected to the GS2962 STANDBY pin. HIGH to power-down device.
NOTE: Cable Driver is not powered down.
JTAG_HOSTn
Connected to the GS2962 JTAG/HOST
pin. Used to select JTAG test mode or Host Interface mode.
When JTAG/HOST
is HIGH, the Host Interface port is configured for JTAG test.
When JTAG/HOST
is LOW, normal operation of the Host Interface port resumes and the separate JTAG pins
become the JTAG port (JP1).
RATE_SEL0
Data Rate
0
0
1
0
1
X
1.485 or 1.485/1.001Gb/s
2.97 or 2.97/1.001Gb/s
270Mb/s
RATE_SEL1
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1.3 Inputs
1.3.1 Parallel Video Input
The EB-GS2962 has a 48-pin parallel connector for the serialized video input (J25). The
video input includes the 20-bit video data and pixel clock.
The related timing signals (F,V,H) are on the 10-bit parallel connector (J27).
1.4 SDI Outputs (J3 and J4)
The EB-GS2962 includes two SDI outputs on J3 and J4.
1.5 Control and Status
1.5.1 GSPI Header (JP8)
The GS2962 contains a set of internal status and configuration registers. These registers
are available to the host via the GS2962’s GSPI pins. To communicate with the GS2962,
a Gennum USB to GSPI dongle must be connected to the GSPI header.
A GSPI dongle is provided for communication to the GSPI interface. If you have the
EB-GS2962 and the EB-GS2960 connected together, only one GSPI dongle is required,
and can be connected to either of the boards. On the EB-GS2962, connector J29 provides
interface with the EB-GS2960.
1.5.2 JTAG Header (JP1)
This header is used for the JTAG test of the GS2962.
1.5.3 Lock Status
LED U25 indicates the lock status of the GS2962.
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1.6 Modes of Operation
The GS2962 supports four distinct modes of operation that can be set through the DIP
switch or by programming internal registers through the GSPI. These modes are: SMPTE
mode, Data-Through mode, DVB-ASI mode and Standby mode.
In SMPTE mode, the GS2962 performs all SMPTE processing features. Both SMPTE 425M
Level A and Level B formats are supported with optional conversion from Level A to
Level B for 1080p 50/60 4:2:2 10-bit.
In DVB-ASI mode, the device will perform 8b/10b encoding prior to transmission.
In Data-Through mode, all SMPTE and DVB-ASI processing is disabled. The device can
be used as a simple parallel to serial converter.
The device can also operate in a lower power Standby mode. In this mode, no signal is
generated at the output.
The DIP switches (SW6 and SW7) correspond directly to pins on the GS2962. Refer to the
GS2962 Data Sheet for a more detailed explanation of the operation of these pins in each
mode.
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2. Board Schematics
2.1 Top Level Schematic
Figure 2-1: Top Level Schematic
TCK
1
GND
2
TDO
3
VDD
4
TMS
5
NC
6
NC
7
NC
8
TDI
9
GND
10
JP1
TSW-105-07-L-D
VCC_3.3V
C69
0.1u
IO_VDD
SD
1RATE_SEL0
X
TIM861
RATE_SEL1
SMPTE_BYPASSn
DV B_ASI
RAT E_SEL 0
0
0
HD
GND
2
RESET
1
MR
3
Vcc
5
WDI
4
U1
MAX6823V
ANC_BL ANKn
0
1
3G
IOPROC_EN/DI Sn
RAT E_SEL 1
20BIT/10BITn
DETECT_TRS
SDO_EN/DI Sn
RATE_SEL1 Pin _ctrl8
20BIT/10BITn Pin _ctrl6
DETECT_ TR S Pin _ctrl4
IO_VDD
1
2
3
4
5
6
7
89
10
11
12
13
14
15
16
RN1 1K
T/R b0
2
A0
3
A1
4
A2
5
A3
6
T/R b3
7
T/R b2
10
B3
11
B2
12
B1
13
B0
14
T/R b1
15
VCCA
1
VCCB
16
GND
8
OEb
9
U17
FXL4TD245
TIM861 Pin _ctrl12
RATE_SEL0 Pin _ctrl9
DVB_ASI Pin _ctrl10
SMPTE_B Y PASSn Pin _ctrl11
GND
IO_VDD
R20
10K
IO_VDD
R21
10K
IO_VDD
R22
10K
JTAG
JTAG0
GSPI3
A_GND
SDI Output
1
3
2
J4
UCBBJE20-1
1
3
2
J3
UCBBJE20-1
+SDO
A_GND
-SDO
GSPI
GND
GND
CS1
JTAG/HOSTb
R80 10K
R79 10K
R78 10K
R77 10K
GSPI2
CS0
GSPI0
GSPI1
GND
GND
Sch_GS2962
GS2962
SDO
SDOn
PCLK
DIN[19:0]
HVF[2:0]
RESETn
GS2972_Locked
Pin _ctrl[13: 0]
JTAG[3:0]
GSPI[3:0]
R108
12
3
4
5
6
7
8
910
JP8
TSW-105-07-L-D
Sch_Power
Power
CS1
GND
R109
R107
1.15K
PCLK_IN
R110
ANC_BLANKn Pin _c trl3
R111 1K
TDI
GND
GND
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
J25
SQT-124-01-F-D-RA
FEMALE: TOP-SIDE
2
4
6
8
10
1
3
5
7
9
J27
SQT-105-01-F-D-RA
FEMALE: TOP-SIDE
VHVF1
HHVF0
IO_VDD
DIN2
DIN1
DIN0
PCLK_IN
DIN6
DIN5
DIN7
DIN4
DIN3
DIN17
DIN12
DIN11
DIN8
DIN9
DIN10
DIN19
DIN15
DIN16
DIN18
DIN14
Pin _ctrl[13: 0]
SDIN
SCLK
SDOUT
DIN13
2
4
6
8
10
1
3
5
7
9
J29
SQT-105-01-F-D-RA
FEMALE: TOP-SIDE
CS1
GSPI[3:0]
TMS
GND
JTAG2TDO
CS0
RST
SCLK
FHVF2
SDO_EN/D ISn Pin _ctrl5
Pin _ctrl0Pin _ctrl0JTAG_HOSTn
STAN DBYSTAND BY Pin _ctrl13
SDIN
GND
STANDBY
VCC_3.3V
CS1
JTAG_HOSTn
Lock
A1 green
1
A2 red
2
K1
3
K2
4
U25
HSMF -C165
R101
75R
GND
GS2972_DIN[ 19:0]
VCC_5V
TCK
HVF[2: 0]
IO_VDD
SDOUT
GND
IO_VDD
VCC_3.3V
JTAG3
1
2
3
4
5
6
7
8
9
24
23
22
21
20
19
18
17
16
15
14
13
10
11
12
SW8
12_SWITCH
JTAG[3:0]
JTAG1
GND
GND
S1
B3S-1002
RESET
GND
RESET
RESET
Pin _ctrl7IOPROC_EN /DISn
GND
VCCA
1
VCCB
10
A0
2
A1
3
TR0
4
TR1
6
GND
5
OEb
7
B0
9
B1
8
U28
FXL2TD245
VCC_3.3V
IO_VDD
GND
1K
1K
1K
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2.2 GS2962 Schematic
Figure 2-2: GS2962 Schematic
10. Impedance controlled signals(ref er to PCB layout guide).
C18
10u
R17
DNP
C41 4u7
R27 75R
R24 75R
C24
10n
C16
1u
C5
10n
C37 1u
C6
10n
C33
1u
C34
10n
C36 10u
C9
10n
R1
200R
R9
0R
C39 4u7
R28 75R
C29
10n
R23
750R
C32
10n
C8
1u
C15
1u
L3 5n6
C31
1u
R13
0R
R26 75R
R6
0R
R14 380R
C10
10n
R11
0R
C7
10u
SDO
R7
105R
Return Loss compensation Network
C30
1u
C35 100p
Pins A5,E1,K8,G10
C17
10n
SDO
(SUBJECT TO CHANGE)
VCO_VDD
B7
VBG
A8
VCO_GND
B8
TDI
E7
RSV
A9
TIM_8 61
G3
PCLK
B4
IO_VDD
G1
DIN18
A2
DIN19
B3
LF
A7
A_VDD
A10
A_GND
B10
DIN17
A1
CORE_VDD
K8
IO_GND
H6
DETECT_TR S
F3
CORE_GND
E6
A_GND
B9
DIN16
B2
CORE_VDD
G10
PLL_VDD
A6
PLL_VDD
B6
RSV
D5
STAN DBY
D3
RSV
K7
RSV
J7
RSV
J6
DIN14
C2
DIN15
B1
CORE_GND
C5
CORE_GND
B5
RSV
D6
RSV
D7
DVB_ASI
G5
LOCKED
H4
IO_GND
H5
RSV
K6
DIN12
C3
DIN13
C1
RSV
D8
TMS
E8
TDO
F8
RATE_SEL0
E3
CORE_GND
E5
CORE_VDD
E1
RSV
K5
IO_VDD
H10
DIN10
D2
DIN11
D1
IO_GND
F4
TCK
J8
CORE_GND
G9
20BIT/10BIT
G4
CORE_GND
F5
CORE_VDD
A5
RSV
J5
IO_GND
G2
DIN8
F2
DIN9
F1
RSV
F7
CD_GND
F9
CD_GND
E9
IOPROC_EN/DIS
G7
SMPTE_BYPASS
G6
RESET
G8
RSV
J4
ANC_BLANK
H3
DIN6
H2
DIN7
H1
CD_GND
D9
CORE_GND
E2
RSV
H7
CS_TMS
K9
SCLK_TCK
J10
SDOUT_TDO
J9
RSV
K4
H/HSYNC
A4
DIN4
J2
DIN5
J1
CORE_GND
F6
PLL_GND
C8
PLL_GND
C7
PLL_GND
C6
SDO_EN/DIS
D4
SDIN_TDI
K10
V/VSYNC
C4
IO_GND
H9
DIN2
K2
DIN3
K1
RSET
F10
CD_VDD
E10
SDO
C10
SDO
D10
CD_GND
C9
JTAG/HOST
H8
F/DE
A3
RATE_SEL1
E4
DIN0
K3
DIN1
J3
U5
GS2962
C40 10n
L4 5n6
C19
10n
C14
10n
C4
10n
C25
1u
C3
10n
PCLK
SDO
HVF[2: 0]
DIN[19:0]
JTAG[3:0]
Pin _ctrl[13:0]
Locked
A_GND
GGSPI[3:0]
A_GND
A_GND
A_GND
VCC_3.3V
A_GND
VCC_3.3V
+1.2V
+1.2V
CD_VDD
+1.2VA
IO_VDD
+3.3VA
+1.2VA
+1.2VA IO_VDD +3.3VA
CD_VDD
+1.2V
A_GND
CD_VDD
GND
CD_VDD
GND
GND
GND
GND
GND
GND
C38
DNP
Close to
GS2962.
PCLK
R82
0R
R81
0R
Locked
3. Pow er consumption:
2. DNP (Do Not Populate);
5. Use BNC ground as the ground test points;
235mA
Close to GS2962.
+1.2V
HHVF0
VHVF1
FHVF2
86
+3.3V
DIN14
Power Decoupling & Filtering
DIN16
DIN15
DIN2
DIN1
DIN19
DIN18
DIN17
DIN6
DIN5
DIN0
DIN4
DIN3
DIN7
DIN11
DIN10
DIN9
DIN8
GS2962
DIN13
DIN12
Device
6. Lable the connectors, LEDs, DIP sw itches and jumpers. Lable some critical signals of the connectors;
JTAG_HOSTn Pin _ ctrl0
Notes:
0Others 3
20BIT/10BITn Pin _ctrl6
SDO_EN/DISnPin _ctrl5
DETECT_TR S Pin _ctrl4
ANC_BLANKn Pin _ctrl3
TIM861Pin _c trl12
SMPTE_BYPASSnPin _ctrl11
DVB_ASIPin _ctrl10
RATE_SEL0 Pin _ctrl9
RATE_SEL1 Pin _ctrl8
IOPROC_EN /DISnPin _ctrl7
LEDs
50
11. Via size test point should be as close as possible to the pin;
Pin A10
IO_V
1. This board is GS2972 compatible;
Pins A6,B6
TDI 2 JTAG0
TMS2JTAG1
TCK2 JTAG3
TDO2 JTAG2
3.3V or 1.8V
SDO GSPI0
SDI GSPI1
SCK GSPI2
CSn GSPI3
Pin E10
Tot al 94mA235mA
7. Minimum of 3x trace w idth spacing f or DIN10~19, PCLK;
4. IO_V DD can be +3.3v, w hich is supplied by this board through a 1-ohm jumper, or diff erent
voltage supplied by the input board connected to it, in w hich case the 1-ohm jumper shall be removed;
8. Analog pow er and ground isolation(ref er to PCB layout guide);
Pin _ctrl13STAN DBY
9. Critital 3G signal layout(refer to PCB layout guide);
Pins G1,H10
A_GND
SDO
SDO
SDO
RESET
RESET
GND
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2.3 Power Schematic
Figure 2-3: Power Schematic
+1.2V
TP2
C26
0.1u
He at s ink
on copper
C27
22u
IN
8
SHDN
5
AGND
4
PGND
6
SENSE
3
OUT
2
NC
1
NC
7
U4
LT3021ES8-1.2
500mA
1
2
3
JP7
VCC_3.3V
1.8V 3.3V
VCC_1.8V
IO V
IO_V
C88
10n
C86
1u
5V
R32
240R
R66
49.9K
R4
1.15K
+1.8V
C84
0.1u
TP3
PWR
C85
22u
He at s ink
on copper
IN
8
SHDN
5
AGND
4
PGND
6
SENSE
3
OUT
2
NC
1
NC
7
U16
LT3021ES8-1.8
VCCA
1
GND
2
A
3
B
4
DIR
5
VCCB
6
SN74LVC1T45DBVR
U15
C87
22u
500mA
VCC_3.3V
PWRGD_3V3
C90
1u
R2
3.57K
VCC_1.8V
C12
22u
GND
GND
VCC_5V
IN
5
IN
6
IN
7
IN
8
BIAS
10
PG
9
OUT
1
OUT
18
OUT
19
OUT
20
NC
17
FB
16
EN
11
SS
15
GND
12
NC
13
NC
14
NC
2
NC
3
NC
4
Pad
21
U14
TPS74201_RGW
D7
LNJ311G8P
GND
VCC_5V
GNDGND
GND
VCC_3.3VVCC_5V
VCC_3.3V
VCC_5V
GND
GND
PWRGD_3V3
POWER SUPPLIES
VCC_3.3V
C70
1u
+1.2V
C20
EEV-FK1C221XP
C91
22u
GND
J1
5V Input
GND
GND
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3. Board Layout
Figure 3-1: Layer 1 (Top Layer)
Figure 3-2: Layer 2 (Ground)
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Figure 3-3: Layer 3 (Power)
Figure 3-4: Layer 4 (Signal 1)
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Figure 3-5: Layer 5 (Signal 2)
Figure 3-6: Layer 6 (Bottom Layer)
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4. Bill of Materials
Table 4-1: Bill of Materials
Quantity Reference Part
14
C3, C4, C5, C6, C9, C10, C14, C17, C19, C24,
C29, C32, C34, C40
10nF Capacitor (402)
3 C7, C18, C36 10μF Capacitor (0603)
8 C8, C15, C16, C25, C30, C31, C33, C37 1μF Capacitor (0603)
5 C12, C27, C85, C87, C91 22μF Capacitor (0805)
1C20
EEV-FK1C221XP Capacitor
(CT-CAP/PANA_FK_D8)
3 C26, C69, C84 0.1μF Capacitor (0603)
1 C35 100pF Capacitor (0402)
2 C39, C41 4.7μF Capacitor (0603)
3 C70, C86, C90 1μF Capacitor (0402)
1 C88 10nF Capacitor (0402)
1D7 LNJ311G8P (1206_LED)
2 JP1, JP8 TSW-105-07-L-D
1 JP7
BLKCON
.100/VH/TM1SQ/W.100/3
1 J1
5V Input
(CON_WEID5MM_2_PWR)
2 J3, J4
UCBBJE20-1 (BNC_EDGEMNT
_GHZ-POUR-2LYR-ER3.8)
1 J25
SQT-124-01-F-D-RA (HEADER
2MM_48_2X24_INVERSE)
2 J27, J29
SQT-105-01-F-D-RA (HEADER
2MM_10_2X5_INVERSE)
2 L3, L4 5.6nH Inductor (0402)
1 R1 200Ω Resistor (0603)
6 R6, R9, R11, R13, R81, R82 0Ω Resistor (0603)
1 R2 3.57kΩ Resistor (0603)
2 R4, R107 1.15kΩ Resistor (0603)
1 R7 105Ω Resistor (0603)
1 R14 380Ω Resistor (0603)
7 R20, R21, R22, R77, R78, R79, R80 10kΩ Resistor (0603)
1 R23 750Ω Resistor (0402)
5 R24, R26, R27, R28, R101 75Ω Resistor (0402)
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1 R32 240Ω Resistor (0603)
1 R66 49.9kΩ Resistor (0603)
2 R109, R110 0Ω Resistor (0402)
1 R111 10kΩ Resistor (0402)
1RN1 1kΩ Resistor Network
1 SW8 12-position DIP switch
1 S1 B3S-1002
2 TP2, TP3 CT-TP (via)
1 U1 MAX6823V (SOT23)
1 U4 LT3021ES8-1.2 (CT-SOIC_8)
1 U5
GS2962
(CT-BGA_100_11X11_1.00)
1U14
TPS74201_RGW
(20QFN-5X5(MOD))
1 U15 SN74LVC1T45DBVR (sot23-6)
1 U16 LT3021ES8-1.8 (CT-SOIC_8)
1 U17 FXL4TD245 (mlp16e)
1 U25 HSMF-C165
1 U28 FXL2TD245 (mac010a)
Table 4-1: Bill of Materials (Continued)
Quantity Reference Part
© Semtech 2012
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DOCUMENT IDENTIFICATION
EVALUATION BOARD USER GUIDE
Information relating to this product and the application or design described
herein is believed to be reliable, however such information is provided as a
guide only and Semtech assumes no liability for any errors in this document, or
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16
Contact Information
Semtech Corporation
Gennum Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805) 498-2111, Fax: (805) 498-3804
www.semtech.com
CAUTION
ELECTROSTATIC SENSITIVE DEVICES
DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A
STATIC-FREE WORKSTATION
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