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Analog Devices ADSP-BF504, ADSP-BF504F, EZ-KIT Lite ADSP-BF506F Hardware Reference Manual

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a
ADSP-BF50x Blackfin
®
Processor
Hardware Reference
Revision 1.2, February 2013
Part Number
82-100101-01
Analog Devices, Inc.
One Technology Way
Norwood, Mass. 02062-9106
Copyright Information
© 2013 Analog Devices, Inc., ALL RIGHTS RESERVED. This docu-
ment may not be reproduced in any form without prior, express written
consent from Analog Devices, Inc.
Printed in the USA.
Disclaimer
Analog Devices, Inc. reserves the right to change this product without
prior notice. Information furnished by Analog Devices is believed to be
accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use; nor for any infringement of patents or other rights of
third parties which may result from its use. No license is granted by impli-
cation or otherwise under the patent rights of Analog Devices, Inc.
Trademark and Service Mark Notice
The Analog Devices logo, Blackfin, CrossCore, EngineerZone, EZ-KIT
Lite, and VisualDSP++ are registered trademarks of Analog Devices, Inc.
All other brand and product names are trademarks or service marks of
their respective owners.
ADSP-BF50x Blackfin Processor Hardware Reference iii
CONTENTS
PREFACE
Purpose of This Manual .................................................................. li
Intended Audience .......................................................................... li
Manual Contents ........................................................................... lii
What’s New in This Manual ........................................................... lv
Technical Support .......................................................................... lvi
Supported Processors .................................................................. lviiii
Product Information .................................................................. lviiii
Analog Devices Web Site ...................................................... lviiii
EngineerZone .......................................................................... lix
Notation Conventions .................................................................... lx
Register Diagram Conventions ...................................................... lxi
INTRODUCTION
General Description of Processor ................................................... 1-1
Portable Low-Power Architecture ............................................. 1-3
System Integration ................................................................... 1-3
Peripherals .................................................................................... 1-4
Contents
iv ADSP-BF50x Blackfin Processor Hardware Reference
Memory Architecture .................................................................... 1-4
Internal Memory ..................................................................... 1-6
External Memory .................................................................... 1-6
I/O Memory Space .................................................................. 1-7
DMA Support .............................................................................. 1-8
General-Purpose I/O (GPIO) ........................................................ 1-9
Two-Wire Interface ..................................................................... 1-10
RSI Interface .............................................................................. 1-11
General-Purpose (GP) Counter ................................................... 1-12
3-Phase PWM Unit .................................................................... 1-13
Parallel Peripheral Interface ......................................................... 1-14
SPORT Controllers .................................................................... 1-16
Serial Peripheral Interface (SPI) Por ts .......................................... 1-18
Timers ........................................................................................ 1-18
UART Por ts ............................................................................... 1-19
Controller Area Network (CAN) Interface ................................... 1-21
ACM Interface ........................................................................... 1-22
Internal ADC ............................................................................. 1-22
Watchdog Timer ......................................................................... 1-23
Clock Signals .............................................................................. 1-23
Dynamic Power Management ...................................................... 1-24
Full-On Operating Mode—Maximum Per formance ............... 1-24
Active Operating Mode—Moderate Dynamic Power Savings .. 1-24
Sleep Operating Mode—High Dynamic Power Savings .......... 1-25
ADSP-BF50x Blackfin Processor Hardware Reference v
Contents
Deep Sleep Operating Mode—Maximum Dynamic Power
Savings ............................................................................... 1-26
Hibernate State—Maximum Static Power Savings ................... 1-26
Instruction Set Description ......................................................... 1-27
Development Tools ..................................................................... 1-28
MEMORY
Memory Architecture .................................................................... 2-1
L1 Instruction SRAM .................................................................... 2-2
L1 Data SRAM ............................................................................. 2-3
L1 Data Cache .............................................................................. 2-4
Boot ROM ................................................................................... 2-4
External Memory .......................................................................... 2-4
Processor-Specific MMRs .............................................................. 2-5
DMEM_CONTROL Register ................................................. 2-5
DTEST_COMMAND Register ............................................... 2-6
CHIP BUS HIERARCHY
Chip Bus Hierarchy Overview ....................................................... 3-1
Interface Overview ........................................................................ 3-2
Internal Clocks ........................................................................ 3-2
Core Bus Overview .................................................................. 3-4
Peripheral Access Bus (PAB) ..................................................... 3-5
PAB Arbitration .................................................................. 3-6
PAB Agents (Masters, Slaves) ............................................... 3-6
PAB Per formance ................................................................ 3-7
Contents
vi ADSP-BF50x Blackfin Processor Hardware Reference
DMA Access Bus (DAB), DMA Core Bus (DCB), DMA
External Bus (DEB) .............................................................. 3-7
DAB, DCB, and DEB Arbitration ....................................... 3-7
DAB Bus Agents (Masters) .................................................. 3-9
DAB, DCB, and DEB Performance ..................................... 3-9
External Access Bus (EAB) .................................................... 3-10
Arbitration of the External Bus .............................................. 3-10
DEB/EAB Per formance ......................................................... 3-10
SYSTEM INTERRUPTS
Specific Information for the ADSP-BF50x ..................................... 4-1
Overview ...................................................................................... 4-1
Features .................................................................................. 4-2
Description of Operation .............................................................. 4-2
Events and Sequencing ............................................................ 4-2
System Peripheral Interrupts .................................................... 4-4
Programming Model ..................................................................... 4-7
System Interrupt Initialization ................................................. 4-8
System Interrupt Processing Summary ..................................... 4-8
System Interrupt Controller Registers .......................................... 4-10
System Interrupt Assignment (SIC_IAR) Register .................. 4-11
System Interrupt Mask (SIC_IMASK) Register ...................... 4-12
System Interrupt Status (SIC_ISR) Register ........................... 4-12
System Interrupt Wakeup-Enable (SIC_IWR) Register ........... 4-12
ADSP-BF50x Blackfin Processor Hardware Reference vii
Contents
Programming Examples ............................................................... 4-13
Clearing Interrupt Requests ................................................... 4-13
Unique Information for the ADSP-BF50x Processor .................... 4-15
Interfaces .............................................................................. 4-15
System Peripheral Interrupts .................................................. 4-18
EXTERNAL BUS INTERFACE UNIT
EBIU Overview ............................................................................ 5-1
Block Diagram ........................................................................ 5-3
Internal Memory Interfaces ...................................................... 5-4
Registers .................................................................................. 5-4
Error Detection ....................................................................... 5-5
AMC Overview and Features ......................................................... 5-5
Features ................................................................................... 5-6
Asynchronous Memory Interface .............................................. 5-6
Asynchronous Memory Address Decode .............................. 5-6
AMC Description of Operation ..................................................... 5-6
Avoiding Bus Contention ........................................................ 5-6
AMC Programming Model ............................................................ 5-7
EBIU Registers ............................................................................. 5-9
EBIU_AMGCTL Register ..................................................... 5-10
EBIU_AMBCTL Register ...................................................... 5-11
EBIU_MODECTL Register .................................................. 5-12
EBIU_FCTL Register ............................................................ 5-12
Contents
viii ADSP-BF50x Blackfin Processor Hardware Reference
INTERNAL FLASH MEMORY
Overview ...................................................................................... 6-1
Command Interface to Internal Flash Memory .............................. 6-6
Command Interface – Standard Commands ............................ 6-7
Read Array Command ....................................................... 6-7
Read Status Register Command ......................................... 6-8
Read Electronic Signature Command ................................. 6-8
Read CFI Quer y Command ............................................... 6-9
Clear Status Register Command ......................................... 6-9
Block Erase Command ..................................................... 6-10
Program Command ......................................................... 6-11
Program/Erase Suspend Command ................................... 6-11
Program/Erase Resume Command ................................... 6-12
Protection Register Program Command ............................ 6-13
The Set Configuration Register Command ....................... 6-14
Block Lock Command ..................................................... 6-14
Block Unlock Command ................................................. 6-15
Block Lock-Down Command ........................................... 6-15
Status Register ..................................................................... 6-18
Program/Erase Controller Status Bit (SR7) ....................... 6-19
Erase Suspend Status Bit (SR6) ........................................ 6-20
Erase Status Bit (SR5) ...................................................... 6-20
Program Status Bit (SR4) ................................................. 6-21
V
PP
Status Bit (SR3) ........................................................ 6-21
ADSP-BF50x Blackfin Processor Hardware Reference ix
Contents
Program Suspend Status Bit (SR2) .................................... 6-22
Block Protection Status Bit (SR1) ..................................... 6-22
Bank Write Status Bit (SR0) ............................................. 6-22
Configuration Register ......................................................... 6-24
Read Select Bit (CR15) .................................................... 6-24
X Latency Bits (CR13-CR11) ........................................... 6-25
Wait Polarity Bit (CR10) .................................................. 6-25
Data Output Configuration Bit (CR9) ............................. 6-26
Wait Configuration Bit (CR8) .......................................... 6-27
Burst Type Bit (CR7) ....................................................... 6-27
Valid Clock Edge Bit (CR6) ............................................. 6-27
Wrap Burst Bit (CR3) ...................................................... 6-27
Burst Length Bits (CR2-CR0) .......................................... 6-27
Read Modes ......................................................................... 6-33
Asynchronous Read Mode ................................................ 6-33
Synchronous Burst Read Mode ......................................... 6-33
Synchronous Burst Read Suspend ..................................... 6-35
Single Synchronous Read Mode ........................................ 6-36
Dual Operations and Multiple Bank Architecture .................. 6-36
Contents
x ADSP-BF50x Blackfin Processor Hardware Reference
Block Locking ...................................................................... 6-38
Reading a Block’s Lock Status .......................................... 6-39
Locked State .................................................................... 6-39
Unlocked State ................................................................ 6-39
Lock-Down State ............................................................. 6-40
Locking Operations During Erase Suspend ....................... 6-40
Block Address Table .................................................................... 6-42
Common Flash Interface ............................................................ 6-45
Flowcharts and Pseudo Codes .................................................... 6-56
Command Interface State Tables ................................................ 6-68
Internal Flash Memory Programming Guidelines ......................... 6-77
Bringing Internal Flash Memory Out of Reset ........................ 6-78
Timing Configurations for Setting the Internal Flash Memory
in Asynchronous Read Mode .............................................. 6-79
Timing Configurations for Setting the Internal Flash Memory
for Write Accesses ............................................................... 6-80
Enabling the Program or Erasure of Internal Flash Memory
Blocks ................................................................................ 6-82
Configuring Internal Flash Memory for Synchronous Burst
Read Mode ......................................................................... 6-83
Supported Configuration Register Combinations in
ADSP-BF50xF Processors .............................................. 6-84
Configuring the EBIU for Synchronous Read Mode .......... 6-85
Unsupported Programming Practices in Flash ........................ 6-87
ADSP-BF50x Blackfin Processor Hardware Reference xi
Contents
Internal Flash Memory Control Registers ..................................... 6-88
Internal Flash Memory Control (FL ASH_CONTROL)
Register .............................................................................. 6-88
Internal Flash Memory Control Set
(FLASH_CONTROL_SET) Register .................................. 6-91
Internal Flash Memory Control Clear
(FLASH_CONTROL_CLEAR) Register ............................. 6-91
DIRECT MEMOR Y ACCESS
Specific Information for the ADSP-BF50x ..................................... 7-1
Overview and Features .................................................................. 7-2
DMA Controller Overview ............................................................ 7-4
External Interfaces ................................................................... 7-4
Internal Interfaces .................................................................... 7-4
Peripheral DMA ...................................................................... 7-5
Memory DMA ........................................................................ 7-6
Handshaked Memory DMA (HMDMA) Mode .................... 7-8
Modes of Operation ...................................................................... 7-9
Register-Based DMA Operation ............................................... 7-9
Stop Mode ........................................................................ 7-11
Autobuffer Mode .............................................................. 7-11
Two-Dimensional DMA Operation ........................................ 7-11
Examples of Two-Dimensional DMA ................................. 7-13
Descriptor-based DMA Operation ......................................... 7-14
Descriptor List Mode ........................................................ 7-15
Descriptor Array Mode ...................................................... 7-15
Contents
xii ADSP-BF50x Blackfin Processor Hardware Reference
Variable Descriptor Size .................................................... 7-15
Mixing Flow Modes .......................................................... 7-17
Functional Description ............................................................... 7-17
DMA Operation Flow ........................................................... 7-17
DMA Startup ................................................................... 7-17
DMA Refresh ................................................................... 7-23
Work Unit Transitions ...................................................... 7-25
DMA Transmit and MDMA Source .............................. 7-26
DMA Receive ............................................................... 7-27
Stopping DMA Transfers .................................................. 7-29
DMA Errors (Aborts) ............................................................ 7-30
DMA Control Commands .................................................... 7-32
Restrictions ...................................................................... 7-35
Transmit Restart or Finish ............................................. 7-35
Receive Restart or Finish ............................................... 7-36
Handshaked Memory DMA Operation .................................. 7-37
Pipelining DMA Requests ................................................. 7-38
HMDMA Interrupts ......................................................... 7-40
ADSP-BF50x Blackfin Processor Hardware Reference xiii
Contents
DMA Performance ................................................................ 7-41
DMA Throughput ............................................................ 7-42
Memory DMA Timing Details .......................................... 7-45
Static Channel Prioritization ............................................. 7-45
Temporar y DMA Urgency ................................................. 7-45
Memory DMA Priority and Scheduling ............................. 7-47
Traffic Control .................................................................. 7-49
Programming Model ................................................................... 7-51
Synchronization of Software and DMA .................................. 7-51
Single-Buffer DMA Transfers ............................................. 7-53
Continuous Transfers Using Autobuffering ........................ 7-54
Descriptor Structures ........................................................ 7-56
Descriptor Queue Management ......................................... 7-57
Descriptor Queue Using Interrupts on Every
Descriptor .................................................................. 7-58
Descriptor Queue Using Minimal Interrupts .................. 7-59
Software-Triggered Descriptor Fetches ............................... 7-61
DMA Registers ........................................................................... 7-63
DMA Channel Registers ........................................................ 7-64
DMA Peripheral Map Registers
(DMAx_PERIPHERAL_MAP/
MDMA_yy_PERIPHERAL_MAP) ................................. 7-67
DMA Configuration Registers
(DMAx_CONFIG/MDMA_yy_CONFIG) .................... 7-68
DMA Interrupt Status Registers
(DMAx_IRQ_STATUS/MDMA_yy_IRQ_STATUS) ...... 7-72
Contents
xiv ADSP-BF50x Blackfin Processor Hardware Reference
DMA Start Address Registers
(DMAx_START_ADDR/MDMA_yy_START_ADDR) . 7-75
DMA Current Address Registers
(DMAx_CURR_ADDR/MDMA_yy_CURR_ADDR) ... 7-76
DMA Inner Loop Count Registers
(DMAx_X_COUNT/MDMA_yy_X_COUNT) ............. 7-76
DMA Current Inner Loop Count Registers
(DMAx_CURR_X_COUNT
/MDMA_yy_CURR_X_COUNT) ................................ 7-77
DMA Inner Loop Address Increment Registers
(DMAx_X_MODIFY/MDMA_yy_X_MODIFY) ........... 7-78
DMA Outer Loop Count Registers
(DMAx_Y_COUNT/MDMA_yy_Y_COUNT) ............. 7-79
DMA Current Outer Loop Count Registers
(DMAx_CURR_Y_COUNT/
MDMA_yy_CURR_Y_COUNT) .................................. 7-80
DMA Outer Loop Address Increment Registers
(DMAx_Y_MODIFY/MDMA_yy_Y_MODIFY) ........... 7-80
DMA Next Descriptor Pointer Registers
(DMAx_NEXT_DESC_PTR/
MDMA_yy_NEXT_DESC_PTR) .................................. 7-81
DMA Current Descriptor Pointer Registers
(DMAx_CURR_DESC_PTR/
MDMA_yy_CURR_DESC_PTR) ................................. 7-82
HMDMA Registers ............................................................... 7-83
Handshake MDMA Control Registers
(HMDMAx_CONTROL) ............................................. 7-83
Handshake MDMA Initial Block Count Registers
(HMDMAx_BCINIT) ................................................... 7-86
ADSP-BF50x Blackfin Processor Hardware Reference xv
Contents
Handshake MDMA Current Block Count Registers
(HMDMAx_BCOUNT) ................................................ 7-86
Handshake MDMA Current Edge Count Registers
(HMDMAx_ECOUNT) ................................................ 7-87
Handshake MDMA Initial Edge Count Registers
(HMDMAx_ECINIT) ................................................... 7-88
Handshake MDMA Edge Count Urgent Registers
(HMDMAx_ECURGENT) ............................................ 7-88
Handshake MDMA Edge Count Overflow Interrupt
Registers (HMDMAx_ECOVERFLOW) ........................ 7-89
DMA Traffic Control Registers
(DMA_TC_PER and DMA_TC_CNT) .............................. 7-89
DMA_TC_PER Register ................................................... 7-90
DMA_TC_CNT Register .................................................. 7-90
Programming Examples ............................................................... 7-92
Register-Based 2-D Memory DMA ........................................ 7-92
Initializing Descriptors in Memory ........................................ 7-95
Software-Triggered Descriptor Fetch Example ........................ 7-98
Handshaked Memory DMA Example ................................... 7-101
Unique Information for the ADSP-BF50x Processor .................. 7-103
Static Channel Prioritization ................................................ 7-105
DYNAMIC POWER MANAGEMENT
Phase Locked Loop and Clock Control .......................................... 8-1
PLL Overview ......................................................................... 8-2
PLL Clock Multiplier Ratios .................................................... 8-4
Core Clock/System Clock Ratio Control ............................. 8-5
Contents
xvi ADSP-BF50x Blackfin Processor Hardware Reference
Dynamic Power Management Controller ....................................... 8-7
Operating Modes .................................................................... 8-8
Dynamic Power Management Controller States ........................ 8-8
Full-On Mode .................................................................... 8-8
Active Mode ....................................................................... 8-9
Sleep Mode ........................................................................ 8-9
Deep Sleep Mode ............................................................. 8-10
Hibernate State ................................................................. 8-11
Operating Mode Transitions .................................................. 8-11
Programming Operating Mode Transitions ............................ 8-14
Dynamic Supply Voltage Control .......................................... 8-16
Power Supply Management ................................................... 8-16
Changing Voltage ............................................................. 8-16
Powering Down the Core (Hibernate State) ....................... 8-18
PLL and VR Registers ................................................................. 8-19
PLL_DIV Register ................................................................ 8-20
PLL_CTL Register ................................................................ 8-21
PLL_STAT Register .............................................................. 8-21
PLL_LOCKCNT Register ..................................................... 8-22
VR_CTL Register ................................................................. 8-22
System Control ROM Function .................................................. 8-23
Programming Model ............................................................. 8-25
Accessing the System Control ROM Function in C/C++ ........ 8-25
Accessing the System Control ROM Function in Assembly .... 8-26
ADSP-BF50x Blackfin Processor Hardware Reference xvii
Contents
Programming Examples ............................................................... 8-29
Full-on Mode to Active Mode and Back ................................. 8-31
Transition to Sleep Mode or Deep Sleep Mode ....................... 8-32
Set Wakeup Events and Enter Hibernate State ........................ 8-34
Perform a System Reset or Soft-Reset ..................................... 8-36
In Full-on Mode, Change VCO Frequency, Core Clock
Frequency, and System Clock Frequency .............................. 8-37
Changing Voltage Levels ........................................................ 8-39
GENERAL-PURPOSE POR TS
Overview ...................................................................................... 9-1
Features ........................................................................................ 9-1
Interface Overview ........................................................................ 9-3
External Interface .................................................................... 9-3
Port F Structure .................................................................. 9-3
Port G Structure ................................................................. 9-5
Port H Structure ................................................................. 9-6
Input Tap Considerations .................................................... 9-6
PWM Unit Considerations .................................................. 9-8
RSI Considerations ............................................................. 9-8
GP Counter Considerations ................................................ 9-9
SPI Considerations .............................................................. 9-9
Contents
xviii ADSP-BF50x Blackfin Processor Hardware Reference
Internal Interfaces ................................................................... 9-9
GP Timer Interaction With Other Blocks .......................... 9-10
Buffered CLKIN (CLKBUF) ......................................... 9-10
GP Counter .................................................................. 9-10
PPI ............................................................................... 9-10
UART .......................................................................... 9-10
SPORT ........................................................................ 9-11
ACM ............................................................................ 9-11
Performance/Throughput ...................................................... 9-12
Description of Operation ............................................................ 9-12
Operation ............................................................................. 9-12
General-Purpose I/O Modules ............................................... 9-13
GPIO Interrupt Processing .................................................... 9-16
Programming Model ................................................................... 9-22
Hysteresis Control ...................................................................... 9-24
PORTx Hysteresis (PORTx_HYSTERESIS) Register ............. 9-24
Drive Strength Control ............................................................... 9-26
Memory-Mapped GPIO Registers ............................................... 9-27
Port Multiplexer Control Registers (PORTx_MUX) ............... 9-27
Function Enable Registers (PORTx_FER) ............................. 9-30
GPIO Direction Registers (PORTxIO_DIR) ......................... 9-30
GPIO Input Enable Registers (PORTxIO_INEN) ................. 9-31
GPIO Data Registers (PORTxIO) ......................................... 9-31
GPIO Set Registers (PORTxIO_SET) ................................... 9-32
ADSP-BF50x Blackfin Processor Hardware Reference xix
Contents
GPIO Clear Registers (PORTxIO_CLEAR) ........................... 9-32
GPIO Toggle Registers (PORTxIO_TOGGLE) ...................... 9-33
GPIO Polarity Registers (PORTxIO_POLAR) ....................... 9-33
Interrupt Sensitivity Registers (PORTxIO_EDGE) ................. 9-34
GPIO Set on Both Edges Registers (PORTxIO_BOTH) ......... 9-34
GPIO Mask Interrupt Registers (PORTxIO_MASKA/B) ........ 9-35
GPIO Mask Interrupt Set Registers
(PORTxIO_MASKA/B_SET ) ............................................. 9-36
GPIO Mask Interrupt Clear Registers
(PORTxIO_MASKA/B_CLEAR) ........................................ 9-38
GPIO Mask Interrupt Toggle Registers
(PORTxIO_MASKA/B_TOGGLE) .................................... 9-40
Programming Examples ............................................................... 9-41
GENERAL-PURPOSE TIMERS
Specific Information for the ADSP-BF50x ................................... 10-1
Overview .................................................................................... 10-2
External Interface .................................................................. 10-3
Internal Interface ................................................................... 10-4
Description of Operation ............................................................ 10-4
Interrupt Processing ............................................................... 10-5
Illegal States .......................................................................... 10-7
Modes of Operation .................................................................. 10-10
Pulse Width Modulation (PWM_OUT) Mode ..................... 10-10
Output Pad Disable ........................................................ 10-12
Single Pulse Generation ................................................... 10-13
Contents
xx ADSP-BF50x Blackfin Processor Hardware Reference
Pulse Width Modulation Waveform Generation .............. 10-14
PULSE_HI Toggle Mode ................................................ 10-16
Externally Clocked PWM_OUT ..................................... 10-21
Using PWM_OUT Mode With the PPI .......................... 10-21
Stopping the Timer in PWM_OUT Mode ...................... 10-22
Pulse Width Count and Capture ( WDTH_CAP) Mode ....... 10-24
Autobaud Mode .............................................................. 10-32
External Event (EXT_CLK) Mode ....................................... 10-33
Programming Model ................................................................. 10-34
Timer Registers ......................................................................... 10-35
Timer Enable Register (TIMER_ENABLE) ......................... 10-36
Timer Disable Register (TIMER_DISABLE) ....................... 10-37
Timer Status Register (TIMER_STATUS) ........................... 10-39
Timer Configuration Register (TIMER_CONFIG) ............. 10-41
Timer Counter Register (TIMER_COUNTER) .................. 10-42
Timer Period ( TIMER_PERIOD) and Timer
Width (TIMER_WIDTH) Registers ................................. 10-43
Summary ............................................................................ 10-46
Programming Examples ............................................................ 10-49
Unique Information for the ADSP-BF50x Processor .................. 10-58
Interface Overview .............................................................. 10-58
External Interface ........................................................... 10-58
CORE TIMER
Specific Information for the ADSP-BF50x ................................... 11-1
/