NXP MPC106 Reference guide

MPC106UM/AD

7/2003

Rev. 2

MPC106

PCI Bridge/Memory Controll

er

User’s Manu

al

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Signal Descriptions

Device Programming

Processor Bus Interface

Secondary Cache Interface

Memory Interface

Internal Control

Performance Monitor

PCI Bus Interface

Bit and Byte Ordering

Index

Power Management

GLO

IND

A

Glossary of Terms and Abbreviations

1

2

3

5

6

7

8

9

4

10

Error Handling

B

Overview

Initialization Example

JTAG/Testing Support C

D

Revision History E

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Signal Descriptions

Device Programming

Processor Bus Interface

Secondary Cache Interface

Memory Interface

Internal Control

Performance Monitor

PCI Bus Interface

Bit and Byte Ordering

Index

Power Management

GLO

IND

A

Glossary of Terms and Abbreviations

1

2

3

5

6

7

8

9

4

10

Error Handling

B

Overview

Initialization Example

JTAG/Testing SupportC

D

Revision History E

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Contents

Section

Number Title

Page

Number

MOTOROLA Contents iii

Contents

Paragraph

Number Title

Page

Number

Contents

About This Book

Audience........................................................................................................... xxvii

Organization..................................................................................................... xxviii

Suggested Reading............................................................................................. xxix

General Information....................................................................................... xxix

Documentation on PowerPC Architecture..................................................... xxix

Conventions....................................................................................................... xxxi

Acronyms and Abbreviations ............................................................................ xxxi

Chapter 1

Overview

1.1 MPC106 PCIB/MC Features............................................................................... 1-1

1.2 MPC106 Major Functional Units ........................................................................1-4

1.2.1 60x Processor Interface....................................................................................1-4

1.2.2 Secondary (L2) Cache/Multiple Processor Interface....................................... 1-4

1.2.3 Memory Interface ............................................................................................ 1-5

1.2.4 PCI Interface....................................................................................................1-6

1.3 Performance Monitor........................................................................................... 1-6

1.4 Power Management ............................................................................................. 1-7

1.4.1 Full-On Mode .................................................................................................. 1-7

1.4.2 Doze Mode....................................................................................................... 1-7

1.4.3 Nap Mode ........................................................................................................ 1-7

1.4.4 Sleep Mode......................................................................................................1-7

1.4.5 Suspend Mode..................................................................................................1-8

Chapter 2

Signal Descriptions

2.1 Signal Configuration............................................................................................2-1

2.2 Signal Descriptions.............................................................................................. 2-2

2.2.1 Signal States at Reset....................................................................................... 2-8

2.2.2 60x Processor Interface Signals.......................................................................2-9

2.2.2.1 Address Bus (A[0–31]).............................................................................. 2-10

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iv MPC106 PCI/Bridge/Memory Controller User’s Manual MOTOROLA

2.2.2.1.1 Address Bus (A[0–31])—Output........................................................... 2-10

2.2.2.1.2 Address Bus (A[0–31])—Input ............................................................. 2-10

2.2.2.2 Address Acknowledge (AACK

)................................................................2-10

2.2.2.2.1 Address Acknowledge (AACK

)—Output............................................. 2-10

2.2.2.2.2 Address Acknowledge (AACK)—Input ............................................... 2-11

2.2.2.3 Address Retry (ARTRY

)............................................................................ 2-11

2.2.2.3.1 Address Retry (ARTRY

)—Output ........................................................ 2-11

2.2.2.3.2 Address Retry (ARTRY)—Input........................................................... 2-12

2.2.2.4 Bus Grant 0 (BG0

)—Output...................................................................... 2-12

2.2.2.5 Bus Request 0 (BR0

)—Input..................................................................... 2-13

2.2.2.6 Caching-Inhibited (CI)—Input/Output...................................................... 2-13

2.2.2.7 Data Bus Grant 0 (DBG0)—Output.......................................................... 2-13

2.2.2.8 Data Bus Grant Local Bus Slave (DBGLB)—Output............................... 2-14

2.2.2.9 Data Bus (DH[0–31], DL[0–31]) ..............................................................2-14

2.2.2.9.1 Data Bus (DH[0–31], DL[0–31])—Output ........................................... 2-15

2.2.2.9.2 Data Bus (DH[0–31], DL[0–31])—Input..............................................2-15

2.2.2.10 Global (GBL)—Input/Output.................................................................... 2-16

2.2.2.11 Local Bus Slave Claim (LBCLAIM)—Input............................................ 2-16

2.2.2.12 Machine Check (MCP)—Output............................................................... 2-16

2.2.2.13 Transfer Acknowledge (TA)...................................................................... 2-17

2.2.2.13.1 Transfer Acknowledge (TA)—Output................................................... 2-17

2.2.2.13.2 Transfer Acknowledge (TA)—Input .....................................................2-17

2.2.2.14 Transfer Burst (TBST)............................................................................... 2-18

2.2.2.14.1 Transfer Burst (TBST)—Output............................................................ 2-18

2.2.2.14.2 Transfer Burst (TBST)—Input.............................................................. 2-18

2.2.2.15 Transfer Error Acknowledge (TEA)—Output........................................... 2-18

2.2.2.16 Transfer Start (TS)..................................................................................... 2-19

2.2.2.16.1 Transfer Start (TS)—Output.................................................................. 2-19

2.2.2.16.2 Transfer Start (TS)—Input..................................................................... 2-19

2.2.2.17 Transfer Size (TSIZ[0–2]) ......................................................................... 2-19

2.2.2.17.1 Transfer Size (TSIZ[0–2])—Output...................................................... 2-19

2.2.2.17.2 Transfer Size (TSIZ[0–2])—Input......................................................... 2-20

2.2.2.18 Transfer Type (TT[0–4])............................................................................ 2-20

2.2.2.18.1 Transfer Type (TT[0–4])—Output......................................................... 2-20

2.2.2.18.2 Transfer Type (TT[0–4])—Input........................................................... 2-20

2.2.2.19 Write-Through (WT)—Input/Output......................................................... 2-20

2.2.2.20 Extended Address Transfer Start (XATS)—Input..................................... 2-21

2.2.3 L2 Cache/Multiple Processor Interface Signals............................................. 2-21

2.2.3.1 Internal L2 Controller Signals ................................................................... 2-22

2.2.3.1.1 Address Strobe (ADS)—Output............................................................2-22

2.2.3.1.2 Burst Address 0 (BA0)—Output...........................................................2-22

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MOTOROLA Contents v

2.2.3.1.3 Burst Address 1 (BA1)—Output...........................................................2-22

2.2.3.1.4 Bus Address Advance (BAA)—Output ................................................ 2-23

2.2.3.1.5 Data Address Latch Enable (DALE

)—Output...................................... 2-23

2.2.3.1.6 Data RAM Chip Select (DCS

)—Output ...............................................2-23

2.2.3.1.7 Dirty In (DIRTY_IN)—Input................................................................2-24

2.2.3.1.8 Dirty Out (DIRTY_OUT

)—Output....................................................... 2-24

2.2.3.1.9 Data RAM Output Enable (DOE

)—Output .......................................... 2-24

2.2.3.1.10 Data RAM Write Enable (DWE[0–2])—Output................................... 2-25

2.2.3.1.11 Hit (HIT

)—Input ................................................................................... 2-25

2.2.3.1.12 Tag Output Enable (TOE

)—Output....................................................... 2-25

2.2.3.1.13 Tag Valid (TV)—Output........................................................................ 2-26

2.2.3.1.14 Tag Write Enable (TWE)—Output........................................................ 2-26

2.2.3.2 External L2 Controller Signals..................................................................2-26

2.2.3.2.1 External L2 Bus Grant (BGL2)—Output..............................................2-26

2.2.3.2.2 External L2 Bus Request (BRL2)—Input............................................. 2-27

2.2.3.2.3 External L2 Data Bus Grant (DBGL2)—Output................................... 2-27

2.2.3.2.4 Hit (HIT)—Input ................................................................................... 2-27

2.2.3.3 Multiple Processor Interface Signals......................................................... 2-28

2.2.3.3.1 Bus Grant 1–3 (BG[1–3])—Output....................................................... 2-28

2.2.3.3.2 Bus Request 1–3 (BR[1–3])—Input...................................................... 2-28

2.2.3.3.3 Data Bus Grant 1–3 (DBG[1–3])—Output ...........................................2-29

2.2.4 Memory Interface Signals.............................................................................. 2-29

2.2.4.1 ROM Address 0 (AR0)—Output............................................................... 2-29

2.2.4.2 ROM Address 1–8 (AR[1–8])—Output....................................................2-30

2.2.4.3 ROM Address 9–20 (AR[9–20])—Output................................................2-30

2.2.4.4 Buffer Control (BCTL[0–1])—Output...................................................... 2-30

2.2.4.5 Column Address Strobe (CAS[0–7])—Output.......................................... 2-31

2.2.4.6 SDRAM Clock Enable (CKE)—Output.................................................... 2-31

2.2.4.7 SDRAM Chip Select (CS[0–7])—Output................................................. 2-31

2.2.4.8 SDRAM Data Input/Output Mask (DQM[0–7])—Output........................ 2-32

2.2.4.9 Flash Output Enable (FOE)—Output........................................................ 2-32

2.2.4.10 Memory Address (MA[0–12])—Output.................................................... 2-32

2.2.4.11 Memory Data Latch Enable (MDLE)—Output......................................... 2-33

2.2.4.12 Data Parity/ECC (PAR[0–7])..................................................................... 2-33

2.2.4.12.1 Data Parity (PAR[0–7])—Output .......................................................... 2-33

2.2.4.12.2 Data Parity (PAR[0–7])—Input............................................................. 2-33

2.2.4.13 Parity Path Read Enable (PPEN)—Output................................................ 2-33

2.2.4.14 Row Address Strobe (RAS[0–7])—Output............................................... 2-34

2.2.4.15 ROM Bank 0 Select (RCS0)—Output....................................................... 2-34

2.2.4.16 ROM Bank 1 Select (RCS1)—Output....................................................... 2-34

2.2.4.17 Real Time Clock (RTC)—Input ................................................................ 2-35

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vi MPC106 PCI/Bridge/Memory Controller User’s Manual MOTOROLA

2.2.4.18 SDRAM Internal Bank Select 0–1 (SDBA[0–1])—Output ...................... 2-35

2.2.4.19 SDRAM Column Address Strobe (SDCAS)—Output.............................. 2-35

2.2.4.20 SDRAM Address (SDMA[0–12])—Output.............................................. 2-35

2.2.4.21 SDRAM Row Address Strobe (SDRAS)—Output ................................... 2-36

2.2.4.22 Write Enable (WE)—Output ..................................................................... 2-36

2.2.5 PCI Interface Signals..................................................................................... 2-36

2.2.5.1 PCI Address/Data Bus (AD[31–0])........................................................... 2-37

2.2.5.1.1 Address/Data (AD[31–0])—Output ...................................................... 2-37

2.2.5.1.2 Address/Data (AD[31–0])—Input......................................................... 2-37

2.2.5.2 Command/Byte Enable (C/BE[3–0])......................................................... 2-37

2.2.5.2.1 Command/Byte Enable (C/BE[3–0])—Output .....................................2-37

2.2.5.2.2 Command/Byte Enable (C/BE[3–0])—Input........................................2-38

2.2.5.3 Device Select (DEVSEL).......................................................................... 2-38

2.2.5.3.1 Device Select (DEVSEL)—Output....................................................... 2-38

2.2.5.3.2 Device Select (DEVSEL)—Input.......................................................... 2-38

2.2.5.4 Frame (FRAME)........................................................................................ 2-39

2.2.5.4.1 Frame (FRAME)—Output ....................................................................2-39

2.2.5.4.2 Frame (FRAME)—Input.......................................................................2-39

2.2.5.5 PCI Bus Grant (GNT)—Input ...................................................................2-39

2.2.5.6 Initiator Ready (IRDY).............................................................................. 2-39

2.2.5.6.1 Initiator Ready (IRDY)—Output........................................................... 2-40

2.2.5.6.2 Initiator Ready (IRDY)—Input ............................................................. 2-40

2.2.5.7 Lock (LOCK)—Input................................................................................2-40

2.2.5.8 Parity (PAR)............................................................................................... 2-40

2.2.5.8.1 Parity (PAR)—Output ...........................................................................2-40

2.2.5.8.2 Parity (PAR)—Input..............................................................................2-41

2.2.5.9 Parity Error (PERR)................................................................................... 2-41

2.2.5.9.1 Parity Error (PERR)—Output ...............................................................2-41

2.2.5.9.2 Parity Error (PERR)—Input.................................................................. 2-41

2.2.5.10 PCI Bus Request (REQ)—Output............................................................. 2-41

2.2.5.11 System Error (SERR) ................................................................................ 2-42

2.2.5.11.1 System Error (SERR)—Output............................................................. 2-42

2.2.5.11.2 System Error (SERR)—Input................................................................ 2-42

2.2.5.12 Stop (STOP)...............................................................................................2-42

2.2.5.12.1 Stop (STOP)—Output ........................................................................... 2-42

2.2.5.12.2 Stop (STOP)—Input.............................................................................. 2-42

2.2.5.13 Target Ready (TRDY) ............................................................................... 2-42

2.2.5.13.1 Target Ready (TRDY)—Output ............................................................ 2-42

2.2.5.13.2 Target Ready (TRDY)—Input............................................................... 2-43

2.2.5.14 PCI Sideband Signals ................................................................................ 2-43

2.2.5.14.1 Flush Request (FLSHREQ)—Input....................................................... 2-43

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2.2.5.14.2 ISA Master (ISA_MASTER)—Input.................................................... 2-43

2.2.5.14.3 Memory Acknowledge (MEMACK)—Output ..................................... 2-44

2.2.5.14.4 Modified Memory Interrupt Request (PIRQ

)—Output......................... 2-44

2.2.6 Interrupt, Clock, and Power Management Signals........................................ 2-44

2.2.7 External ECM Error Detect (BERR)—Input................................................. 2-44

2.2.7.1 Test Clock (CKO)—Output.......................................................................2-45

2.2.7.2 Hard Reset (HRST

)—Input.......................................................................2-45

2.2.7.3 Nonmaskable Interrupt (NMI)—Input ...................................................... 2-45

2.2.7.4 Quiesce Acknowledge (QACK

)—Output.................................................2-46

2.2.7.5 Quiesce Request (QREQ

)—Input.............................................................. 2-46

2.2.7.6 Suspend (SUSPEND)—Input.................................................................... 2-46

2.2.7.7 System Clock (SYSCLK)—Input.............................................................. 2-47

2.2.8 IEEE 1149.1 Interface Signals.......................................................................2-47

2.2.8.1 JTAG Test Clock (TCK)—Input................................................................ 2-47

2.2.8.2 JTAG Test Data Output (TDO)—Output................................................... 2-47

2.2.8.3 JTAG Test Data Input (TDI)—Input ......................................................... 2-47

2.2.8.4 JTAG Test Mode Select (TMS)—Input..................................................... 2-48

2.2.8.5 JTAG Test Reset (TRST)—Input ..............................................................2-48

2.2.9 Configuration Signals....................................................................................2-48

2.2.9.1 501-Mode (BCTL0)—Input ...................................................................... 2-48

2.2.9.2 Address Map (DBG0)—Input ................................................................... 2-49

2.2.9.3 ROM Bank 0 Data Path Width (FOE)—Input........................................... 2-49

2.2.9.4 60x Clock Phase (LBCLAIM)—Input ...................................................... 2-49

2.2.9.5 Clock Mode (PLL[0–3])—Input................................................................ 2-49

2.2.9.6 ROM Location (RCS0)—Input ................................................................. 2-50

2.3 Clocking............................................................................................................. 2-50

Chapter 3

Device Programming

3.1 Address Maps ......................................................................................................3-1

3.1.1 Address Map A................................................................................................ 3-1

3.1.2 Address Map B ................................................................................................ 3-8

3.1.3 Emulation Mode Address Map...................................................................... 3-11

3.2 Configuration Registers.....................................................................................3-14

3.2.1 Configuration Register Access ...................................................................... 3-14

3.2.1.1 Configuration Register Access in Little-Endian Mode ............................. 3-14

3.2.1.2 Configuration Register Access in Big-Endian Mode ................................ 3-16

3.2.2 Configuration Register Summary.................................................................. 3-17

3.2.3 PCI Registers ................................................................................................. 3-21

3.2.3.1 PCI Command Register............................................................................. 3-22

3.2.3.2 PCI Status Register.................................................................................... 3-24

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3.2.4 Performance Monitor Registers..................................................................... 3-25

3.2.4.1 Performance Monitor Command Register (CMDR)—0x48 ..................... 3-25

3.2.4.2 Performance Monitor Mode Control Register (MMCR)—0x4C..............3-26

3.2.4.3 Performance Monitor Counters (PMC0, PMC1, PMC2, PMC3)—

0x50, 0x54, 0x58, 0x5C......................................................................... 3-27

3.2.5 Power Management Configuration Registers (PMCRs)................................ 3-28

3.2.6 Output Driver Control Register (ODCR)—0x73...........................................3-31

3.2.7 Error Handling Registers............................................................................... 3-33

3.2.7.1 ECC Single-Bit Error Registers................................................................. 3-33

3.2.7.2 Error Enabling Registers............................................................................ 3-34

3.2.7.3 Error Detection Registers ..........................................................................3-36

3.2.7.4 Error Status Registers ................................................................................ 3-38

3.2.8 Memory Interface Configuration Registers...................................................3-40

3.2.8.1 Memory Boundary Registers..................................................................... 3-40

3.2.8.2 Memory Bank Enable Register.................................................................. 3-44

3.2.8.3 Memory Page Mode Register....................................................................3-45

3.2.8.4 Memory Control Configuration Registers................................................. 3-46

3.2.9 Processor Interface Configuration Registers ................................................. 3-56

3.2.10 Alternate OS-Visible Parameters Registers................................................... 3-66

3.2.11 Emulation Support Configuration Registers.................................................. 3-68

3.2.11.1 Modified Memory Status Register............................................................. 3-70

3.2.12 External Configuration Registers................................................................... 3-71

Chapter 4

Processor Bus Interface

4.1 MPC106 Processor Bus Configuration................................................................ 4-1

4.1.1 Single-Processor System Configuration.......................................................... 4-1

4.1.2 Multiprocessor System Configuration............................................................. 4-1

4.1.3 Multiprocessor System Configuration with External L2 Cache...................... 4-3

4.1.4 Processor Bus Interface Configuration Registers............................................4-5

4.2 Processor Bus Protocol Overview ....................................................................... 4-5

4.2.1 MPC106 Arbitration........................................................................................4-6

4.2.2 Address Pipelining and Split-Bus Transactions............................................... 4-7

4.3 Address Tenure Operations..................................................................................4-8

4.3.1 Address Arbitration.......................................................................................... 4-8

4.3.2 Address Transfer Attribute Signals................................................................ 4-10

4.3.2.1 Transfer Type Signal Encodings................................................................ 4-10

4.3.2.2 TBST and TSIZ[0–2] Signals and Size of Transfer ..................................4-13

4.3.2.3 Burst Ordering During Data Transfers ...................................................... 4-13

4.3.2.4 Effect of Alignment on Data Transfers...................................................... 4-14

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4.3.3 Address Transfer Termination ....................................................................... 4-16

4.3.3.1 MPC106 Snoop Response ......................................................................... 4-16

4.3.3.2 Address Tenure Timing Configuration......................................................4-17

4.4 Data Tenure Operations ..................................................................................... 4-18

4.4.1 Data Bus Arbitration......................................................................................4-18

4.4.2 Data Bus Transfers and Normal Termination................................................4-18

4.4.3 Data Tenure Timing Configurations..............................................................4-19

4.4.4 Data Bus Termination by TEA ...................................................................... 4-19

4.4.5 60x Local Bus Slave Support.........................................................................4-20

4.4.5.1 60x Local Bus Slave Timing .....................................................................4-21

Chapter 5

Secondary Cache Interface

5.1 L2 Cache Configurations..................................................................................... 5-2

5.1.1 Write-Back Cache Operation........................................................................... 5-2

5.1.2 Write-Through Cache Operation .....................................................................5-2

5.1.3 Synchronous Burst SRAMs.............................................................................5-2

5.1.4 Pipelined Burst SRAMs...................................................................................5-4

5.1.5 Asynchronous SRAMs .................................................................................... 5-6

5.1.6 Two-Bank Support........................................................................................... 5-7

5.2 Internal L2 Cache Controller Operation.............................................................. 5-8

5.2.1 L2 Cache Addressing....................................................................................... 5-8

5.2.2 L2 Cache Line Status....................................................................................... 5-9

5.2.3 L2 Cache Tag Lookup......................................................................................5-9

5.2.4 L2 Cache Castout Operations........................................................................ 5-10

5.2.5 L2 Cache Parity ............................................................................................. 5-10

5.2.6 L2 Cache Interface and Interrupt Vector Relocation..................................... 5-11

5.3 L2 Cache Response to Bus Operations.............................................................. 5-11

5.3.1 Write-Back L2 Cache Response.................................................................... 5-11

5.3.2 Write-Through L2 Cache Response............................................................... 5-18

5.4 L2 Cache Interface Parameters.......................................................................... 5-21

5.4.1 L2 Cache Interface Control Parameters ........................................................ 5-22

5.4.2 L2 Cache Interface Initialization Parameters................................................. 5-22

5.4.2.1 CF_L2_HIT_DELAY................................................................................5-24

5.4.2.2 CF_DOE.................................................................................................... 5-24

5.4.2.3 CF_WDATA .............................................................................................. 5-24

5.4.2.4 CF_WMODE............................................................................................. 5-25

5.4.2.4.1 Normal Write Timing without Partial Update (CF_WMODE = 0)....... 5-25

5.4.2.4.2 Normal Write Timing (CF_WMODE = 1)............................................5-26

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5.4.2.4.3 Delayed Write Timing (CF_WMODE = 2)........................................... 5-27

5.4.2.4.4 Early Write Timing (CF_WMODE = 3)................................................ 5-28

5.5 L2 Cache Interface Timing Examples ...............................................................5-29

5.5.1 Synchronous Burst SRAM L2 Cache Timing ...............................................5-29

5.5.1.1 L2 Cache Read Hit Timing........................................................................ 5-29

5.5.1.2 L2 Cache Write Hit Timing ....................................................................... 5-31

5.5.1.3 L2 Cache Line Update Timing .................................................................. 5-32

5.5.1.4 L2 Cache Line Castout Timing.................................................................. 5-33

5.5.1.5 L2 Cache Hit Timing Following PCI Read Snoop.................................... 5-35

5.5.1.6 L2 Cache Line Push Timing Following PCI Write Snoop ........................ 5-36

5.5.1.7 L2 Cache Line Invalidate Timing Following PCI

Write-with-Invalidate Snoop ................................................................. 5-37

5.5.2 Asynchronous SRAM L2 Cache Timing....................................................... 5-38

5.5.2.1 Burst Read Timing..................................................................................... 5-38

5.5.2.2 L2 Cache Burst Read Line Update Timing ............................................... 5-39

5.5.2.3 Burst Write Timing.................................................................................... 5-40

5.6 External L2 Cache Controller Operation........................................................... 5-41

5.6.1 External L2 Cache Operation ........................................................................5-42

5.6.2 External L2 Cache Controller Interface Parameters...................................... 5-42

Chapter 6

Memory Interface

6.1 Overview..............................................................................................................6-1

6.2 Memory Interface Signal Buffering..................................................................... 6-2

6.2.1 Flow-Through Buffers..................................................................................... 6-3

6.2.2 Transparent Latch Buffers ............................................................................... 6-4

6.2.3 Registered Buffers ........................................................................................... 6-5

6.2.4 Parity/ECC Path Read Control ........................................................................ 6-8

6.3 Memory Interface Signal Connections ................................................................ 6-8

6.4 DRAM/EDO Interface Operation...................................................................... 6-10

6.4.1 Supported DRAM/EDO Organizations......................................................... 6-12

6.4.2 DRAM/EDO Address Multiplexing.............................................................. 6-13

6.4.3 DRAM/EDO Power-On Initialization........................................................... 6-15

6.4.3.1 Supported Memory Interface Configurations............................................ 6-16

6.4.4 DRAM/EDO Interface Timing ...................................................................... 6-16

6.4.5 DRAM/EDO Burst Wrap............................................................................... 6-23

6.4.6 DRAM/EDO Latency.................................................................................... 6-23

6.4.7 DRAM/EDO Page Mode Retention .............................................................. 6-24

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6.4.8 DRAM/EDO Parity and RMW Parity...........................................................6-25

6.4.8.1 RMW Parity Latency Considerations........................................................ 6-25

6.4.9 Error Checking and Correction—ECC.......................................................... 6-26

6.4.9.1 DRAM/EDO Interface Timing with ECC................................................. 6-26

6.4.10 DRAM/EDO Refresh..................................................................................... 6-30

6.4.10.1 DRAM/EDO Refresh Timing.................................................................... 6-30

6.4.10.2 DRAM/EDO Refresh and Power Saving Modes....................................... 6-31

6.4.10.2.1 Self-Refresh in Sleep and Suspend Modes............................................ 6-32

6.4.10.2.2 RTC Refresh in Suspend Mode............................................................. 6-33

6.4.11 Processor-to-DRAM Transaction Examples.................................................. 6-33

6.4.12 PCI-to-DRAM Transaction Examples........................................................... 6-37

6.5 SDRAM Interface Operation............................................................................. 6-44

6.5.1 Supported SDRAM Organizations ................................................................ 6-46

6.5.2 SDRAM Address Multiplexing.....................................................................6-47

6.5.3 SDRAM Burst and Single-Beat Transactions................................................ 6-49

6.5.4 SDRAM Page Mode Retention......................................................................6-49

6.5.5 SDRAM Power-On Initialization .................................................................. 6-51

6.5.6 JEDEC Standard SDRAM Interface Commands........................................... 6-53

6.5.7 SDRAM Interface Timing ............................................................................. 6-55

6.5.7.1 Processor-to-SDRAM Transaction Examples ........................................... 6-55

6.5.7.2 SDRAM Mode-Set Command Timing...................................................... 6-60

6.5.8 SDRAM Parity and RMW Parity .................................................................. 6-61

6.5.8.1 RMW Parity Latency Considerations........................................................ 6-62

6.5.9 External Error Checking Module (ECM) Support......................................... 6-62

6.5.9.1 External ECM Timing Examples............................................................... 6-64

6.5.10 SDRAM Refresh............................................................................................ 6-66

6.5.10.1 SDRAM Refresh Timing........................................................................... 6-68

6.5.10.2 SDRAM Refresh and Power Saving Modes.............................................. 6-68

6.6 ROM/Flash Interface Operation ........................................................................6-70

6.6.1 ROM/Flash Cacheability ...............................................................................6-73

6.6.2 64-Bit ROM/Flash Interface Timing .............................................................6-73

6.6.3 Processor Read from 64-Bit ROM Transaction Examples............................ 6-75

6.6.4 Eight-Bit ROM/Flash Interface Timing......................................................... 6-78

6.6.5 Processor Read from 8-Bit ROM Transaction Examples.............................. 6-79

6.6.6 ROM/Flash Interface Write Operations......................................................... 6-83

6.6.6.1 ROM/Flash Interface Write Timing........................................................... 6-83

6.6.6.2 Processor Write to 8-Bit ROM Transaction Example ............................... 6-84

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xii MPC106 PCI/Bridge/Memory Controller User’s Manual MOTOROLA

Chapter 7

PCI Bus Interface

7.1 PCI Interface Overview ....................................................................................... 7-1

7.1.1 MPC106 as a PCI Master.................................................................................7-2

7.1.2 MPC106 as a PCI Target.................................................................................. 7-2

7.2 PCI Bus Arbitration .............................................................................................7-3

7.3 PCI Bus Protocol ................................................................................................. 7-3

7.3.1 Basic Transfer Control..................................................................................... 7-3

7.3.2 PCI Bus Commands.........................................................................................7-4

7.3.3 Addressing.......................................................................................................7-6

7.3.3.1 Memory Space Addressing..........................................................................7-6

7.3.3.2 I/O Space Addressing .................................................................................. 7-7

7.3.3.3 Configuration Space Addressing.................................................................7-7

7.3.4 Device Selection.............................................................................................. 7-7

7.3.5 Byte Alignment................................................................................................7-8

7.3.6 Bus Driving and Turnaround ........................................................................... 7-8

7.4 PCI Bus Transactions...........................................................................................7-9

7.4.1 PCI Read Transactions..................................................................................... 7-9

7.4.2 PCI Write Transactions.................................................................................. 7-10

7.4.3 Transaction Termination................................................................................ 7-11

7.4.3.1 Master-Initiated Termination..................................................................... 7-11

7.4.3.2 Target-Initiated Termination...................................................................... 7-12

7.4.4 Fast Back-to-Back Transactions .................................................................... 7-14

7.4.5 Configuration Cycles..................................................................................... 7-15

7.4.5.1 The PCI Configuration Space Header ....................................................... 7-15

7.4.5.2 Accessing the PCI Configuration Space.................................................... 7-17

7.4.6 Other Bus Transactions.................................................................................. 7-21

7.4.6.1 Interrupt Acknowledge Transactions......................................................... 7-21

7.4.6.2 Special-Cycle Transactions........................................................................ 7-22

7.5 Exclusive Access ............................................................................................... 7-23

7.5.1 Starting an Exclusive Access......................................................................... 7-23

7.5.2 Continuing an Exclusive Access.................................................................... 7-24

7.5.3 Completing an Exclusive Access................................................................... 7-24

7.5.4 Attempting to Access a Locked Target.......................................................... 7-24

7.5.5 Exclusive Access and the MPC106............................................................... 7-24

7.6 PCI Error Functions........................................................................................... 7-25

7.6.1 PCI Parity.......................................................................................................7-25

7.6.2 Error Reporting.............................................................................................. 7-26

7.7 MPC106-Implemented PCI Sideband Signals................................................... 7-27

7.7.1 ISA_MASTER............................................................................................... 7-27

7.7.2 FLSHREQ and MEMACK............................................................................7-27

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7.8 Emulation Support............................................................................................. 7-28

7.8.1 PCI Address Decoding................................................................................... 7-28

7.8.2 Interrupt Vector Relocation............................................................................7-28

7.8.3 Modified Memory Status Register.................................................................7-28

7.8.4 Curious Code Protection................................................................................ 7-31

7.9 Processor-to-PCI Transaction Examples ...........................................................7-31

Chapter 8

Internal Control

8.1 Internal Buffers.................................................................................................... 8-1

8.1.1 60x Processor/System Memory Buffers .......................................................... 8-2

8.1.2 60x Processor/PCI Buffers...............................................................................8-3

8.1.2.1 Processor-to-PCI-Read Buffer (PRPRB)..................................................... 8-4

8.1.2.2 Processor-to-PCI-Write Buffers (PRPWBs)................................................ 8-5

8.1.3 PCI/System Memory Buffers........................................................................... 8-6

8.1.3.1 PCI-to-System-Memory-Read Buffer (PCMRB)........................................ 8-7

8.1.3.1.1 Speculative PCI Reads from System Memory........................................ 8-8

8.1.3.2 PCI-to-System-Memory-Write Buffers (PCMWBs)................................... 8-9

8.2 Internal Arbitration .............................................................................................. 8-9

Chapter 9

Error Handling

9.1 Priority of Externally-Generated Interrupts......................................................... 9-2

9.2 Interrupt and Error Signals .................................................................................. 9-3

9.2.1 System Reset.................................................................................................... 9-3

9.2.2 60x Processor Bus Error Signals .....................................................................9-3

9.2.2.1 Machine Check (MCP)................................................................................ 9-3

9.2.2.2 Transfer Error Acknowledge (TEA)............................................................ 9-4

9.2.3 PCI Bus Error Signals...................................................................................... 9-5

9.2.3.1 System Error (SERR) .................................................................................. 9-5

9.2.3.2 Parity Error (PERR)..................................................................................... 9-5

9.2.3.3 Nonmaskable Interrupt (NMI)..................................................................... 9-5

9.3 Error Reporting.................................................................................................... 9-6

9.3.1 60x Processor Interface....................................................................................9-7

9.3.1.1 Unsupported 60x Bus Transaction Error ..................................................... 9-7

9.3.1.2 Illegal L2 Copyback Error........................................................................... 9-7

9.3.1.3 Flash Write Error ......................................................................................... 9-7

9.3.2 Memory Interface ............................................................................................ 9-7

9.3.2.1 System Memory Read Data Parity Error..................................................... 9-8

9.3.2.2 L2 Cache Read Data Parity Error................................................................ 9-8

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9.3.2.3 System Memory ECC Error......................................................................... 9-8

9.3.2.3.1 External ECM Errors............................................................................... 9-9

9.3.2.4 System Memory Select Error....................................................................... 9-9

9.3.2.5 System Memory Refresh Overflow Error.................................................... 9-9

9.3.3 PCI Interface....................................................................................................9-9

9.3.3.1 Address Parity Error.................................................................................. 9-10

9.3.3.2 Data Parity Error........................................................................................ 9-10

9.3.3.3 Master-Abort Transaction Termination ..................................................... 9-10

9.3.3.4 Received Target-Abort Error ..................................................................... 9-11

9.3.3.5 NMI (Nonmaskable Interrupt)...................................................................9-12

9.4 Interrupt Latencies............................................................................................. 9-12

9.5 Example Signal Connections............................................................................. 9-12

Chapter 10

Performance Monitor

10.1 Performance Monitor Operation........................................................................ 10-1

10.2 Performance Monitor Events............................................................................. 10-2

10.2.1 Command Type 0 Events............................................................................... 10-3

10.2.2 Command Type 1 Events............................................................................... 10-4

10.2.3 Threshold Events ........................................................................................... 10-8

10.2.4 Burstiness.......................................................................................................10-8

10.2.5 Counter Overflow.......................................................................................... 10-9

Appendix A

Power Management

A.1 MPC106 Power Modes....................................................................................... A-1

A.1.1 MPC106 Power Mode Transition................................................................... A-1

A.1.2 Full-On Mode ................................................................................................. A-3

A.1.3 Doze Mode...................................................................................................... A-3

A.1.4 Nap Mode ....................................................................................................... A-3

A.1.5 Sleep Mode..................................................................................................... A-4

A.1.6 Suspend Mode................................................................................................. A-5

A.2 MPC106 Power Management Support ............................................................... A-6

A.2.1 Power Management Configuration Registers................................................. A-6

A.2.2 Clock Configuration ....................................................................................... A-6

A.2.3 PCI Address Bus Decoding ............................................................................ A-7

A.2.4 PCI Bus Special-Cycle Operations................................................................. A-7

A.2.5 Processor Bus Request Monitoring................................................................. A-7

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A.2.6 Memory Refresh Operations in Sleep/Suspend Mode.................................... A-8

A.2.7 PCI Bus Parking in Sleep and Suspend Modes .............................................. A-8

A.2.8 Device Drivers................................................................................................ A-8

Appendix B

Bit and Byte Ordering

B.1 Big-Endian Mode.................................................................................................B-1

B.2 Little-Endian Mode..............................................................................................B-5

Appendix C

JTAG/Testing Support

C.1 JTAG Interface Description.................................................................................C-1

C.1.1 JTAG Signals...................................................................................................C-2

C.1.2 JTAG Registers and Scan Chains....................................................................C-2

C.1.2.1 Bypass Register ...........................................................................................C-2

C.1.2.2 Boundary-Scan Registers.............................................................................C-2

C.1.2.3 Instruction Register......................................................................................C-3

C.1.3 TAP Controller ................................................................................................C-3

Appendix D

Initialization Example

Appendix E

Revision History

E.1 Revision Changes From Revision 1 to Revision 2............................................. D-1

Glossary of Terms and Abbreviations

Index

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Figures

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MOTOROLA Figures xvii

Figures

1-1 MPC106 Block Diagram............................................................................................. 1-2

2-1 MPC106 Signal Groupings......................................................................................... 2-3

2-2 SYSCLK Input with Internal Multiples.................................................................... 2-50

3-1 Address Map A (Contiguous Map)............................................................................. 3-4

3-2 Address Map A (Discontiguous Map) ........................................................................ 3-5

3-3 PCI Memory Map (Address Map A) .......................................................................... 3-6

3-4 PCI I/O Map (Address Map A)...................................................................................3-7

3-5 Address Map B.......................................................................................................... 3-10

3-6 Emulation Mode Address Map ................................................................................. 3-13

3-7 MPC106 Configuration Space.................................................................................. 3-21

3-8 PCI Command Register ............................................................................................ 3-22

3-9 PCI Status Register ................................................................................................... 3-24

3-10 Performance Monitor Command Register (CMDR)—0x48..................................... 3-25

3-11 Performance Monitor Mode Control Register (MMCR)—0x4C ............................. 3-26

3-12 Performance Monitor Counter (PMCn)....................................................................3-28

3-13 Power Management Configuration Register 1 (PMCR1)......................................... 3-28

3-14 Power Management Configuration Register 2 (PMCR2)......................................... 3-30

3-15 Output Driver Control Register (ODCR)—0x73...................................................... 3-31

3-16 ECC Single-Bit Error Counter Register—0xB8....................................................... 3-33

3-17 ECC Single-Bit Error Trigger Register—0xB9........................................................ 3-33

3-18 Error Enabling Register 1 (ErrEnR1)........................................................................ 3-34

3-19 Error Enabling Register 2 (ErrEnR2)........................................................................ 3-35

3-20 Error Detection Register 1 (ErrDR1)—0xC1 ........................................................... 3-36

3-21 Error Detection Register 2 (ErrDR2)—0xC5 ........................................................... 3-37

3-22 60x Bus Error Status Register—0xC3 ...................................................................... 3-38

3-23 PCI Bus Error Status Register—0xC7......................................................................3-39

3-24 60x/PCI Error Address Register—0xC8................................................................... 3-39

3-25 Memory Starting Address Register 1—0x80............................................................ 3-40

3-26 Memory Starting Address Register 2—0x84............................................................ 3-41

3-27 Extended Memory Starting Address Register 1—0x88............................................ 3-41

3-28 Extended Memory Starting Address Register 2—0x8C........................................... 3-41

3-29 Memory Ending Address Register 1—0x90............................................................. 3-42

3-30 Memory Ending Address Register 2—0x94............................................................. 3-42

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xviii MPC106 PCI/Bridge/Memory Controller User’s Manual MOTOROLA

3-31 Extended Memory Ending Address Register 1—0x98............................................. 3-43

3-32 Extended Memory Ending Address Register 2—0x9C............................................3-43

3-33 Memory Bank Enable Register—0xA0....................................................................3-44

3-34 Memory Page Mode Register—0xA3....................................................................... 3-45

3-35 Memory Control Configuration Register 1 (MCCR1)—0xF0 ................................. 3-46

3-36 Memory Control Configuration Register 2 (MCCR2)—0xF4 ................................. 3-49

3-37 Memory Control Configuration Register 3 (MCCR3)—0xF8 ................................. 3-51

3-38 Memory Control Configuration Register 4 (MCCR4)—0xFC................................. 3-54

3-39 Processor Interface Configuration Register 1 (PICR1)—0xA8................................ 3-57

3-40 Processor Interface Configuration Register 2 (PICR2)—0xAC............................... 3-61

3-41 Alternate OS-Visible Parameters Register 1—0xBA ............................................... 3-66

3-42 Alternate OS-Visible Parameters Register 2—0xBB................................................ 3-67

3-43 Emulation Support Configuration Register 1 (ESCR1)—0xE0 ............................... 3-68

3-44 Emulation Support Configuration Register 2 (ESCR2)—0xE8 ............................... 3-69

3-45 Modified Memory Status Register—0xE4/0xEC ..................................................... 3-70

3-46 External Configuration Register 1—Port 0x092....................................................... 3-71

3-47 External Configuration Register 2—Port 0x81C...................................................... 3-72

3-48 External Configuration Register 3—Port 0x850....................................................... 3-72

4-1 Single-Processor Configuration with Optional L2 Cache........................................... 4-2

4-2 Multiprocessor Configuration.....................................................................................4-3

4-3 Multiprocessor Configuration with External L2 Cache.............................................. 4-4

4-4 Overlapping Tenures on the 60x Bus for a Single-Beat Transfer ............................... 4-6

4-5 Address Bus Arbitration with Dual Processors........................................................... 4-9

4-6 Address Pipelining.................................................................................................... 4-10

4-7 Snooped Address Transaction with ARTRY and L1 Cache Copyback.................... 4-17

4-8 Single-Beat and Burst Data Transfers....................................................................... 4-19

4-9 Data Tenure Terminated by Assertion of TEA ......................................................... 4-20

4-10 Local Bus Slave Transaction.....................................................................................4-23

4-11 60x Bus State Diagram.............................................................................................. 4-24

5-1 Typical L2 Cache Using Burst SRAM (Write-Back).................................................. 5-3

5-2 Typical L2 Cache Using Pipelined Burst SRAM (Write-Back, ADSC Only)............ 5-4

5-3 Alternate L2 Cache Using Pipelined Burst SRAM (Write-Back

Using ADSP).......................................................................................................... 5-5

5-4 Typical L2 Cache Using Asynchronous SRAM (Write-Back)................................... 5-6

5-5 512-Kbyte, Two-Bank, L2 Cache Using Synchronous Burst SRAM (Write-Back)... 5-7

5-6 1-Mbyte, Two-Bank, L2 Cache Using Pipelined Burst SRAM

(Write-Back, ADSC Only)..................................................................................... 5-8

5-7 HIT and DIRTY_IN Delay Configuration................................................................ 5-24

5-8 External Byte Decode Logic Requiring CF_WMODE = 1 ...................................... 5-26

5-9 Normal Write Timing (CF_WMODE = 0 or 1)........................................................ 5-26

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