Texas Instruments TMS320C6416 Seamless CVE Model (Rev. B) User guide

Brand: Texas Instruments

Model: TMS320C6416 Seamless CVE Model (Rev. B)

Category: Supplementary music equipment

Type: User guide

TMS320C6416

Seamless CVE Model

User’s Guide

Literature Number: SPRU548B

May 2002

Printed on Recycled Paper

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vRead This First

Preface

Read This First

About This Manual

This document contains the following chapters:

Chapter one describes some of the features of the TMS320C6416 Seamless

CVE model, including features supported, device pins, accuracy and known

limitations.

The second chapter takes you through the tutorials provided with the Seam-

less CVE model.

Notational Conventions

This document uses the following conventions.

- Program listings, program examples, and interactive displays are shown

in a special typeface similar to a typewriter’s. Examples use a bold

version of the special typeface for emphasis; interactive displays use a

bold version of the special typeface to distinguish commands that you

enter from items that the system displays (such as prompts, command

output, error messages, etc.).

Here is a sample program listing:

0011 0005 0001 .field 1, 2

0012 0005 0003 .field 3, 4

0013 0005 0006 .field 6, 3

0014 0006 .even

Here is an example of a system prompt and a command that you might

enter:

C: csr –a /user/ti/simuboard/utilities

- In syntax descriptions, the instruction, command, or directive is in a bold

typeface font and parameters are in an italic typeface. Portions of a syntax

that are in bold should be entered as shown; portions of a syntax that are

in italics describe the type of information that should be entered. Here is

an example of a directive syntax:

.asect ”section name”, address

Notational Conventions

.asect is the directive. This directive has two parameters, indicated by sec-

tion name and address. When you use .asect, the first parameter must be

an actual section name, enclosed in double quotes; the second parameter

must be an address.

- Square brackets ( [ and ] ) identify an optional parameter. If you use an

optional parameter, you specify the information within the brackets; you

don’t enter the brackets themselves. Here’s an example of an instruction

that has an optional parameter:

LALK 16–bit constant [, shift]

The LALK instruction has two parameters. The first parameter, 16-bit con-

stant, is required. The second parameter, shift, is optional. As this syntax

shows, if you use the optional second parameter, you must precede it with

a comma.

Square brackets are also used as part of the pathname specification for

VMS pathnames; in this case, the brackets are actually part of the path-

name (they are not optional).

- Braces ( { and } ) indicate a list. The symbol | (read as or) separates items

within the list. Here’s an example of a list:

{ * | *+ | *– }

This provides three choices: *, *+, or *–.

Unless the list is enclosed in square brackets, you must choose one item

from the list.

- Some directives can have a varying number of parameters. For example,

the .byte directive can have up to 100 parameters. The syntax for this di-

rective is:

.byte value

[, ... , value

]

This syntax shows that .byte must have at least one value parameter, but

you have the option of supplying additional value parameters, separated

by commas.

Information About Cautions and Warnings

viiRead This First

Information About Cautions and Warnings

This book may contain cautions and warnings.

This is an example of a caution statement.

A caution statement describes a situation that could potentially

damage your software or equipment.

This is an example of a warning statement.

A warning statement describes a situation that could potentially

cause harm to you

The information in a caution or a warning is provided for your protection.

Please read each caution and warning carefully.

Trademarks

TI is a trademark of Texas Instruments Incorporated.

Microsoft is a registered trademark of Microsoft Corporation.

Windows and Windows NT are registered trademarks of Microsoft Corporation.

Seamless CVE is a trademark of Mentor Graphics Corporation.

Contents

1 Features of the TMS320C6416 Seamless CVE 1-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Describes the processor support package, methods for invoking, supported devices, simula-

tion features, and known limitations of the TMS320C6416 Seamless CVE model.

1.1 Processor Support Package 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1.1 Contents 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1.2 Licensing Information 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1.3 Supported Platforms 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1.4 Versions 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 How to Invoke 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2.1 Setting Up the Seamless CVE 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2.2 Setting Up the ISS 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2.3 Setting up the BIM 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3 Supported TMS320C6416 Device Pins 1-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4 Simulation Features 1-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4.1 BootLoad 1-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4.2 Reset Sequence 1-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4.3 Clock Behavior 1-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.5 Seamless Features Supported 1-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.5.1 Seamless Optimization 1-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.5.2 HW Break 1-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.5.3 Loading COFF into External Memory 1-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.6 Simulation Accuracy 1-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.7 Known Limitations 1-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 TMS320C6416 Seamless CVE Model Tutorial 2-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contains tutorials that allow you to explore some of the capabilities of the TMS320C6416

Seamless CVE model.

2.1 Hooking up the Denali SRAM 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.1 Connecting the TMS320C6416 Device and a Denali SRAM Model 2-2. . . . . . . . .

2.1.2 Performing Seamless Optimizations 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.3 Performing COFF Load into External Memory 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 Using the Serial Port 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.1 Using the Serial Port for Transmission and Reception 2-4. . . . . . . . . . . . . . . . . . . .

2.2.2 Generating Serial Port Events 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3 Simulating External Interrupts 2-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contents

2.3.1 Using External Interrupts 2-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4 Using the HPI 2-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4.1 Performing HPI Bootload 2-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4.2 Performing HOST Reads and Writes 2-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5 Using the Utopia 2-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5.1 Performing Read and Write of an ATM Cell 2-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6 Using the Hardware/Software Synchronization Feature 2-10. . . . . . . . . . . . . . . . . . . . . . . . .

2.6.1 How to Use the Synchronization Feature 2-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6.2 Performing SYNCHRONIZATION_ON/_OFF During EMIF Transactions 2-10. . .

2.6.3 Synchronization Feature on External Interrupt 2-11. . . . . . . . . . . . . . . . . . . . . . . . . .

2.7 Using Host Port Interface and Utopia On/Off Switch 2-12. . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.7.1 How to Use the Switching Feature 2-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.8 Using the GPIO 2-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.8.1 Generating EDMA Events and CPU Interrupts Using GPIO 2-13. . . . . . . . . . . . . .

2.9 Using the PCI 2-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.9.1 Performing the PCI Bootload 2-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.9.2 lPerforming PCI Slave Reads/Writes 2-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.9.3 Performing PCI Master Reads/Writes 2-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-1

FeaturesĂofĂtheĂTMS320C6416ĂSeamlessĂCVEĂ

This chapter describes the processor support package, methods for invoking,

supported devices, simulation features, simulation accuracy, and known limi-

tations of the TMS320C6416 Seamless CVE model.

Topic Page

1.1 Processor Support Package 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 How to Invoke 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3 Supported TMS320C6416 Device Pins 1-6. . . . . . . . . . . . . . . . . . . . . . . . . .

1.4 Simulation Features 1-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.5 Seamless Features Supported 1-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.6 Simulation Accuracy 1-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.7 Known Limitations 1-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter 1

Processor Support Package

1-2

1.1 Processor Support Package

The TMS320C6416 Seamless model simulates most of the pins of the

TMS320C6416 device accurately. The TMS320C6416 Processor Support

Package contains the Seamless model and all associated files required to run

in a Mentor Seamless CVE environment.

Code Composer Studio IDE, the debugger interface for the TMS320C6416

ISS, is not shipped as part of this package. Please contact Texas Instruments

to obtain a copy.

1.1.1 Contents

The package contains the following

- TMS320C6416 Seamless Model

- TMS320C6416 Seamless CVE Model User’s Guide

- Code Composer Studio GEL files that implement some of the standard

ISS commands to Seamless

- Binaries and Library files needed by the TMS320C6416 Seamless model

for execution

- Examples that help in using the various features of the TMS320C6416

Seamless model

1.1.2 Licensing Information

The TMS320C6416 Seamless model is a licensed product. Licenses need to

be obtained for two different entities of the product

- TMS320C6416 Seamless CVE model

- Code Composer Studio IDE on Solaris

Licenses for the model can be obtained by contacting Mentor Graphics Sup-

port. Please contact Texas Instruments to obtain licenses for Code Composer

Studio IDE.

1.1.3 Supported Platforms

The model is supported only on the UNIX–Solaris platform.

1.1.4 Versions

The following Solaris versions are supported:

Processor Support Package

1-3Features of the TMS320C6416 Seamless CVE

SUNOS 5.5.1 (SOLARIS 2.5.1)

J SUNOS 5.6 (SOLARIS 2.6)

The model supports Seamless CVE version 4.1.

The model supports ModelSim version 5.4c.

The model works with Code Composer Studio IDE V1.1 and V2.0 on the UNIX

platform.

How to Invoke

1-4

1.2 How to Invoke

This section details the steps to be performed to invoke the TMS320C6416

Seamless model. Please invoke the Seamless CVE executable only after the

ISS and BIM have been successfully set up, as seen in sections 1.2.2 and

NO TAG of this document.

1.2.1 Setting Up the Seamless CVE

Please refer the Mentor Graphics Seamless CVE User Guide for details as to

how to setup the Seamless CVE application.

The TMS320C6416 Seamless model is released as part of the Mentor Graph-

ics Seamless release tree.

1.2.2 Setting Up the ISS

1) Set the environment variable TI_PSP_DIR to the installation directory

2) Ensure that the location of cc_app (Code Composer Studio IDE) is in your

path.

3) Invoke cc_setup, select the tisimC64xx board and add to the system. For

more help, refer to the Code Composer Studio help.

4) Edit the board properties to select the simulator config file

simc6416seamless.cfg from the directory:

TI_PSP_DIR/isms/TMS320C6416/.

1.2.3 Setting up the BIM

1) Set the environment variable TI_PSP_DIR to the installation directory.

2) Set the environment variables CVE_HOME and MODELSIM.

3) Go to TI_PSP_DIR/isms/TMS320C6416/ and source the script

setup_tms320c6416

Sourcing this script will override the TI_PSP_DIR settings and point it to

CVE_HOME. If you do not source the script, you need to do the following set-

tings yourself:

- LD_LIBRARY_PATH settings

You need to set the LD_LIBRARY_PATH environment variable to include

H TI_PSP_DIR/isms/TMS320C6416,

How to Invoke

1-5Features of the TMS320C6416 Seamless CVE

H TI_PSP_DIR/lib/TMS320C6416, and

H TI_PSP_DIR/lib/TMS320C6416/VIP_MODEL/

VIP_END_USER_40/SunOS5/lib.

- VIPENV_VHD settings

You need to set the VIPENV_VHD environment variable to

H TI_PSP_DIR/lib/TMS320C6416/VIP_MODEL

- PATH settings.

You need to set the path to include the directories

H $(CVE_HOME}/bin, ${VIPENV_VHD}/SunOS5/bin

H ${VIPENV_VHD}/jre/SunOS5/bin

- VHDL GENERIC settings.

You need to set the VHDL generic ENDIAN_MODE. By default it is set to 1.

H 1 – little endian

H 0 – big endian

Supported TMS320C6416 Device Pins

1-6

1.3 Supported TMS320C6416 Device Pins

The following table summarizes the pins simulated by the TMS320C6416

Seamless Model.

Table 1–1. Pins Simulated by the TMS320C6416 Seamless Model

Pin Name Direction Width Supported Peripherals

CLKIN IN 1 X CLOCKING/PLL

CLKMODE IN 2–0 – CLOCKING/PLL

PLLV OUT 1 – CLOCKING/PLL

RESET IN 1 X SYSTEM CONTROL

PCI_EN IN 1 X SYSTEM CONTROL

MCBSP2_EN IN 1 X SYSTEM CONTROL

TINP IN 2–0 – TIMER

BARDY IN 1 X EMIFB (16 BIT EXTERNAL MEMORY INT)

BHOLD IN 1 – EMIFB (16 BIT EXTERNAL MEMORY INT)

BECLKIN IN 1 X EMIFB (16 BIT EXTERNAL MEMORY INT)

AARDY IN 1 X EMIFA (64 BIT EXTERNAL MEMORY INT)

AHOLD IN 1 – EMIFA (64 BIT EXTERNAL MEMORY INT)

AECLKIN IN 1 – EMIFA (64 BIT EXTERNAL MEMORY INT)

TCLK IN 1 – EMULATION CONTROL

TDI IN 1 – EMULATION CONTROL

TMS IN 1 – EMULATION CONTROL

TRST IN 1 – EMULATION CONTROL

UXCLK IN 1 X UTOPIA

URSOC IN 1 X UTOPIA

URENB IN 1 X UTOPIA

URDATA IN 7–0 X UTOPIA

CLKS0 IN 1 – MCBSP0

CLKS2_GP8 INOUT 1 X MCBSP2

DR0 IN 1 X MCBSP2

GP0 INOUT 1 X GPIO

GP1_CLKOUT4 INOUT 1 X SYSTEM CONTROL

GP2_CLKOUT6 INOUT 1 X SYSTEM CONTROL

NMI IN 1 X SYSTEM CONTROL

GP3 INOUT 1 X SYSTEM CONTROL

GP4_EINT4 INOUT 1 X SYSTEM CONTROL

GP5_EINT5 INOUT 1 X SYSTEM CONTROL

GP6_EINT6 INOUT 1 X SYSTEM CONTROL

GP7_EINT7 INOUT 1 X SYSTEM CONTROL

XSP_CS OUT 1 – PCI SERIAL EEPROM INTERFACE

TOUT OUT 2–0 – TIMER

BED INOUT 15–0 X EMIFB 16 BIT MEMORY INTERFACE

BEA INOUT 8–1 X EMIFB 16 BIT MEMORY INTERFACE

BEA09 INOUT 1 X EMIFB 16 BIT MEMORY INTERFACE

BEA10 INOUT 1 X EMIFB 16 BIT MEMORY INTERFACE

Supported TMS320C6416 Device Pins

1-7Features of the TMS320C6416 Seamless CVE

Table 1–1. Pins Simulated by the TMS320C6416 Seamless Model (Continued)

Pin Name Direction Width Supported Peripherals

BEA11_UTOPIAEN INOUT 1 X EMIFB 16 BIT MEMORY INTERFACE

BEA20_LENDIAN INOUT 1 X EMIFB 16 BIT MEMORY INTERFACE

BEA13_PCIEEAI INOUT 1 X EMIFB 16 BIT MEMORY INTERFACE

BEA14_BECLKINSEL0 INOUT 1 X EMIFB 16 BIT MEMORY INTERFACE

BEA15_BECLKINSEL1 INOUT 1 X EMIFB 16 BIT MEMORY INTERFACE

BEA12 INOUT 1 X EMIFB 16 BIT MEMORY INTERFACE

BEA17_AECLKINSEL1 INOUT 1 X EMIFB 16 BIT MEMORY INTERFACE

BEA18_BOOTMODE0 INOUT 1 X EMIFB 16 BIT MEMORY INTERFACE

BEA19_BOOTMODE1 INOUT 1 X EMIFB 16 BIT MEMORY INTERFACE

BEA16_AECLKINSEL0 INOUT 1 X EMIFB 16 BIT MEMORY INTERFACE

AEDH INOUT 31–0 X EMIFA 64 BIT MEMORY INTERFACE

AEDL INOUT 31–0 X EMIFA 64 BIT MEMORY INTERFACE

EMU INOUT 9–0 – EMULATION CONTROL

EMUCLK INOUT 1–0 – EMULATION CONTROL

UXCLAV OUT 1 X UTOPIA

UXENB IN 1 X UTOPIA

UXADDR0 IN 1 X UTOPIA

URCLAV OUT 1 X UTOPIA

URCLK IN 1 X UTOPIA

DX1_UXADDR4 INOUT 1 X MCBSP1/UTOPIA

FSX1_UXADDR3 INOUT 1 X MCBSP1/UTOPIA

FSR1_UXADDR2 INOUT 1 X MCBSP1/UTOPIA

DR1_UXADDR1 IN 1 X MCBSP1/UTOPIA

CLKX1_UXADDR4 INOUT 1 X MCBSP1/UTOPIA

CLKS1_UXADDR3 IN 1 X MCBSP1/UTOPIA

CLKR1_UXADDR2 INOUT 1 X MCBSP1/UTOPIA

URADDR IN 1–0 X UTOPIA

CLKX0 INOUT 1 X MCBSP0

CLKX2_XSPCLK INOUT 1 X MCBSP2/PCI

CLKR0 INOUT 1 X MCBSP0

CLKR2 INOUT 1 X MCBSP2

FSX0 INOUT 1 X MCBSP0

FSX2 INOUT 1 X MCBSP2

FSR0 INOUT 1 X MCBSP0

DR2_XSPDI IN 1 X MCBSP2/PCI

FSR2 INOUT 1 X MCBSP2

PCBE0 INOUT 1 – PCI

HDS2_PCBE1 INOUT 1 X HPI/PCI

HRW_PCBE2 INOUT 1 X HPI/PCI

GP9_PIDSEL INOUT 1 X GPIO/PCI

GP10_PCBE3 INOUT 1 X GPIO/PCI

GP11_PREQ INOUT 1 X GPIO/PCI

GP12_PGNT INOUT 1 X GPIO/PCI

GP13_PINTA INOUT 1 X GPIO/PCI

Supported TMS320C6416 Device Pins

1-8

Table 1–1. Pins Simulated by the TMS320C6416 Seamless Model (Continued)

Pin Name Direction Width Supported Peripherals

GP14_PCLK INOUT 1 X GPIO/PCI

GP15_PRST INOUT 1 X GPIO/PCI

HINT_PFRAME INOUT 1 X HPI/PCI

HCNTRL0_PSTOP INOUT 1 X HPI/PCI

HCNTRL1_PDEVSEL INOUT 1 X HPI/PCI

HHWIL_PTRDY INOUT 1 X HPI/PCI

HAS_PPAR INOUT 1 X HPI/PCI

HCS_PPERR INOUT 1 X HPI/PCI

HDS1_PSERR INOUT 1 X HPI/PCI

HRDY_PIRDY INOUT 1 X HPI/PCI

HD_AD INOUT 31–0 X HPI/PCI

BCE OUT 3–0 X EMIFB 16 BIT MEMORY INTERFACE

BBE OUT 1–0 X EMIFB 16 BIT MEMORY INTERFACE

BSDCAS OUT 1 X EMIFB 16 BIT MEMORY INTERFACE

BSDRAS OUT 1 X EMIFB 16 BIT MEMORY INTERFACE

BSOE3 OUT 1 – EMIFB 16 BIT MEMORY INTERFACE

BSDWE OUT 1 X EMIFB 16 BIT MEMORY INTERFACE

BHOLDA OUT 1 – EMIFB 16 BIT MEMORY INTERFACE

BBUSREQ OUT 1 – EMIFB 16 BIT MEMORY INTERFACE

BPDT OUT 1 – EMIFB 16 BIT MEMORY INTERFACE

BECLKOUT1 OUT 1 X EMIFB 16 BIT MEMORY INTERFACE

BECLKOUT2 OUT 1 – EMIFB 16 BIT MEMORY INTERFACE

AEA OUT 19–0 X EMIFA 64 BIT MEMORY INTERFACE

ACE OUT 3–0 X EMIFA 64 BIT MEMORY INTERFACE

ABE OUT 7–0 X EMIFA 64 BIT MEMORY INTERFACE

ASDCAS OUT 1 X EMIFA 64 BIT MEMORY INTERFACE

ASDRAS OUT 1 X EMIFA 64 BIT MEMORY INTERFACE

ASOE3 OUT 1 – EMIFA 64 BIT MEMORY INTERFACE

ASDWE OUT 1 X EMIFA 64 BIT MEMORY INTERFACE

ASCKE OUT 1 – EMIFA 64 BIT MEMORY INTERFACE

AHOLDA OUT 1 – EMIFA 64 BIT MEMORY INTERFACE

ABUSREQ OUT 1 – EMIFA 64 BIT MEMORY INTERFACE

APDT OUT 1 – EMIFA 64 BIT MEMORY INTERFACE

AECLKOUT1 OUT 1 X EMIFA 64 BIT MEMORY INTERFACE

AECLKOUT2 OUT 1 – EMIFA 64 BIT MEMORY INTERFACE

TDO OUT 1 – EMULATION CONTROL

UXSOC OUT 1 X UTOPIA

UXDATA OUT 7–0 X UTOPIA

DX0 OUT 1 X MCBSP0

DX2_XSPDO OUT 1 X MCBSP2/PCI

Simulation Features

1-9Features of the TMS320C6416 Seamless CVE

1.4 Simulation Features

1.4.1 BootLoad

The TMS320C6416 Seamless model supports device BOOTLOAD through

the EMIF pins.

At reset the model samples the pins BEA(19:18). The bootload operation hap-

pens depending on these pin values:

0 No Boot load. The model begins execution from the memory located at

address 0.

1 Boot load through HPI/PCI. The boot load is done through the Host Port

Interface (HPI) or the Peripheral Component Interconnect (PCI) port. The CPU

will wait till an external host initializes the CPU’s memory space as necessary

through the parallel port. Once this is done, the CPU begins execution from

address 0. Boot load happens through PCI if PCI is enabled, otherwise Boot-

load happens through HPI.

2 Boot load from EMIF B CE1 space start address (0x64000000). (ROM

boot process) The EDMA copies 1K bytes from the beginning of CE1 to ad-

dress 0, using default ROM timings. After the transfer the CPU begins execut-

ing from address 0.

3 Quick Boot Load. This feature is supported by the model and not the actual

device. In this mode, the bootload will be performed through debug reads of

1K bytes from memory address 0x90000000. Once this is complete, the CPU

begins execution from address 0.

1.4.2 Reset Sequence

The TMS320C6416 Seamless model performs reset by sampling the RESET

pin. The reset pulse width should be a minimum of 10 CPU clock cycles. The

RESET pin is not sampled after the first reset.

The device reset uses active low signal RESET. While the RESET is low the

model is held in its reset state. The control will be with the Hardware simulator.

Most output pins go to their default state. The rising edge on the RESET starts

the model run with the prescribed boot configuration. The following pins are

sampled at reset:

- BEA20_LENDIAN : The model will sample this pin to ensure that the In-

struction Set Simulator (ISS) and the Bus Interface Model (BIM) are oper-

ating in the same endian. A ’1’ on this pin will mean that the model should

Simulation Features

1-10

be operating in the little endian mode, whereas a ’0’ on this will mean that

the model should be operating in the big endian. The model will check to

see if the ISS and BIM are operating in the same endian, and if they are

not it will give an error message and exit.

- Boot load config pins BE18_BOOTMODE0, BE19_BOOTMODE1. The

values on these pins determine the boot load mode as explained in section

1.4.1, on page 1-9.

1.4.3 Clock Behavior

The model operates from the clock supplied by the CLKIN pin. The EMIF oper-

ates at 1/4th this clock frequency, whereas the HPI/PCI and Utopia operate at

1/2 this clock frequency. For the model to work properly, the rising edge of all

the clocks should be in sync when the reset is applied.

The EMIF doesn’t support other clock frequencies or external clock inputs.

Seamless Features Supported

1-11Features of the TMS320C6416 Seamless CVE

1.5 Seamless Features Supported

1.5.1 Seamless Optimization

1.5.1.1 Memory Optimization

To learn more about Memory Optimization, please read the Mentor Graphics

Seamless CVE User’s Guide.

TMS320C6416 PSP supports Memory Optimization. This feature has been

tested with Denali SRAM models. While using the Memory optimization fea-

ture, please register the memory ranges that are to be optimized, with the

Seamless CVE.

1.5.1.2 Time Optimization

To learn more about Time Optimization refer to the Mentor Graphics Seamless

CVE manuals.

The TMS320C6416 Seamless model supports the Time Optimization feature.

This optimization can be enabled at any time of execution of the model. The

model takes care of any unfinished pipelined memory requests that may be

pending at the time of turning on the Time Optimization feature, before switch-

ing into optimized mode of execution.

1.5.1.3 Ratio Time Optimization

To learn more about Ratio Time Optimization please refer to the Mentor Graph-

ics Seamless CVE User’s Guide.

On the same lines of support for Time Optimization, the TMS320C6416 Seam-

less model supports Ratio Time Optimization also.

1.5.2 HW Break

This command is implemented as a Code Composer Studio GEL function. In-

voking this function from Code Composer Studio IDE causes the hardware

simulator to go into an interactive mode. It is possible to simultaneously use

both the hardware simulator and Code Composer Studio IDE interactively.

1.5.3 Loading COFF into External Memory

The TMS320C6416 Seamless model allows loading of a COFF file into exter-

nal memories. The hardware simulator is not advanced while the load is in

progress.

Seamless Features Supported

1-12

This feature is supported only when the external memories are Seamless me-

mories such as Denali memory models.

The COFF load is performed by loading the file through Code Composer Stu-

dio.

Simulation Accuracy

1-13Features of the TMS320C6416 Seamless CVE

1.6 Simulation Accuracy

The TMS320C6416 Seamless Model simulates the following blocks of the de-

vice:

J CPU

J L1, L2 Cache System

J Enhanced DMA sub–system

J Interrupt Selector

J Timers

J Serial Ports (McBSP)

J TCP, VCP co–processors

J EMIF interface

J Utopia–II

J HPI/PCI

J GPIO

CPU – The CPU core of the device has been modeled accurately both in terms

of functionality and cycles.

L1, L2 Cache System – All of the functionality in the L1, L2 Cache system has

been modeled in the TMS320C6416 Seamless Model. The simulation of the

Cache System is still not 100% cycle accurate though. L1P is not accurate on

the Instruction Read Misses. L1D is very accurate on Data Read misses and

Victim requests to L2, but is about 95% accurate on L1D write miss cycles.

EDMA – The EDMA subsystem is modeled functionally to support complete

programmability of the EDMA configuration registers. The number of cycles

spent in the subsystem is however inaccurate.

Peripherals such as the EMIF, Timer, Serial Ports, Utopia, GPIO, HPI, and PCI

are modeled accurately for functionality and cycles. Coprocessors TCP/VCP

are modeled accurately for functionality and cycles.

Please refer to Section 1.7 on page 1-14 for known limitations in the

TMS320C6416 Seamless model.

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Texas Instruments TMS320C6416 Seamless CVE Model (Rev. B) User guide

Brand: Texas Instruments

Model: TMS320C6416 Seamless CVE Model (Rev. B)

Category: Supplementary music equipment

Type: User guide

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Texas Instruments TMS320C6416 Seamless CVE Model (Rev. B) User guide

Texas Instruments TMS320C6416 Seamless CVE Model (Rev. B) User guide

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