Terasic DE1-SoC User manual

Brand
Terasic
Model
DE1-SoC
Type
User manual
DE1-SoC User Manual
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August 5, 2015
DE1-SoC User Manual
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August 5, 2015
CONTENTS
CHAPTER 1
DE1-SOC DEVELOPMENT KIT
......................................................................... 4
1.1 Package Contents ....................................................................................................................... 4
1.2 DE1-SoC System CD ................................................................................................................. 5
1.3 Getting Help ............................................................................................................................... 5
CHAPTER 2
INTRODUCTION OF THE DE1-SOC BOARD
.................................................... 6
2.1 Layout and Components ............................................................................................................. 6
2.2 Block Diagram of the DE1-SoC Board ...................................................................................... 9
CHAPTER 3
USING THE DE1-SOC BOARD
........................................................................ 12
3.1 Settings of FPGA Configuration Mode .................................................................................... 12
3.2 Configuration of Cyclone V SoC FPGA on DE1-SoC ............................................................. 13
3.3 Board Status Elements.............................................................................................................. 19
3.4 Board Reset Elements .............................................................................................................. 20
3.5 Clock Circuitry ......................................................................................................................... 21
3.6 Peripherals Connected to the FPGA ......................................................................................... 23
3.6.1 User Push-buttons, Switches and LEDs ................................................................................ 23
3.6.2 7-segment Displays ............................................................................................................... 26
3.6.3 2x20 GPIO Expansion Headers ............................................................................................. 28
3.6.4 24-bit Audio CODEC ............................................................................................................ 30
3.6.5 I2C Multiplexer ..................................................................................................................... 31
3.6.6 VGA ...................................................................................................................................... 32
3.6.7 TV Decoder ........................................................................................................................... 35
3.6.8 IR Receiver ............................................................................................................................ 37
3.6.9 IR Emitter LED ..................................................................................................................... 37
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3.6.10 SDRAM Memory ................................................................................................................ 38
3.6.11 PS/2 Serial Port ................................................................................................................... 40
3.6.12 A/D Converter and 2x5 Header ........................................................................................... 42
3.7 Peripherals Connected to Hard Processor System (HPS)......................................................... 43
3.7.1 User Push-buttons and LEDs ................................................................................................ 43
3.7.2 Gigabit Ethernet .................................................................................................................... 44
3.7.3 UART .................................................................................................................................... 45
3.7.4 DDR3 Memory ...................................................................................................................... 46
3.7.5 Micro SD Card Socket .......................................................................................................... 48
3.7.6 2-port USB Host .................................................................................................................... 49
3.7.7 G-sensor ................................................................................................................................ 50
3.7.8 LTC Connector ...................................................................................................................... 51
CHAPTER 4
DE1-SOC SYSTEM BUILDER
.......................................................................... 53
4.1 Introduction .............................................................................................................................. 53
4.2 Design Flow ............................................................................................................................. 53
4.3 Using DE1-SoC System Builder .............................................................................................. 54
CHAPTER 5
EXAMPLES FOR FPGA
................................................................................... 60
5.1 DE1-SoC Factory Configuration .............................................................................................. 60
5.2 Audio Recording and Playing .................................................................................................. 61
5.3 Karaoke Machine ..................................................................................................................... 64
5.4 SDRAM Test in Nios II ............................................................................................................ 66
5.5 SDRAM Test in Verilog ........................................................................................................... 69
5.6 TV Box Demonstration ............................................................................................................ 71
5.7 PS/2 Mouse Demonstration ...................................................................................................... 73
5.8 IR Emitter LED and Receiver Demonstration ......................................................................... 76
5.9 ADC Reading ........................................................................................................................... 82
CHAPTER 6
EXAMPLES FOR HPS SOC
.............................................................................. 85
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6.1 Hello Program .......................................................................................................................... 85
6.2 Users LED and KEY ................................................................................................................ 87
6.3 I2C Interfaced G-sensor ........................................................................................................... 93
6.4 I2C MUX Test .......................................................................................................................... 96
CHAPTER 7
EXAMPLES FOR USING BOTH HPS SOC AND FGPA
..................................... 99
7.1 HPS Control LED and HEX ..................................................................................................... 99
7.2 DE1-SoC Control Panel ......................................................................................................... 103
7.3 DE1-SoC Linux Frame Buffer Project ................................................................................... 103
CHAPTER 8
PROGRAMMING THE EPCS DEVICE
............................................................. 105
8.1 Before Programming Begins .................................................................................................. 105
8.2 Convert .SOF File to .JIC File ................................................................................................ 105
8.3 Write JIC File into the EPCS Device ..................................................................................... 110
8.4 Erase the EPCS Device .......................................................................................................... 112
8.5 Nios II Boot from EPCS Device in Quartus II v13.1 ............................................................. 113
CHAPTER 9
APPENDIX
...................................................................................................... 114
9.1 Revision History ..................................................................................................................... 114
9.2 Copyright Statement ............................................................................................................... 114
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Chapter 1
DE1-SoC
Development Kit
The DE1-SoC Development Kit presents a robust hardware design platform built around the Altera
System-on-Chip (SoC) FPGA, which combines the latest dual-core Cortex-A9 embedded cores
with industry-leading programmable logic for ultimate design flexibility. Users can now leverage
the power of tremendous re-configurability paired with a high-performance, low-power processor
system. Altera’s SoC integrates an ARM-based hard processor system (HPS) consisting of processor,
peripherals and memory interfaces tied seamlessly with the FPGA fabric using a high-bandwidth
interconnect backbone. The DE1-SoC development board is equipped with high-speed DDR3
memory, video and audio capabilities, Ethernet networking, and much more that promise many
exciting applications.
The DE1-SoC Development Kit contains all the tools needed to use the board in conjunction with a
computer that runs the Microsoft Windows XP or later.
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Figure 1-1 shows a photograph of the DE1-SoC package.
Figure 1-1 The DE1-SoC package contents
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The DE1-SoC package includes:
The DE1-SoC development board
DE1-SoC Quick Start Guide
USB cable (Type A to B) for FPGA programming and control
USB cable (Type A to Mini-B) for UART control
12V DC power adapter
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The DE1-SoC System CD contains all the documents and supporting materials associated with
DE1-SoC, including the user manual, system builder, reference designs, and device datasheets.
Users can download this system CD from the link: http://cd-de1-soc.terasic.com.
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Here are the addresses where you can get help if you encounter any problems:
Altera Corporation
101 Innovation Drive San Jose, California, 95134 USA
Email: [email protected]
Terasic Technologies
9F., No.176, Sec.2, Gongdao 5th Rd, East Dist, Hsinchu City, 30070. Taiwan
Email: [email protected]
Tel.: +886-3-575-0880
Website: de1-soc.terasic.com
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Chapter 2
Introduction of the
DE1-SoC Board
This chapter provides an introduction to the features and design characteristics of the board.
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Figure 2-1 shows a photograph of the board. It depicts the layout of the board and indicates the
location of the connectors and key components.
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Figure 2-1 DE1-SoC development board (top view)
Figure 2-2 De1-SoC development board (bottom view)
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The DE1-SoC board has many features that allow users to implement a wide range of designed
circuits, from simple circuits to various multimedia projects.
The following hardware is provided on the board:
FPGA
Altera Cyclone® V SE 5CSEMA5F31C6N device
Altera serial configuration device – EPCS128
USB-Blaster II onboard for programming; JTAG Mode
64MB SDRAM (16-bit data bus)
4 push-buttons
10 slide switches
10 red user LEDs
Six 7-segment displays
Four 50MHz clock sources from the clock generator
24-bit CD-quality audio CODEC with line-in, line-out, and microphone-in jacks
VGA DAC (8-bit high-speed triple DACs) with VGA-out connector
TV decoder (NTSC/PAL/SECAM) and TV-in connector
PS/2 mouse/keyboard connector
IR receiver and IR emitter
Two 40-pin expansion header with diode protection
A/D converter, 4-pin SPI interface with FPGA
HPS (Hard Processor System)
800MHz Dual-core ARM Cortex-A9 MPCore processor
1GB DDR3 SDRAM (32-bit data bus)
1 Gigabit Ethernet PHY with RJ45 connector
2-port USB Host, normal Type-A USB connector
Micro SD card socket
Accelerometer (I2C interface + interrupt)
UART to USB, USB Mini-B connector
Warm reset button and cold reset button
One user button and one user LED
LTC 2x7 expansion header
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Figure 2-3 is the block diagram of the board. All the connections are established through the
Cyclone V SoC FPGA device to provide maximum flexibility for users. Users can configure the
FPGA to implement any system design.
Figure 2-3 Block diagram of DE1-SoC
Detailed information about Figure 2-3 are listed below.
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F
FP
PG
GA
A
D
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Cyclone V SoC 5CSEMA5F31 Device
Dual-core ARM Cortex-A9 (HPS)
85K programmable logic elements
4,450 Kbits embedded memory
6 fractional PLLs
2 hard memory controllers
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Quad serial configuration device – EPCS128 on FPGA
Onboard USB-Blaster II (normal type B USB connector)
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64MB (32Mx16) SDRAM on FPGA
1GB (2x256Mx16) DDR3 SDRAM on HPS
Micro SD card socket on HPS
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Two port USB 2.0 Host (ULPI interface with USB type A connector)
UART to USB (USB Mini-B connector)
10/100/1000 Ethernet
PS/2 mouse/keyboard
IR emitter/receiver
I2C multiplexer
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Two 40-pin expansion headers
One 10-pin ADC input header
One LTC connector (one Serial Peripheral Interface (SPI) Master ,one I2C and one GPIO
interface )
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24-bit VGA DAC
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24-bit CODEC, Line-in, Line-out, and microphone-in jacks
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TV decoder (NTSC/PAL/SECAM) and TV-in connector
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AD
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Fast throughput rate: 1 MSPS
Channel number: 8
Resolution: 12-bit
Analog input range : 0 ~ 2.5 V or 0 ~ 5V as selected via the RANGE bit in the control register
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5 user Keys (FPGA x4, HPS x1)
10 user switches (FPGA x10)
11 user LEDs (FPGA x10, HPS x 1)
2 HPS reset buttons (HPS_RESET_n and HPS_WARM_RST_n)
Six 7-segment displays
S
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G-Sensor on HPS
P
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12V DC input
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Chapter 3
Using the DE1-SoC
Board
This chapter provides an instruction to use the board and describes the peripherals.
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When the DE1-SoC board is powered on, the FPGA can be configured from EPCS or HPS. The
MSEL[4:0] pins are used to select the configuration scheme. It is implemented as a 6-pin DIP
switch SW10 on the DE1-SoC board, as shown in Figure 3-1.
Figure 3-1 DIP switch (SW10) setting of Active Serial (AS) mode at the back of DE1-SoC board
Table 3-1 shows the relation between MSEL[4:0] and DIP switch (SW10).
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Table 3-1 FPGA Configuration Mode Switch (SW10)
Board Reference
Description
Default
SW10.1
Use these pins to set the FPGA
Configuration scheme
ON (“0”)
SW10.2
OFF (“1”)
SW10.3
ON (“0”)
SW10.4
ON (“0”)
SW10.5
OFF (“1”)
SW10.6
N/A
N/A
Figure 3-1 shows MSEL[4:0] setting of AS mode, which is also the default setting on DE1-SoC.
When the board is powered on, the FPGA is configured from EPCS, which is pre-programmed with
the default code. If developers wish to reconfigure FPGA from an application software running on
Linux, the MSEL[4:0] needs to be set to “01010” before the programming process begins. If
developers using the "Linux Console with frame buffer" or "Linux LXDE Desktop" SD Card image,
the MSEL[4:0] needs to be set to “00000” before the board is powered on.
Table 3-2 MSEL Pin Settings for FPGA Configure of DE1-SoC
MSEL[4:0]
Configure Scheme
Description
10010
AS
FPGA configured from EPCS (default)
01010
FPPx32
FPGA configured from HPS software: Linux
00000
FPPx16
FPGA configured from HPS software: U-Boot, with
image stored on the SD card, like LXDE Desktop or
console Linux with frame buffer edition.
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There are two types of programming method supported by DE1-SoC:
1. JTAG programming: It is named after the IEEE standards Joint Test Action Group.
The configuration bit stream is downloaded directly into the Cyclone V SoC FPGA. The FPGA will
retain its current status as long as the power keeps applying to the board; the configuration
information will be lost when the power is off.
2. AS programming: The other programming method is Active Serial configuration.
The configuration bit stream is downloaded into the quad serial configuration device (EPCS128),
which provides non-volatile storage for the bit stream. The information is retained within EPCS128
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even if the DE1-SoC board is turned off. When the board is powered on, the configuration data in
the EPCS128 device is automatically loaded into the Cyclone V SoC FPGA.
JTAG Chain on DE1-SoC Board
The FPGA device can be configured through JTAG interface on DE1-SoC board, but the JTAG
chain must form a closed loop, which allows Quartus II programmer to the detect FPGA device.
Figure 3-2 illustrates the JTAG chain on DE1-SoC board.
Figure 3-2 Path of the JTAG chain
Configure the FPGA in JTAG Mode
There are two devices (FPGA and HPS) on the JTAG chain. The following shows how the FPGA is
programmed in JTAG mode step by step.
1. Open the Quartus II programmer and click “Auto Detect”, as circled in Figure 3-3
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Figure 3-3 Detect FPGA device in JTAG mode
2. Select detected device associated with the board, as circled in Figure 3-4.
Figure 3-4 Select 5CSEMA5 device
3. Both FPGA and HPS are detected, as shown in Figure 3-5.
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Figure 3-5 FPGA and HPS detected in Quartus programmer
4. Right click on the FPGA device and open the .sof file to be programmed, as highlighted in
Figure 3-6.
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Figure 3-6 Open the .sof file to be programmed into the FPGA device
5. Select the .sof file to be programmed, as shown in Figure 3-7.
Figure 3-7 Select the .sof file to be programmed into the FPGA device
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6. Click “Program/Configure” check box and then click “Start” button to download the .sof file
into the FPGA device, as shown in Figure 3-8.
Figure 3-8 Program .sof file into the FPGA device
Configure the FPGA in AS Mode
The DE1-SoC board uses a quad serial configuration device (EPCS128) to store configuration
data for the Cyclone V SoC FPGA. This configuration data is automatically loaded from the
quad serial configuration device chip into the FPGA when the board is powered up.
Users need to use Serial Flash Loader (SFL) to program the quad serial configuration device
via JTAG interface. The FPGA-based SFL is a soft intellectual property (IP) core within the
FPGA that bridge the JTAG and Flash interfaces. The SFL Megafunction is available in
Quartus II. Figure 3-9 shows the programming method when adopting SFL solution.
Please refer to Chapter 9: Steps of Programming the Quad Serial Configuration Device for the
basic programming instruction on the serial configuration device.
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Figure 3-9 Programming a quad serial configuration device with SFL solution
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In addition to the 10 LEDs that FPGA device can control, there are 5 indicators which can indicate
the board status (See Figure 3-10), please refer the details in Table 3-3
Figure 3-10 LED Indicators on DE1-SoC
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Terasic DE1-SoC User manual

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DE1-SoC
Type
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