PEX 8112 Fwd Riser
Reference Design
(For Board Revision 1.0)
Version 1.1
September 9, 2010
Website: www.plxtech.com
Technical Support: www.plxtech.com/support
Copyright © 2010 by PLX Technology, Inc. All Rights Reserved – Version 1.1
September 9, 2010
© 2010 PLX Technology, Inc. All rights reserved.
PLX Technology, Inc. retains the right to make changes to this product at any time, without notice. Products may
have minor variations to this publication, known as errata. PLX assumes no liability whatsoever, including
infringement of any patent or copyright, for sale and use of PLX products.
PLX Technology and the PLX logo are registered trademarks of PLX Technology, Inc.
Other brands and names are the property of their respective owners.
Order Number: PEX8112-FwdRiser-ReferenceDesign -1.1
September 9, 2010
PEX 8112 Fwd Riser Reference Design for Board Revision 1.0 – Version 1.1
Copyright © 2010 by PLX Technology, Inc. All rights reserved iii
CONTENTS
1. General Information ............................................................................................................................ 1
1.1 PEX 8112 Features ....................................................................................................................... 2
1.2 PEX 8112 Fwd Riser Features ...................................................................................................... 2
2. PEX 8112 Fwd Riser System Architecture ......................................................................................... 3
3. PEX 8112 Fwd Riser Hardware Architecture ...................................................................................... 4
3.1 PEX 8112 PCI Express Bridge Device .......................................................................................... 4
3.2 Serial EEPROM ............................................................................................................................ 4
3.3 PCI Interface ................................................................................................................................. 4
3.3.1 PCI Power ............................................................................................................................... 5
3.4 PCI Express Interface ................................................................................................................... 5
3.4.1 RefClk ..................................................................................................................................... 5
3.4.2 PERST# .................................................................................................................................. 5
3.5 LED Indicators............................................................................................................................... 5
3.6 PEX 8112 Fwd Riser Power .......................................................................................................... 5
3.6.1 PEX 8112 Bridge Device Power ............................................................................................. 5
3.7 Power Management Signaling ...................................................................................................... 6
3.7.1 Wakeup ................................................................................................................................... 6
4. M
ECHANICAL ARCHITECTURE ................................................................................................................ 7
4.1 Monitoring Point, Indicator, Control, and DIP Switch Summary .................................................... 7
4.1.1 Monitoring Points .................................................................................................................... 7
4.1.2 General-Purpose I/O, PWR_OK Signals Access Points ......................................................... 7
4.1.3 PCI Bus Configurations ........................................................................................................... 7
4.1.4 PCB Stackup ........................................................................................................................... 8
5. References .......................................................................................................................................... 9
6. Bill of Materials and Schematics ....................................................................................................... 10
FIGURES
Figure 1. PEX 8112 Fwd Riser – 3.3V PCI ............................................................................................... 1
Figure 2. PEX 8112 Fwd Riser – 5V PCI .................................................................................................. 1
Figure 3. PEX 8112 Fwd Riser Hardware Architecture ............................................................................. 4
Figure 4. PEX 8112 Fwd Riser Stackup ................................................................................................... 8
TABLES
Table 1. PEX 8112 Fwd Riser LED Indicator Function ............................................................................. 5
Table 2. PEX 8112 Fwd Riser Default Jumper Settings ........................................................................... 7
PEX 8112 Fwd Riser Reference Design for Board Revision 1.0 – Version 1.1
iv
Copyright © 2010 by PLX Technology, Inc. All rights reserved
PREFACE
NOTICE
This document contains PLX Confidential and Proprietary information. The contents of this document may not be
copied nor duplicated in any form, in whole or in part, without prior written consent from PLX Technology, Inc.
PLX provides the information and data included in this document for your benefit, but it is not possible to entirely
verify and test all the information, in all circumstances, particularly information relating to non-PLX manufactured
products. PLX makes neither warranty nor representation relating to the quality, content, or adequacy of this
information. The information in this document is subject to change without notice. Although every effort has been
made to ensure the accuracy of this manual, PLX shall not be liable for any errors, incidental or consequential
damages in connection with the furnishing, performance, or use of this manual or examples herein. PLX assumes
no responsibility for damage or loss resulting from the use of this manual, for loss or claims by third parties, which
may arise through the use of the PEX 8112 Fwd Riser, or for any damage or loss caused by deletion of data as a
result of malfunction or repair.
ABOUT THIS MANUAL
This document describes the PLX PEX 8112 Fwd Riser, the PEX 8112 Forward Bridge Riser Card, from a
hardware perspective. It contains a description of all major functional circuit blocks on the board and also is a
reference for the creation of software for this product. This manual also includes a complete bill of materials and
schematics.
REVISION HISTORY
Date Version Comments
January 2008 1.0 Initial release.
September
2010
1.1
Corrected C1 and C2 capacitors values to 0.1uF in the BOM and
schematic.
PEX 8112 Fwd Riser Reference Design for Board Revision 1.0 – Version 1.1
Copyright © 2010 by PLX Technology, Inc. All rights reserved 1
1. General Information
The PLX PEX 8112 Fwd Riser is a Reference Design based on the PEX 8112, a single-lane, PCI Express-to-PCI
bridge device. The PEX 8112 Fwd Riser provides a complete hardware platform allowing a PCI device to be
utilized in a PCI Express host system. The PEX 8112 Fwd Riser allows the PEX 8112 bridge device upstream
PCI Express port to be connected to a host system slot by way of a standard PCI Express edge connector (the
PEX 8112 Fwd Riser is designed to plug into a PCI Express motherboard slot). The PEX 8112 Fwd Riser also
allows one PCI adapter to be plugged into the downstream bus, by way of a standard PCI slot residing on the
PEX 8112 Fwd Riser (see Figure 1 and Figure 2 below for details).
Figure 1. PEX 8112 Fwd Riser – 3.3V PCI
Figure 2. PEX 8112 Fwd Riser – 5V PCI
PEX 8112 Fwd Riser Reference Design for Board Revision 1.0 – Version 1.1
2
Copyright © 2010 by PLX Technology, Inc. All rights reserved
1.1 PEX 8112 Features
 Compliant to the following specifications:
 PCI Express Base Specification, Revision 1.0a
 PCI Express to PCI Bridge Specification, Revision 1.0
 PCI Local Bus Specification, Revision 3.0
 Small package, enabling compact design
 Supports Forward and Reverse Bridging, allowing systems to migrate to PCI Express and leverage
software compatibility
Note: The PEX 8112 Fwd Riser is for Forward Mode designs. For Reverse Mode designs, refer to the
PEX 8112 Rev Riser.
 Integrated PCI Express interface with x1 link, dual-simplex 2.5 Gbps SerDes
 Single PCI Express port, capable of x1 link width
 Single PCI Bus segment supporting PCI protocol at 32-bit/66 MHz
 Low power consumption, meeting designers’ demands for reduced power draws
 3.3V I/O and 5V tolerant PCI
 Serial EEPROM configuration option with Serial Peripheral Interface (SPI)
 8-KB general-purpose shared RAM
1.2 PEX 8112 Fwd Riser Features
 PLX PCI Express-to-PCI bridge device in a 13mm x 13mm, 144-ball PBGA package
 Form factor based on the PCI Local Bus Specification, Revision 3.0
 Single x1 PCI Express Edge connector for insertion into standard PCI Express slot of x1 or greater link
width
 One downstream 32-bit PCI slot
 Socketable SPI serial EEPROM (3.3V devices supported)
 LEDs for link status visual inspection
 Auxiliary floppy disk power connector for additional power requirement support
PEX 8112 Fwd Riser Reference Design for Board Revision 1.0 – Version 1.1
Copyright © 2010 by PLX Technology, Inc. All rights reserved 3
2. PEX 8112 Fwd Riser System Architecture
The PEX 8112 Fwd Riser assists customers in evaluating PLX Technology’s PEX 8112 PCI Express-to-PCI
bridge device. The usage configuration is forward bridging between a PCI Express base board and a PCI add-in
board. The PEX 8112 Fwd Riser is designed to showcase all PEX 8112 features when operating in Forward
Bridge mode.
The PEX 8112 Fwd Riser’s form factor is based on the PCI Local Bus Specification, Revision 3.0. The PCI
interface supports up to 32-bit transfers, at up to 66 MHz. The PEX 8112 Fwd Riser has one PCI slot (female)
connector (straddle mount). The PCI Express interface supports one lane operating at 2.5 Gbps.
PEX 8112 Fwd Riser power is generated from +3.3 VDC, provided through the PCI Express edge connector.
Limited PCI +5 VDC power is generated from +12 VDC, provided through the PCI Express edge connector.
Limited PCI -12 VDC power is generated from +5 VDC that was generated. PCI +3.3 VDC and +12 VDC are
provided through the PCI Express edge connector. If PCI bus power demands are beyond the capability of
onboard circuitry, PCI bus power can be supplied from a 4-pin hard disk power connector.
PEX 8112 Fwd Riser Reference Design for Board Revision 1.0 – Version 1.1
4
Copyright © 2010 by PLX Technology, Inc. All rights reserved
3. PEX 8112 Fwd Riser Hardware Architecture
Figure 3. PEX 8112 Fwd Riser Hardware Architecture
3.1 PEX 8112 PCI Express Bridge Device
The PEX 8112 is a high-performance bridge, designed to the PCI Express-to-PCI Bridge Specification 1.0, which
enables designers to migrate legacy PCI Bus interfaces to the new, advanced serial PCI Express. This 2-port
device is equipped with a single-lane PCI Express port and a parallel bus segment supporting Conventional PCI
operation. The PEX 8112 is capable of operating in Forward and Reverse Bridging modes. The PEX 8112 bridge
device is housed in a 13mm x 13mm, 144-ball PBGA package. Ball spacing is 1.0mm. No additional cooling is
required.
3.2 Serial EEPROM
The PEX 8112 bridge device has an SPI serial EEPROM, which can be used to load configuration data from a
serial EEPROM on power-up. However, a serial EEPROM is not needed to bring up the PEX 8112. This interface
is connected to an 8-pin DIP socket (U2), which houses the serial EEPROM. A pull-up resistor (R11) on the
EERDDATA ball produces a value of FFh if there is no serial EEPROM installed.
The PEX 8112 supports up to 16-MB serial EEPROMs, utilizing 1, 2, or 3-byte addressing. The PEX 8112
automatically determines the appropriate addressing mode. The SPI operates at up to 25 MHz and can directly
interface with the PEX 8112. The Atmel AT25640 device is recommended. Other compatible 128-byte serial
EEPROMs include the Atmel AT25010A, Catalyst CAT25C01, and ST Microelectronics M95010W.
3.3 PCI Interface
This PEX 8112 Fwd Riser has one female PCI slot, which connects to the PEX 8112’s PCI bus. Connector J3 is a
straddle-mount (SMT) connector that has its own REQ#/GNT# pair, which can be arbitrated by the PEX 8112.
Cards plugged into this slot are oriented parallel to the PEX 8112 Fwd Riser. The slot supports 32-bit data
transfers and can be populated for a 3.3V or 5V keyed PCI edge connector. The slot supports up to 66-MHz clock
rate.
PEX 8112 Fwd Riser Hardware Reference Manual for Board Revision 1.0 – Version 1.1
Copyright © 2010 by PLX Technology, Inc. All rights reserved 5
3.3.1 PCI Power
The PEX 8112 Fwd Riser provides four voltages to the PCI slot. These are:
• 3.3V derived from the PCI Express slot
• 5V supplied by way of the floppy disk power connector (J4)
• +12V derived from the PCI Express edge slot or the floppy disk power connector (J4), by option resistor
• -12V regulated on board from the 3.3V supply
3.4 PCI Express Interface
The PCI Express interface is a male card edge connector, based on the PCI Express Card Electromechanical
(CEM) Specification, Revision 1.0a for an x1 interface. The card edge provides +12 VDC and +3.3 VDC, RefClk,
and PERST#. The PCI Express lanes are laid out as 100-Ohm, controlled-impedance, microstrip-differential pairs.
Trace length mismatch within signal pairs is not greater than 0.005".
3.4.1 RefClk
PCI Express RefClk enters the PEX 8112RFwd Riser through the PCI Express card edge (male) connector.
RefClk is laid out as a 100-Ohm, controlled-impedance, microstrip-differential pair. Trace length mismatch is not
greater than 0.005".
3.4.2 PERST#
PERST# is the fundamental Reset signal to the PEX 8112, from the PCI Express edge connector.
3.5 LED Indicators
The PEX 8112 Fwd Riser provides several LED indicators, including power-on indication and programmable PEX
8112 GPIO lane status indication. Table 1 provides a quick explanation of each LED indicator.
Table 1. PEX 8112 Fwd Riser LED Indicator Function
Indicator Type Location LED ON
GPIO D1
Output
OFF (0) – Link Down
ON (1) – Link Up
3.6 PEX 8112 Fwd Riser Power
The PEX 8112 Fwd Riser has two sources for DC power. The first source is the card edge connector (J1). This x1
connector provides up to 500 mA at +12V, and 3.0A at +3.3V. Card edge power is intended to power only PEX
8112 Fwd Riser components, as well as optional PCI connector (J3).
The second source, the 4-pin floppy disk power connector, provides +12V, -12V, and +5V DC power. The +5V is
converted down to +3.3V and -12V for slot J3 when configured as a 3.3V slot. The +12V power rail is used
directly.
3.6.1 PEX 8112 Bridge Device Power
The PEX 8112 bridge device power consists of the following:
 VDD Core +1.5 VDC ±0.1V
 VDD I/O +3.3 VDC ±10%
 VIO Clamp +5 VDC for 5V PCI
+3.3 VDC for 3.3V PCI
PEX 8112 Fwd Riser Reference Design for Board Revision 1.0 – Version 1.1
6
Copyright © 2010 by PLX Technology, Inc. All rights reserved
3.7 Power Management Signaling
PCI devices assert the PME# pin (connected to the PEX 8112 PMEIN# ball) to signal a Power Management
event. The PEX 8112 converts the PME# signal to PCI Express Power Management Event (PME) messages.
There are no internal events that cause a PME message to be sent upstream.
Power Management messages are used to support PMEs signaled by devices downstream of the PEX 8112.
System software needs to identify the source of a PCI PME reported by a PM_PME message. When the PME
comes from an agent on a PCI Bus, then the PM_PME Message Requester ID reports the Bus Number from
which the PME was collected, and the Device Number and Function Number reported must both be zero (0).
When the PME message is sent to the host, the PWRMNGCSR register PME Status bit is set and a 100-ms timer
is started. If the status bit is not cleared within 100 ms, another PME message is sent.
When the upstream device is powering down the downstream devices, it first places all devices into the D3
hot
state. It then sends a PCI Express PME_Turn_Off message. After the PEX 8112 receives this message, it stops
sending PME messages upstream. The PEX 8112 then sends a PME_TO_Ack message to the upstream device
and places its link into the L2/L3 Ready state. The downstream device is now ready to be powered down. If the
upstream device changes the PEX 8112 power state back to D0, PME messages are re-enabled. The PCI
Express PME_Turn_Off message terminates at the PEX 8112, and is not communicated to the PCI devices. The
PEX 8112 does not issue a PM_PME message on behalf of a downstream PCI device while its upstream link is in
the L2/L3 non-communicating state.
To avoid loss of PME# assertions in the conversion of the level-sensitive PME# signal to the edge- triggered PCI
Express PM_PME message, the PCI PME# signal is polled every 256 ms by the PEX 8112 and a PCI Express
PM_PME message is generated if PME# is asserted.
The PMEIN# ball is used only when the PEX 8112 is in Forward Bridge Mode.
3.7.1 Wakeup
The PEX 8112 asserts the WAKEOUT# signal or sends a PCI Express beacon for the following:
 PCI PME# pin is asserted while link is in L2 state
 PCI Express beacon is received while link is in L2 state
 PCI Express PM_PME Message is received
A beacon is transmitted if the following are true:
 PCI PME# pin is asserted while link is in L2 state
 DEVSPECCTL register Beacon Generate Enable bit is set
 PWRMNGCSR register PME Enable bit is set
The WAKEOUT# signal is used only when the PEX 8112 is in Forward Bridge mode.
PEX 8112 Fwd Riser Hardware Reference Manual for Board Revision 1.0 – Version 1.1
Copyright © 2010 by PLX Technology, Inc. All rights reserved 7
4. MECHANICAL ARCHITECTURE
4.1 Monitoring Point, Indicator, Control, and DIP Switch Summary
This section summarizes the interfaces available on the PEX 8112 Fwd Riser for controlling and monitoring PEX
8112 performance.
4.1.1 Monitoring Points
 Voltages to the PEX 8112 and PCI bus can be monitored at the following component locations:
Voltages Function
-12.0 V R18
+1.5 V R15
+3.3 V C20, C21,C48, C49
+5.0 V R17
+12.0 V R16
4.1.2 General-Purpose I/O, PWR_OK Signals Access Points
PEX 8112 General-Purpose I/O signals GPIO[3:1] are accessible via header JP2. PEX 8112 PWR_OK signal is
accessible via header TP1. These headers are located next to the serial EEPROM socket, U2. J2 Pin
assignments are as follows:
J2 Pin # Function
1 GPIO1
2 GPIO2
3 GPIO3
4.1.3 PCI Bus Configurations
The PEX 8112 FWD Riser supports two different assembly configurations, one for 3-volt-keyed adapters, and one
for 5-volt-keyed adapters. These assembly configurations are described below.
3.3 Volt PCI Bus Configuration:
¾ Install straddle-mount PCI slot connector J3 with keyed end in-line with the PCI Express card edge.
¾ Install R19 (0.1 Ohms, 1206)
¾ Do Not Install R20
5 Volt PCI Bus Configuration:
(Note: some additional rework is needed to support 5 Volt slot configuration)
¾ Install straddle-mount PCI slot connector J3 with keyed end opposite of the PCI Express card edge.
¾ Wire J3, pin A-18 (GND) to pins A12, A13 (there are no gold fingers on the PCB in these locations).
¾ Wire J3, pin B-11 (GND) to pins B12, B13 (there are no gold fingers on the PCB in these locations).
¾ Install R20 (47 Ohms, 1206)
¾ Do Not Install R19
Table 2. PEX 8112 Fwd Riser Default Jumper Settings
PEX 8112 Fwd Riser Reference Design for Board Revision 1.0 – Version 1.1
8
Copyright © 2010 by PLX Technology, Inc. All rights reserved
4.1.4 PCB Stackup
The PEX 8112 Fwd Riser is a 6-layer, 62-mil thick PCB. The target signal impedance for all routing layers is 60
Ohms ±15% single-ended impedance and 100 Ohms ±5% differential. (Refer to Figure 5.)
L1, SIGNAL 1
SOLDERMASK
PREPREG
L2, GROUND
LAMINATE
L3, POWER PLANE
PREPREG
L4, POWER PLANE/
SIGNAL
L5, GROUND
LAMINATE
PREPREG
L6, SIGNAL 5
SOLDERMASK
Controller Impedance microstrip
Controller Impedance microstrip
Figure 4. PEX 8112 Fwd Riser Stackup
PEX 8112 Fwd Riser Hardware Reference Manual for Board Revision 1.0 – Version 1.1
Copyright © 2010 by PLX Technology, Inc. All rights reserved 9
5. References
The following is a list of documentation to provide further details.
 PLX Technology, Inc.
870 Maude Ave., Sunnyvale, CA 94085 USA
Tel: 408 774-9060 or 800 759-3735, Fax: 408 774-2169, http://www.plxtech.com
 PEX 8112BB Data Book, Version 0.83 or higher
 PEX 8112RDK-R Hardware Reference Manual
 PCI Special Interest Group (PCI-SIG)
5440 SW Westgate Drive #217, Portland, OR 97221 USA
Tel: 503 291-2569, Fax: 503 297-1090, http://www.pcisig.com
 PCI Express Card Electromechanical (CEM) Specification, Revision 1.0a
 PCI Express-to-PCI Bridge Specification 1.0
 PCI Local Bus Specification, Revision 3.0
PEX 8112 Fwd Riser Reference Design for Board Revision 1.0 – Version 1.1
10
Copyright © 2010 by PLX Technology, Inc. All rights reserved
6. Bill of Materials and Schematics
The following pages contain the PEX 8112 Fwd Riser bill of materials and schematics.
Item
#
Qty Man. Man. Part number Description Package Type
Component
Designator(s)
( ) = Do Not Populate
1 11 AVX 04023D103KAT2A
Cap, Ceramic, 0.01 uF,
25V, 10%, X5R, 0402
0.01 uF
C11, C13, C15, C17,
C22, C24, C26,
C28,C30, C32, C37
2 2 AVX 0805YD105KAT2A
Cap, Ceramic, 1 uF,
16V, 10%, X5R, 0805
1 uF C3,C35
3 45 AVX 0402YD104KAT2A
Cap, Ceramic, 0.1 uF,
16V, 10%, X5R, 0402
0.1 uF
C1, C2, C4, C6, C7, C8,
C12, C14, C16,C18,
C19, C23, C25, C27,
C29, C31, C34, C40,
C41, C42, C43, C44,
C45, C46, C47,C50,
C51, C52, C53, C54,
C55, C56, C57, C52,
C53, C54, C55, C56,
C57, C52, C53,C54,
C55, C56, C57, C58,
C59, C60, C61, C62,
C63, C66, C67, C68,
C69, C71, C72
4 1 AVX TAJD476K016R
Cap, Tantalum, 47 uF,
16V, Case D
47 uF C5
5 11 AVX TAJB106K016R
Cap, Tantalum, 10 uF,
16V, Case B
10 uF
C9, C10, C20, C21, C36,
C38, C39, C48, C49,
C64, C65
6 2 AVX TAJB226K016R
Cap, Tantalum, 22 uF,
16V, Case B
22 uF/16V C33, C70
7 1 Chicago CMD17-21VGC/TR8 LED, Green, SMT, 0805 SMLED0805 D1
8 1
Diodes
Inc.
B130L
Diode, B130L, SMT
(SMA)
B130L D2
9 1 n/a n/a n/a
PCI Express
x1 Edge
(J1)
10 1 n/a n/a n/a
Header 3x1,
0.1in
(J2)
11 1 Raycon RT-HD2-GT120ECN
Edge Card Conn., Dual
Bay (PCI 3.3V keyed)
0.050" pitch, extender
card tails, ke
RT-HD2-
GT120ECN
J3
12 1 Molex 22111041
Header 1x4, 0.125",
w/locking tab
HEADER 4 J4
13 1 Murata LQH32CN470K53L
Inductor, Winding, 47
uH, 10%, 170 mA, 1.3
ohms, 1210
47 uH (1210) L1
14 1 Toko S1023AS-470M
Coil, 47 uH, Ferrite-
Shielded
47 uH L2
15 13 AVX CRB2A4E472JT
Resistor Array, x4, 2.7K
ohms, 5%, 0.1W, 0805
2.7K
RN2, RN3, RN4, RN6,
R21, R22, R23, R24,
R25, R26, R27, R28,
R29
16 1 Panasonic ERJ2GEYJ512C
Resistor, 5.1K ohms,
5.1K RN7
PEX 8112 Fwd Riser Hardware Reference Manual for Board Revision 1.0 – Version 1.1
Copyright © 2010 by PLX Technology, Inc. All rights reserved 11
Item
#
Qty Man. Man. Part number Description Package Type
Component
Designator(s)
( ) = Do Not Populate
5%, 0.1W, 0402
17 4 Panasonic ERJ2GEY0R00V
Resistor, 0 ohms, 5%,
0.1W, 0402
0 ( R1, R3 , R8, R12 )
18 2 Panasonic ERJ2GEYJ472C
Resistor, 4.7K ohms,
5%, 0.1W, 0402
4.7K R2, R4
19 2 Panasonic ERJ2GEYJ330C
Resistor, 33 Ohms, 5%,
0.1W, 0402
33 R5, R6
20 1 Panasonic ERJ6RSJR18V
Resistor, 0.18 Ohms,
1%, 0.25W, 0805
0.18 (0805) R7
21 1 Panasonic ERJ2GEYJ241C
Resistor, 240 Ohms,
5%, 0.1W, 0402
274 R9
22 2 Panasonic ERJ2GEYJ103C
Resistor, 10K Ohms,
5%, 0.1W, 0402
10K R10, R11
23 2 Panasonic ERJ2GEYJ102C
Resistor, 100 Ohms,
5%, 0.1W, 0402
100 R13, (R14)
24 5
AVX
(Kyocera)
LR32R100FT
Resistor, 0.01 Ohms,
1%, 1206
0.01 (1206)
R15, R16, R17, R18,
R19
25 1 Panasonic ERJ8GYJ470V
Resistor, 47 Ohms, 5%,
1/4 W, 1206
47 (1206) (R20)
26 1 n/a n/a
Test point, plated thru-
hole
n/a (TP1)
27 1
PLX
Technolog
yInc.
PEX 8112-AA66BI F
PCI Express-to-PCI
Bridge
PEX8112-
144P
U1
28a * 1 Atmel
AT25640A-10PU-
2.7
Serial EEPROM, SPI,
25640, socketed
AT25640 U2
28b 1 Mill-Max
110-93-308-41-
001000
EEPROM socket, low-
profile, thru-hole, PDIP-
8
Socket (PDIP-
8)
U2
29 1
National
Semi-
conductor
LP2992AIM5-1.5
Regulator, LDO, 1.5 V
fixed (NS Package
Marking: " LFBA ")
LP2992 U3
30 1 Maxim MAX765CSA
Regulator, Inv. Boost, -
12V fixed, 200mA
MAX765 U4
Manually Inserted Components
28a * 1 Atmel
AT25640A-10PU-
2.7
Serial EEPROM, SPI,
25640, socketed
AT25640 U2
Do Not Populate / No Part Required
J1,J2, R1, R3, R8, R12, R14, R20, TP1
PLX Part # PEX 8112 Fwd Rise
r
Revision 1.0
Product Name: PEX 8112 Fwd Rise
r
Date October 23, 2007
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
01- Title Page
02- PEX8112 part 1
03- PEX8112 part 2
04- PCI connector A
05- Power, PCI bypass caps
PEX8112 Fwd. Riser
PCI Slot, 3.3V, x32 Bits, 33/66 MHz
PEX8112
PCI Express Card-Edge, x1 Lane
SPI
EEPROM
DATE
Description
Power
Regulation
+3.3 V+5 V+12 V -12 V
+1.5 V
+3.3 V
+3.3 V+12 VP
PCIe x1
PCI
ATX/FDD
POWER
HEADER
9/10/2007 Released For Layout
- added link status LED pg 2
- added resistor option for IDSEL on A20, pg4
- replaced 5V regulator with FDD power header, pg 5
- Annotations Frozen, DSN, Netlist released for layout
9/19/2007
Post Layout Schematic Update
- Deleted RN1, replaced with R21-R25
- Deleted RN5, replaced with R26-R29
- Mirror Horizontal RN2,3,4,6,7
- Changed 12VCC to +12V
9/25/2007
Post Layout Schematic Update #2
- Undo Mirror Horizontal RN6
- Updated component sizes in properties table
L1, L2: change size to 0805
D12N1: change value to B130L, change size to SMA
10/01/2007 Release 1.0 (for fabrication)
- J1.A2,A3,B1,B2: Pin name changed to +12VP (no conn)
- RN6.2: Connect to TRDY#, RN6.3: connect to IRDY#
- L1 change value to FB0805
- L2 change value to 47 uF, change footprint to Toko p/n S1023AS-470M
Revision History
Block Diagram
09/08/2010 - C1, C2 changed value to 0.1 uF
Title
Size Document Number Rev
Date: Sheet
of
1.0
Cover Page
PLX TECHNOLOGY, INC.
870 Maude Ave, Sunnyvale, CA 94085
B
15Wednesday, September 08, 2010
www.plxtech.com
PEX 8112 FWD RISER
Title
Size Document Number Rev
Date: Sheet
of
1.0
Cover Page
PLX TECHNOLOGY, INC.
870 Maude Ave, Sunnyvale, CA 94085
B
15Wednesday, September 08, 2010
www.plxtech.com
PEX 8112 FWD RISER
Title
Size Document Number Rev
Date: Sheet
of
1.0
Cover Page
PLX TECHNOLOGY, INC.
870 Maude Ave, Sunnyvale, CA 94085
B
15Wednesday, September 08, 2010
www.plxtech.com
PEX 8112 FWD RISER
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PEX8112 PCI Bus
Place series termination
resistors close to PCLKO
PEX8112 Fwd. Riser
DO NOT INSTALL
PCI Express X1 Card-Edge
Match trace lengths
for nets PCLKI, PCI_CLK
Differential Pair
Differential Pair
Differential Pair
Place caps close
to card edge fingers
PRSNT Trace Routing
DO NOT INSTALL
PEX 8112 PCI Express
PRSNT
REFCLK+
REFCLK-
PERn0
PERp0
REQ0#
REQ2#
REQ1#
REQ3#
PCI_RST#
PMEIN#
FRAME#
TRDY#
IRDY#
DEVSEL#
STOP#
PAR
PERR#
SERR#
GNT#
LOCK#IDSEL
INTD#
INTA#
INTC#
INTB#
AD0
AD1
AD3
AD2
AD4
AD5
AD6
AD7
AD9
AD8
AD11
AD10
AD12
AD13
AD15
AD14
AD16
AD17
AD19
AD20
AD23
AD22
AD18
AD25
AD21
AD24
AD27
AD28
AD26
AD29
AD30
AD31
AD[31:0]
C/BE3#
PETp0C
C/BE2#
C/BE0#
C/BE1#
PETn0C
WAKEOUT#
PCI_CLK
PERST#
M66EN#
PCLKI
PRSNT
PCLKO62SEL#
PERp0
PERn0
PETp0
PETn0
PERST#
REFCLK+
REFCLK-
3.3VCC 3.3VCC
+VI/O
M66EN
AD[31:0]
C/BE0#
C/BE1#
C/BE2#
C/BE3#
GNT#
FRAME#
IRDY#
TRDY#
STOP#
DEVSEL#
PERR#
SERR#
PAR
LOCK#
PCI_CLK
WAKEOUT#
INTA#
INTB#
INTC#
INTD#
REQ0#
REQ1#
REQ2#
REQ3#
PCI_RST#
PMEIN#
Title
Size Document Number Rev
Date: Sheet
of
1.0
PEX 8112, Part 1
PLX TECHNOLOGY, INC.
870 Maude Ave, Sunnyvale, CA 94085
B
25Wednesday, September 08, 2010
www.plxtech.com
Title
Size Document Number Rev
Date: Sheet
of
1.0
PEX 8112, Part 1
PLX TECHNOLOGY, INC.
870 Maude Ave, Sunnyvale, CA 94085
B
25Wednesday, September 08, 2010
www.plxtech.com
Title
Size Document Number Rev
Date: Sheet
of
1.0
PEX 8112, Part 1
PLX TECHNOLOGY, INC.
870 Maude Ave, Sunnyvale, CA 94085
B
25Wednesday, September 08, 2010
www.plxtech.com
R5 33R5 33
R2
4.7K
R2
4.7K
C1 0.1 uFC1 0.1 uF
R3
0
R3
0
R6 33R6 33
C2 0.1 uFC2 0.1 uF
J1
PCI Express x1 Edge
J1
PCI Express x1 Edge
+12VP
B1
+12VP
B2
RSVD
B3
GND
B4
SMCLK
B5
SMDAT
B6
GND
B7
+3.3V
B8
JTAG1
B9
3.3Vaux
B10
WAKE#
B11
RSVD
B12
GND
B13
PETp0
B14
PETn0
B15
GND
B16
PRSNT2#
B17
GND
B18
PRSNT1#
A1
+12VP
A2
+12VP
A3
GND
A4
JTAG2
A5
JTAG3
A6
JTAG4
A7
JTAG5
A8
+3.3V
A9
+3.3V
A10
PERST#
A11
GND
A12
REFCLK+
A13
REFCLK-
A14
GND
A15
PERp0
A16
PERn0
A17
GND
A18
R4
4.7K
R4
4.7K
R1
0
R1
0
PEX 8112
PCI32/66
U1A
PEX8112-144P
PEX 8112
PCI32/66
U1A
PEX8112-144P
AD0
D3
AD1
C1
AD2
D1
AD3
D2
AD4
E1
AD5
E2
AD6
E3
AD7
E4
AD8
F2
AD9
F3
AD10
F4
AD11
G1
AD12
G2
AD13
G3
AD14
H1
AD15
H2
AD16
J5
AD17
L6
AD18
M6
AD19
K6
AD20
J6
AD21
M7
AD22
L7
AD23
K7
AD24
L8
AD25
K8
AD26
M9
AD27
L9
AD28
K12
AD29
J11
AD30
J12
AD31
J10
CBE0#
F1
CBE1#
H3
CBE2#
K5
CBE3#
M8
INTA#
E12
INTB#
E9
INTC#
D11
INTD#
E10
REQ0#
G11
REQ1#
H9
REQ2#
G12
REQ3#
H11
GNT0#
G10
GNT1#
G9
GNT2#
F11
GNT3#
E11
FRAME#
M5
IRDY#
L5
TRDY#
M4
STOP#
L4
DEVSEL#
K4
PERR#
J3
SERR#
J2
PAR
J1
LOCK#
M3
PMEOUT#
L12
PCLKO
H10
PCIRST#
F10
IDSEL
K9
PMEIN#
H12
PCLKI
D12
M66EN
D10
PCLK062SEL#
C2
PCI-Express
U1B
PEX8112-144P
PCI-Express
U1B
PEX8112-144P
PETp0
B5
PETn0
A4
PERST#
B12
REFCLK+
A6
REFCLK-
B6
PERp0
A8
PERn0
B7
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PEX 8112, Part 2: Configuration and Power
PEX 8112 PLL Power Filter
DO NOT INSTALL
PEX 8112 Configuration, Test, Misc. PEX8112 Power
Configuration Serial EEPROM
PDIP-8 Socket
Do Not Install
Thru-holes only
Place components close to PEX 8112 AVDD, VDD_P balls.
Place close to VDD5 balls.
Place close to VDD1.5, VDD_R, VDD_T balls.
Place close to VDD3.3 balls.
Link Status LED
1.4 Ohms Total DCR
EECLK
EECS#
EEWRDATA
GND
GND
GND
WAKEOUT#
EEWRDATA
GND
GND
GND
GND
GND
EECLK
GND
GND
EERDATA
FORWARD
EERDATA
BAR0ENB#
EECS#
GPIO0
GPIO1
GPIO2
GPIO3
WAKEIN#
GND
TDI
TMS
PWR_OK
TDO
FORWARD
WAKEIN#
TDI
TMS
TDO GPIO0
+VI/O
3.3VCC
3.3VCC1.5VCC1.5AVCC
1.5VCC
+VI/O
3.3VCC
1.5AVCC
1.5VCC
3.3VCC
WAKEOUT#
Title
Size Document Number Rev
Date: Sheet
of
1.0
PEX 8112, Part 2
PLX TECHNOLOGY, INC.
870 Maude Ave, Sunnyvale, CA 94085
B
35Wednesday, September 08, 2010
www.plxtech.com
PEX 8112 Fwd. Riser
Title
Size Document Number Rev
Date: Sheet
of
1.0
PEX 8112, Part 2
PLX TECHNOLOGY, INC.
870 Maude Ave, Sunnyvale, CA 94085
B
35Wednesday, September 08, 2010
www.plxtech.com
PEX 8112 Fwd. Riser
Title
Size Document Number Rev
Date: Sheet
of
1.0
PEX 8112, Part 2
PLX TECHNOLOGY, INC.
870 Maude Ave, Sunnyvale, CA 94085
B
35Wednesday, September 08, 2010
www.plxtech.com
PEX 8112 Fwd. Riser
R8
0
R8
0
C26
0.01 uF
C26
0.01 uF
R22 2.7KR22 2.7K
C15
0.01 uF
C15
0.01 uF
C31
0.1 uF
C31
0.1 uF
J2
Header 3x1, 0.1in
J2
Header 3x1, 0.1in
1
2
3
C27
0.1 uF
C27
0.1 uF
C8
0.1 uF
C8
0.1 uF
12
+
C5
47 uF
+
C5
47 uF
12
C11
0.01 uF
C11
0.01 uF
C16
0.1 uF
C16
0.1 uF
U2
AT25640
U2
AT25640
SCK
6
CS#
1
SI
5
WP#
3
SO
2
HOLD#
7
GND
4
VCC
8
C12
0.1 uF
C12
0.1 uF
R25 2.7KR25 2.7K
R10
10K
R10
10K
C22
0.01 uF
C22
0.01 uF
R7
0.18 (0805)
R7
0.18 (0805)
C28
0.01 uF
C28
0.01 uF
R9
274
R9
274
C17
0.01 uF
C17
0.01 uF
C24
0.01 uF
C24
0.01 uF
R24 2.7KR24 2.7K
C3
1 uF
C3
1 uF
12
C20
10 uF
C20
10 uF
C29
0.1 uF
C29
0.1 uF
C19
0.1 uF
C19
0.1 uF
C13
0.01 uF
C13
0.01 uF
C6
0.1 uF
C6
0.1 uF
12
C18
0.1 uF
C18
0.1 uF
C25
0.1 uF
C25
0.1 uF
C21
10 uF
C21
10 uF
C14
0.1 uF
C14
0.1 uF
D1
SMLED0805
D1
SMLED0805
C9
10 uF
C9
10 uF
R23 2.7KR23 2.7K
TP1
Thru-hole
TP1
Thru-hole
1
TEST/MISC.
U1C
PEX8112-144P
TEST/MISC.
U1C
PEX8112-144P
EERDDATA
A1
TDO
L1
EECS#
C4
EECLK
B2
EEWRDATA
A2
WAKEOUT#
A9
PWR_OK
B9
WAKEIN#
C12
FORWARD
L11
EXTARB
K11
TEST
A3
BUNRI
D8
BTON
M11
SMC
K1
TMC
C8
TMC1
B1
TMC2
M1
TDI
L3
TCK
M2
TMS
M12
TRST#
L10
GPIO0
C9
GPIO1
A10
GPIO2
B10
GPIO3
A11
BAR0ENB#
E8
R11
10K
R11
10K
C10
10 uF
C10
10 uF
POWER
U1D
PEX8112-144P
POWER
U1D
PEX8112-144P
AVDD
E7
VDD1.5
D4
VDD1.5
F6
VDD1.5
F8
VDD1.5
K3
VDD1.5
G6
VDD1.5
C10
VDD1.5
G7
VDD1.5
J9
VDD5
G8
VDD5
F5
VDD5
H6
VDDQ
J7
VDDQ
H5
VDDQ
F9
VDDQ
E5
VDDQ
G4
VDDQ
H8
AVSS
C7
VDD3.3
B3
VDD3.3
B11
VDD3.3
L2
VDD3.3
M10
VDD_P
D5
VDD_R
A7
VDD_T
A5
GND
A12
GND
B4
GND
C3
GND
C11
GND
D9
GND
E6
GND
F12
GND
G5
GND
H4
GND
H7
GND
J4
GND
J8
GND
K2
GND
K10
VSS_C
D7
VSS_P0
D6
VSS_P1
C6
VSS_R
B8
VSS_RE
F7
VSS_T
C5
C7
0.1 uF
C7
0.1 uF
12
C23
0.1 uF
C23
0.1 uF
R12
0
R12
0
C4
0.1 uF
C4
0.1 uF
12
R21 2.7KR21 2.7K
C30
0.01 uF
C30
0.01 uF
L1
FB0805
L1
FB0805
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PCI Slot Connector
Place
close to
J3
PCI Pull-ups
Do Not Populate
AD16
INTA#
AD30
AD25
AD15
AD27
PCI_IDSEL#
C/BE2#
SERR#
INTB#
AD19
AD18
PCI_TRST#
AD14
M66EN
PCI_RST#
AD28
LOCK#
PAR
AD[31:0]
INTC#
AD29
AD26
C/BE1#
PCI_TCK
AD17
TRDY#
GNT#
PMEIN#
C/BE3#
AD23
AD5
ACK64#
AD8
REQ64#
AD31
AD24
AD10
AD7
AD3
AD2
AD21
AD16
AD0
INTD#
REQ0#
AD22
AD20
PCI_TDI
PERR#
AD13
C/BE0#
AD1
AD9
IRDY#
AD11
AD6
PCI_TMS
FRAME#
DEVSEL#
STOP#
AD12
AD4
PCI_CLK
REQ3#
REQ2#
REQ1#
REQ0#
TRDY#
IRDY#
PCI_TCK
PCI_TDI
FRAME#
STOP#
PMEIN#
PERR#
SERR#
PCI_TMS
PCI_TRST#
LOCK#
DEVSEL#
INTD#
INTC#
INTB#
PCI_RST#
INTA#
ACK64#
REQ64#
AD20
PCI_IDSEL#
+12VN12VCC +VI/O3.3VCC 5VCC 5VCC 3.3VCC
+VI/O
+VI/O
M66EN
REQ1#
REQ2#
REQ3#
INTA#
INTC#
PCI_RST#
GNT#
PMEIN#
FRAME#
TRDY#
STOP#
PAR
INTB#
INTD#
PCI_CLK
REQ0#
AD[31:0]
C/BE3#
C/BE2#
IRDY#
DEVSEL#
C/BE0#
PERR#
SERR#
C/BE1#
LOCK#
Title
Size Document Number Rev
Date: Sheet
of
1.0
PCI Connector, Pull-Ups
PLX TECHNOLOGY, INC.
870 Maude Ave, Sunnyvale, CA 94085
B
45Wednesday, September 08, 2010
www.plxtech.com
PEX 8112 FWD. RISER
Title
Size Document Number Rev
Date: Sheet
of
1.0
PCI Connector, Pull-Ups
PLX TECHNOLOGY, INC.
870 Maude Ave, Sunnyvale, CA 94085
B
45Wednesday, September 08, 2010
www.plxtech.com
PEX 8112 FWD. RISER
Title
Size Document Number Rev
Date: Sheet
of
1.0
PCI Connector, Pull-Ups
PLX TECHNOLOGY, INC.
870 Maude Ave, Sunnyvale, CA 94085
B
45Wednesday, September 08, 2010
www.plxtech.com
PEX 8112 FWD. RISER
RN75.1K RN75.1K
1
2
3
45
6
7
8
RN32.7K RN32.7K
1
2
3
45
6
7
8
R14 100R14 100
RN42.7K RN42.7K
1
2
3
45
6
7
8
R13 100R13 100
R26 2.7KR26 2.7K
J3
RT-HD2-GT120ECN
J3
RT-HD2-GT120ECN
TRST#
A1
-12V
B1
+12V
A2
TCK
B2
TMS
A3
GND
B3
TDI
A4
TDO
B4
+5V
A5
+5V
B5
INTA#
A6
+5V
B6
INTC#
A7
INTB#
B7
+5V
A8
INTD#
B8
RESERVED
A9
PRSNT1#
B9
VIO
A10
RESERVED
B10
RESERVED
A11
PRSNT2#
B11
3.3VAUX
A14
RESERVED
B14
RST#
A15
GND
B15
VIO
A16
CLK
B16
GNT#
A17
GND
B17
GND
A18
REQ#
B18
PME#
A19
VIO
B19
AD30
A20
AD31
B20
+3.3V
A21
AD29
B21
AD28
A22
GND
B22
AD26
A23
AD27
B23
GND
A24
AD25
B24
AD24
A25
+3.3V
B25
IDSEL
A26
C/BE3#
B26
+3.3V
A27
AD23
B27
AD22
A28
GND
B28
AD20
A29
AD21
B29
GND
A30
AD19
B30
AD18
A31
+3.3V
B31
AD16
A32
AD17
B32
+3.3V
A33
C/BE2#
B33
FRAME#
A34
GND
B34
GND
A35
IRDY#
B35
TRDY#
A36
+3.3V
B36
GND
A37
DEVSEL#
B37
STOP#
A38
GND
B38
+3.3V
A39
LOCK#
B39
SDONE
A40
PERR#
B40
SBO#
A41
+3.3V
B41
GND
A42
SERR#
B42
PAR
A43
+3.3V
B43
AD15
A44
C/BE1#
B44
+3.3V
A45
AD14
B45
AD13
A46
GND
B46
AD11
A47
AD12
B47
GND
A48
AD10
B48
AD9
A49
M66EN
B49
C/BE0#
A52
AD8
B52
+3.3V
A53
AD7
B53
AD6
A54
+3.3V
B54
AD4
A55
AD5
B55
GND
A56
AD3
B56
AD2
A57
GND
B57
AD0
A58
AD1
B58
VIO
A59
VIO
B59
REQ64#
A60
ACK64#
B60
+5V
A61
+5V
B61
+5V
A62
+5V
B62
GND
B50
GND
B51
GND
A50
GND
A51
R27 2.7KR27 2.7K
C32
0.01 uF
C32
0.01 uF
12
R28 2.7KR28 2.7K
RN6 2.7KRN6 2.7K
1
2
3
4 5
6
7
8
R29 2.7KR29 2.7K
RN22.7K RN22.7K
1
2
3
45
6
7
8
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
POWER
+1.5 V for PEX 8112 (core, VTT)
+12V, +5V Supplies for PCI Slot
-12 V @ 200 mA max. for PCI
Install R85 and NOT R86 for 3.3V PCI Signalling
Install R86 and NOT R85 for 5V PCI Signalling
PCI Signalling Voltage (+VIO) Option Jumpers
PCI Slot Power Bypass Caps
Place caps close to PCI slot power pins
Molex p/n
0022111041
Toko p/n
S1023AS-470M
1.5VCC
N12VCC
+12V
5VCC
3.3VCC
3.3VCC
5VCC
1.5VCC
N12VCC
3.3VCC
+VI/O
+12V
5VCC
3.3VCC
N12VCC
+VI/O
+12V
5VCC
Title
Size Document Number Rev
Date: Sheet
of
1.0
Power
PLX TECHNOLOGY, INC.
870 Maude Ave, Sunnyvale, CA 94085
C
55Wednesday, September 08, 2010
www.plxtech.com
PEX 8112 FWD. RISER
Title
Size Document Number Rev
Date: Sheet
of
1.0
Power
PLX TECHNOLOGY, INC.
870 Maude Ave, Sunnyvale, CA 94085
C
55Wednesday, September 08, 2010
www.plxtech.com
PEX 8112 FWD. RISER
Title
Size Document Number Rev
Date: Sheet
of
1.0
Power
PLX TECHNOLOGY, INC.
870 Maude Ave, Sunnyvale, CA 94085
C
55Wednesday, September 08, 2010
www.plxtech.com
PEX 8112 FWD. RISER
C55
0.1 uF
C55
0.1 uF
R20 47 (1206)R20 47 (1206)
C40
0.1 uF
C40
0.1 uF
C56
0.1 uF
C56
0.1 uF
C58
0.1 uF
C58
0.1 uF
C64
10 uF
C64
10 uF
C41
0.1 uF
C41
0.1 uF
L2
47 uH
L2
47 uH
1 2
C57
0.1 uF
C57
0.1 uF
C59
0.1 uF
C59
0.1 uF
R15
0.01 (1206)
R15
0.01 (1206)
C38
10 uF
C38
10 uF
R19 0.01 (1206)R19 0.01 (1206)
C42
0.1 uF
C42
0.1 uF
C60
0.1 uF
C60
0.1 uF
C39
10 uF
C39
10 uF
C43
0.1 uF
C43
0.1 uF
+
C70
22 uF/16V
+
C70
22 uF/16V
1 2
C61
0.1 uF
C61
0.1 uF
+
C36
10 uF
+
C36
10 uF
12
R17 0.01 (1206)R17 0.01 (1206)
U4
MAX765
U4
MAX765
OUT
1
SHDN
3
REF
4
FB
2
LX
8
V+
6
V+
7
C44
0.1 uF
C44
0.1 uF
C62
0.1 uF
C62
0.1 uF
R18
0.01 (1206)
R18
0.01 (1206)
C45
0.1 uF
C45
0.1 uF
C48
10 uF
C48
10 uF
C46
0.1 uF
C46
0.1 uF
J4
HEADER 4
J4
HEADER 4
1
2
3
4
C66
0.1 uF
C66
0.1 uF
C49
10 uF
C49
10 uF
C63
0.1 uF
C63
0.1 uF
C47
0.1 uF
C47
0.1 uF
C51
0.1 uF
C51
0.1 uF
C67
0.1 uF
C67
0.1 uF
U3
LP2992
U3
LP2992
VIN
1
VOUT
5
GND
2
BYPASS
4
ON/OFF
3
C50
0.1 uF
C50
0.1 uF
C68
0.1 uF
C68
0.1 uF
C52
0.1 uF
C52
0.1 uF
D2
B130L
D2
B130L
C69
0.1 uF
C69
0.1 uF
C71
0.1 uF
C71
0.1 uF
12
C33
22 uF/16V
C33
22 uF/16V
C53
0.1 uF
C53
0.1 uF
C65
10 uF
C65
10 uF
C54
0.1 uF
C54
0.1 uF
C72
0.1 uF
C72
0.1 uF
12
C37
0.01 uF
C37
0.01 uF
12
C35
1 uF
C35
1 uF
12
C34
0.1 uF
C34
0.1 uF
R16 0.01 (1206)R16 0.01 (1206)
/
