NXP MPC8245 Reference guide

Type
Reference guide
Programming Environments Manual
for 32-Bit Implementations of the
PowerPC™ Architecture
MPCFPE32B
Rev. 3, 9/2005
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. The PowerPC
name is a trademark of IBM Corp. and is used under license. All other product or service names are
the property of their respective owners.
© Freescale Semiconductor, Inc., 2005. All rights reserved.
Document Number: MPCFPE32B
Rev. 3, 9/2005
Information in this document is provided solely to enable system and software
implementers to use Freescale Semiconductor products. There are no express or
implied copyright licenses granted hereunder to design or fabricate any integrated
circuits or integrated circuits based on the information in this document.
Freescale Semiconductor reserves the right to make changes without further notice to
any products herein. Freescale Semiconductor makes no warranty, representation or
guarantee regarding the suitability of its products for any particular purpose, nor does
Freescale Semiconductor assume any liability arising out of the application or use of
any product or circuit, and specifically disclaims any and all liability, including without
limitation consequential or incidental damages. “Typical” parameters which may be
provided in Freescale Semiconductor data sheets and/or specifications can and do
vary in different applications and actual performance may vary over time. All operating
parameters, including “Typicals” must be validated for each customer application by
customer’s technical experts. Freescale Semiconductor does not convey any license
under its patent rights nor the rights of others. Freescale Semiconductor products are
not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life,
or for any other application in which the failure of the Freescale Semiconductor product
could create a situation where personal injury or death may occur. Should Buyer
purchase or use Freescale Semiconductor products for any such unintended or
unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all
claims, costs, damages, and expenses, and reasonable attorney fees arising out of,
directly or indirectly, any claim of personal injury or death associated with such
unintended or unauthorized use, even if such claim alleges that Freescale
Semiconductor was negligent regarding the design or manufacture of the part.
How to Reach Us:
Home Page:
www.freescale.com
email:
support@freescale.com
USA/Europe or Locations Not Listed:
Freescale Semiconductor
Technical Information Center, CH370
1300 N. Alma School Road
Chandler, Arizona 85224
(800) 521-6274
480-768-2130
support@freescale.com
Europe, Middle East, and Africa:
Freescale Halbleiter Deutschland GmbH
Technical Information Center
Schatzbogen 7
81829 Muenchen, Germany
+44 1296 380 456 (English)
+46 8 52200080 (English)
+49 89 92103 559 (German)
+33 1 69 35 48 48 (French)
support@freescale.com
Japan:
Freescale Semiconductor Japan Ltd.
Headquarters
ARCO Tower 15F
1-8-1, Shimo-Meguro, Meguro-ku
Tokyo 153-0064, Japan
0120 191014
+81 2666 8080
support.japan@freescale.com
Asia/Pacific:
Freescale Semiconductor Hong Kong Ltd.
Technical Information Center
2 Dai King Street
Tai Po Industrial Estate,
Tai Po, N.T., Hong Kong
+800 2666 8080
support.asia@freescale.com
For Literature Requests Only:
Freescale Semiconductor
Literature Distribution Center
P.O. Box 5405
Denver, Colorado 80217
(800) 441-2447
303-675-2140
Fax: 303-675-2150
LDCForFreescaleSemiconductor
@hibbertgroup.com
Overview
Register Set
Operand Conventions
Addressing Modes
Memory Management Unit
Instruction Set
Instruction Set Listings
Multiple-Precision Shifts
Floating-Point Models
Synchronization Programming Examples
Glossary
1
2
3
4
5
6
7
8
A
B
C
D
GLO
E
F
Cache
Exceptions
Simplified Mnemonics
PEM Revision History
Index IND
Overview
Register Set
Operand Conventions
Addressing Modes
Memory Management Unit
Instruction Set
Instruction Set Listings
Multiple-Precision Shifts
Floating-Point Models
Synchronization Programming Examples
Glossary
1
2
3
4
5
6
7
8
A
B
C
D
GLO
E
F
Cache
Exceptions
Simplified Mnemonics
PEM Revision History
IndexIND
Programming Environments Manual for 32-Bit Implementations of the PowerPC Architecture, Rev. 3
Freescale Semiconductor v
Contents
Paragraph
Number Title
Page
Number
Chapter 1
Overview
1.1 PowerPC Architecture Overview..................................................................................... 1-2
1.1.1 The Levels of the PowerPC Architecture .................................................................... 1-3
1.1.2 Latitude within the Levels of the Architecture............................................................1-4
1.1.3 Features Not Defined by the PowerPC Architecture................................................... 1-4
1.2 The Architectural Models................................................................................................ 1-5
1.2.1 Registers and Programming Model ............................................................................. 1-5
1.2.2 Operand Conventions .................................................................................................. 1-7
1.2.2.1 Byte Ordering .......................................................................................................... 1-7
1.2.2.2 Data Organization in Memory and Data Transfers.................................................. 1-8
1.2.2.3 Floating-Point Conventions..................................................................................... 1-8
1.2.3 Instruction Set and Addressing Modes........................................................................ 1-8
1.2.3.1 Instruction Set..........................................................................................................1-8
1.2.3.2 Calculating Effective Addresses............................................................................ 1-10
1.2.4 Cache Model..............................................................................................................1-10
1.2.5 Interrupt Model.......................................................................................................... 1-10
1.2.6 Memory Management Model (MMU)....................................................................... 1-11
Chapter 2
Register Set
2.1 UISA Register Set............................................................................................................2-1
2.1.1 General-Purpose Registers (GPRs).............................................................................. 2-3
2.1.2 Floating-Point Registers (FPRs).................................................................................. 2-3
2.1.3 Condition Register (CR).............................................................................................. 2-5
2.1.3.1 Condition Register CR0 Field Definition................................................................2-5
2.1.3.2 Condition Register CR1 Field Definition................................................................2-6
2.1.3.3 Condition Register CRn Field—Compare Instruction ............................................2-6
2.1.4 Floating-Point Status and Control Register (FPSCR).................................................. 2-6
2.1.5 XER Register (XER) ................................................................................................... 2-9
2.1.6 Link Register (LR)..................................................................................................... 2-10
2.1.7 Count Register (CTR)................................................................................................ 2-11
2.2 VEA Register Set—Time Base...................................................................................... 2-12
2.2.1 Reading the Time Base.............................................................................................. 2-14
2.2.2 Computing Time of Day from the Time Base ...........................................................2-15
2.3 OEA Register Set........................................................................................................... 2-15
2.3.1 Machine State Register (MSR).................................................................................. 2-18
Programming Environments Manual for 32-Bit Implementations of the PowerPC Architecture, Rev. 3
vi Freescale Semiconductor
Contents
Paragraph
Number Title
Page
Number
2.3.2 Processor Version Register (PVR)............................................................................. 2-21
2.3.3 BAT Registers............................................................................................................ 2-21
2.3.4 SDR1..........................................................................................................................2-24
2.3.5 Segment Registers...................................................................................................... 2-25
2.3.6 Data Address Register (DAR) ................................................................................... 2-26
2.3.7 SPRG0–SPRG3 ......................................................................................................... 2-26
2.3.8 DSISR........................................................................................................................2-27
2.3.9 Machine Status Save/Restore Register 0 (SRR0)...................................................... 2-27
2.3.10 Machine Status Save/Restore Register 1 (SRR1)...................................................... 2-28
2.3.11 Floating-Point Exception Cause Register (FPECR).................................................. 2-28
2.3.12 Time Base Facility (TB)—OEA................................................................................2-29
2.3.12.1 Writing to the Time Base....................................................................................... 2-29
2.3.13 Decrementer Register (DEC)..................................................................................... 2-29
2.3.13.1 Decrementer Operation.......................................................................................... 2-30
2.3.13.2 Writing and Reading the DEC............................................................................... 2-30
2.3.14 Data Address Breakpoint Register (DABR )............................................................. 2-30
2.3.15 External Access Register (EAR)................................................................................ 2-32
2.3.16 Processor Identification Register (PIR)..................................................................... 2-32
2.3.17 Synchronization Requirements for Special Registers and for Lookaside Buffers..... 2-33
Chapter 3
Operand Conventions
3.1 Data Organization in Memory and Data Transfers..........................................................3-1
3.1.1 Aligned and Misaligned Accesses............................................................................... 3-1
3.1.2 Byte Ordering ..............................................................................................................3-2
3.1.3 Structure Mapping Examples....................................................................................... 3-2
3.1.3.1 Big-Endian Mapping ............................................................................................... 3-2
3.1.3.2 Little-Endian Mapping.............................................................................................3-3
3.1.4 Byte Ordering in PowerPC Architecture ..................................................................... 3-4
3.1.4.1 Aligned Scalars in Little-Endian Mode................................................................... 3-4
3.1.4.2 Misaligned Scalars in Little-Endian Mode.............................................................. 3-6
3.1.4.3 Nonscalars................................................................................................................3-7
3.1.4.4 Instruction Addressing in Little-Endian Mode........................................................ 3-7
3.1.4.5 Input/Output Data Transfer Addressing in Little-Endian Mode..............................3-8
3.2 Operand Placement and Performance—VEA.................................................................. 3-8
3.2.1 Summary of Performance Effects................................................................................ 3-8
3.2.2 Instruction Restart...................................................................................................... 3-10
3.3 Floating-Point Execution Models—UISA..................................................................... 3-10
3.3.1 Floating-Point Data Format ....................................................................................... 3-11
3.3.1.1 Value Representation ............................................................................................. 3-12
Programming Environments Manual for 32-Bit Implementations of the PowerPC Architecture, Rev. 3
Freescale Semiconductor vii
Contents
Paragraph
Number Title
Page
Number
3.3.1.2 Binary Floating-Point Numbers............................................................................. 3-13
3.3.1.3 Normalized Numbers (±NORM)........................................................................... 3-14
3.3.1.4 Zero Values (±0) .................................................................................................... 3-14
3.3.1.5 Denormalized Numbers (±DENORM).................................................................. 3-14
3.3.1.6 Infinities (±)........................................................................................................ 3-15
3.3.1.7 Not a Numbers (NaNs).......................................................................................... 3-15
3.3.2 Sign of Result.............................................................................................................3-16
3.3.3 Normalization and Denormalization.......................................................................... 3-17
3.3.4 Data Handling and Precision ..................................................................................... 3-17
3.3.5 Rounding....................................................................................................................3-19
3.3.6 Floating-Point Program Exceptions........................................................................... 3-21
3.3.6.1 Invalid Operation and Zero Divide Exception Conditions....................................3-27
3.3.6.1.1 Invalid Operation Exception Condition............................................................. 3-29
3.3.6.1.2 Zero Divide Exception Condition...................................................................... 3-30
3.3.6.2 Overflow, Underflow, and Inexact Exception Conditions.....................................3-31
3.3.6.2.1 Overflow Exception Condition.......................................................................... 3-33
3.3.6.2.2 Underflow Exception Condition........................................................................ 3-34
3.3.6.2.3 Inexact Exception Condition ............................................................................. 3-35
Chapter 4
Addressing Modes and Instruction Set Summary
4.1 Conventions ..................................................................................................................... 4-2
4.1.1 Sequential Execution Model........................................................................................ 4-2
4.1.2 Classes of Instructions ................................................................................................. 4-2
4.1.2.1 Definition of Boundedly Undefined........................................................................ 4-3
4.1.2.2 Defined Instruction Class ........................................................................................ 4-3
4.1.2.2.1 Preferred Instruction Forms................................................................................. 4-3
4.1.2.2.2 Invalid Instruction Forms .................................................................................... 4-3
4.1.2.2.3 Optional Instructions ........................................................................................... 4-4
4.1.2.3 Illegal Instruction Class........................................................................................... 4-4
4.1.2.4 Reserved Instructions............................................................................................... 4-5
4.1.3 Memory Addressing .................................................................................................... 4-5
4.1.3.1 Memory Operands ................................................................................................... 4-5
4.1.3.2 Effective Address Calculation ................................................................................. 4-6
4.1.4 Synchronizing Instructions.......................................................................................... 4-6
4.1.4.1 Context Synchronizing Instructions ........................................................................ 4-7
4.1.4.2 Execution Synchronizing Instructions..................................................................... 4-7
4.1.5 Interrupt Summary....................................................................................................... 4-7
4.1.6 Recommended Simplified Mnemonics........................................................................ 4-8
4.2 UISA Instructions ............................................................................................................4-8
Programming Environments Manual for 32-Bit Implementations of the PowerPC Architecture, Rev. 3
viii Freescale Semiconductor
Contents
Paragraph
Number Title
Page
Number
4.2.1 Integer Instructions ...................................................................................................... 4-8
4.2.1.1 Integer Arithmetic Instructions................................................................................ 4-9
4.2.1.2 Integer Compare Instructions ................................................................................ 4-12
4.2.1.3 Integer Logical Instructions................................................................................... 4-13
4.2.1.4 Integer Rotate and Shift Instructions..................................................................... 4-15
4.2.1.4.1 Integer Rotate Instructions................................................................................. 4-15
4.2.1.4.2 Integer Shift Instructions ................................................................................... 4-16
4.2.2 Floating-Point Instructions ........................................................................................ 4-17
4.2.2.1 Floating-Point Arithmetic Instructions.................................................................. 4-18
4.2.2.2 Floating-Point Multiply-Add Instructions............................................................. 4-20
4.2.2.3 Floating-Point Rounding and Conversion Instructions .........................................4-21
4.2.2.4 Floating-Point Compare Instructions..................................................................... 4-22
4.2.2.5 Floating-Point Status and Control Register Instructions .......................................4-22
4.2.2.6 Floating-Point Move Instructions.......................................................................... 4-23
4.2.3 Load and Store Instructions ....................................................................................... 4-24
4.2.3.1 Integer Load and Store Address Generation..........................................................4-24
4.2.3.1.1 Register Indirect with Immediate Index Addressing
for Integer Loads and Stores.......................................................................... 4-25
4.2.3.1.2 Register Indirect with Index Addressing for Integer Loads and Stores............. 4-25
4.2.3.1.3 Register Indirect Addressing for Integer Loads and Stores...............................4-26
4.2.3.2 Integer Load Instructions....................................................................................... 4-27
4.2.3.3 Integer Store Instructions....................................................................................... 4-29
4.2.3.4 Integer Load and Store with Byte-Reverse Instructions........................................ 4-30
4.2.3.5 Integer Load and Store Multiple Instructions........................................................4-31
4.2.3.6 Integer Load and Store String Instructions............................................................ 4-31
4.2.3.7 Floating-Point Load and Store Address Generation.............................................. 4-32
4.2.3.7.1 Register Indirect with Immediate Index Addressing for Floating-Point
Loads and Stores............................................................................................ 4-32
4.2.3.7.2 Register Indirect with Index Addressing for Floating-Point
Loads and Stores............................................................................................ 4-33
4.2.3.8 Floating-Point Load Instructions........................................................................... 4-34
4.2.3.9 Floating-Point Store Instructions........................................................................... 4-35
4.2.4 Branch and Flow Control Instructions....................................................................... 4-36
4.2.4.1 Branch Instruction Address Calculation................................................................ 4-37
4.2.4.1.1 Branch Relative Addressing Mode.................................................................... 4-37
4.2.4.1.2 Branch Conditional to Relative Addressing Mode............................................ 4-38
4.2.4.1.3 Branch to Absolute Addressing Mode............................................................... 4-39
4.2.4.1.4 Branch Conditional to Absolute Addressing Mode...........................................4-40
4.2.4.1.5 Branch Conditional to Link Register Addressing Mode...................................4-41
4.2.4.1.6 Branch Conditional to Count Register Addressing Mode.................................4-41
Programming Environments Manual for 32-Bit Implementations of the PowerPC Architecture, Rev. 3
Freescale Semiconductor ix
Contents
Paragraph
Number Title
Page
Number
4.2.4.2 Conditional Branch Control................................................................................... 4-42
4.2.4.3 Branch Instructions................................................................................................ 4-45
4.2.4.4 Simplified Mnemonics for Branch Processor Instructions.................................... 4-45
4.2.4.5 Condition Register Logical Instructions................................................................ 4-46
4.2.4.6 Trap Instructions.................................................................................................... 4-46
4.2.4.7 System Linkage Instruction—UISA......................................................................4-47
4.2.5 Processor Control Instructions—UISA ..................................................................... 4-47
4.2.5.1 Move to/from Condition Register Instructions...................................................... 4-47
4.2.5.2 Move to/from Special-Purpose Register Instructions (UISA)...............................4-47
4.2.6 Memory Synchronization Instructions—UISA .........................................................4-48
4.3 VEA Instructions ........................................................................................................... 4-49
4.3.1 Processor Control Instructions—VEA....................................................................... 4-50
4.3.2 Memory Synchronization Instructions—VEA .......................................................... 4-51
4.3.3 Memory Control Instructions—VEA ........................................................................ 4-51
4.3.3.1 User-Level Cache Instructions—VEA .................................................................. 4-52
4.3.4 External Control Instructions (Optional)................................................................... 4-54
4.4 OEA Instructions ........................................................................................................... 4-55
4.4.1 System Linkage Instructions—OEA ......................................................................... 4-55
4.4.2 Processor Control Instructions—OEA....................................................................... 4-56
4.4.2.1 Move to/from Machine State Register Instructions...............................................4-56
4.4.2.2 Move to/from Special-Purpose Register Instructions (OEA)................................4-56
4.4.3 Memory Control Instructions—OEA ........................................................................ 4-57
4.4.3.1 Supervisor-Level Cache Management Instruction ................................................4-57
4.4.3.2 Segment Register Manipulation Instructions.........................................................4-58
4.4.3.3 Translation Lookaside Buffer Management Instructions ......................................4-59
Chapter 5
Cache Model and Memory Coherency
5.1 Overview..........................................................................................................................5-1
5.2 The Virtual Environment ................................................................................................. 5-1
5.2.1 Memory Access Ordering............................................................................................ 5-2
5.2.1.1 Enforce In-Order Execution of I/O Instruction (eieio)............................................ 5-2
5.2.1.2 Synchronize Instruction........................................................................................... 5-3
5.2.2 Atomicity ..................................................................................................................... 5-3
5.2.3 Cache Model................................................................................................................5-4
5.2.4 Memory Coherency ..................................................................................................... 5-4
5.2.4.1 Memory/Cache Access Modes................................................................................ 5-4
5.2.4.1.1 Pages Designated as Write-Through....................................................................5-5
5.2.4.1.2 Pages Designated as Caching-Inhibited ..............................................................5-5
5.2.4.1.3 Pages Designated as Memory Coherency Required............................................5-5
Programming Environments Manual for 32-Bit Implementations of the PowerPC Architecture, Rev. 3
x Freescale Semiconductor
Contents
Paragraph
Number Title
Page
Number
5.2.4.1.4 Pages Designated as Memory Coherency Not Required..................................... 5-5
5.2.4.1.5 Pages Designated as Guarded.............................................................................. 5-6
5.2.4.2 Coherency Precautions ............................................................................................ 5-6
5.2.5 VEA Cache Management Instructions ........................................................................ 5-6
5.2.5.1 Data Cache Instructions........................................................................................... 5-7
5.2.5.1.1 Data Cache Block Touch (dcbt) and
Data Cache Block Touch for Store (dcbtst) Instructions................................ 5-7
5.2.5.1.2 Data Cache Block Set to Zero (dcbz) Instruction ...............................................5-7
5.2.5.1.3 Data Cache Block Store (dcbst) Instruction........................................................5-8
5.2.5.1.4 Data Cache Block Flush (dcbf) Instruction......................................................... 5-8
5.2.5.2 Instruction Cache Instructions................................................................................. 5-9
5.2.5.2.1 Instruction Cache Block Invalidate Instruction (icbi)......................................... 5-9
5.2.5.2.2 Instruction Synchronize Instruction (isync)......................................................5-10
5.2.6 Shared Memory.......................................................................................................... 5-10
5.2.6.1 Memory Access Ordering...................................................................................... 5-10
5.2.6.1.1 Programming Considerations ............................................................................ 5-12
5.2.6.1.2 Programming Examples .................................................................................... 5-14
5.2.6.2 Lock Acquisition and Import Barriers................................................................... 5-14
5.2.6.2.1 Acquire Lock and Import Shared Memory........................................................ 5-14
5.2.6.2.2 Obtain Pointer and Import Shared Memory ...................................................... 5-15
5.3 The Operating Environment .......................................................................................... 5-15
5.3.1 Memory/Cache Access Attributes ............................................................................. 5-16
5.3.1.1 Write-Through Attribute (W) ................................................................................5-17
5.3.1.2 Caching-Inhibited Attribute (I).............................................................................. 5-17
5.3.1.3 Memory Coherency Attribute (M)......................................................................... 5-18
5.3.1.4 W, I, and M Bit Combinations............................................................................... 5-18
5.3.1.5 The Guarded Attribute (G) .................................................................................... 5-19
5.3.1.5.1 Definition of Speculative and Out-of-Order Memory Accesses .......................5-19
5.3.1.5.2 Performing Operations Speculatively................................................................ 5-19
5.3.1.5.3 Guarded Memory............................................................................................... 5-20
5.3.1.5.4 Speculative Accesses to Guarded Memory .......................................................5-21
5.3.2 I/O Interface Considerations......................................................................................5-21
5.3.3 OEA Cache Management Instruction—Data Cache Block Invalidate (dcbi)........... 5-22
Chapter 6
Interrupts
6.1 Overview..........................................................................................................................6-1
6.2 Interrupt Classes ..............................................................................................................6-2
6.2.1 Precise Interrupts .........................................................................................................6-4
6.2.2 Context Synchronization.............................................................................................. 6-4
Programming Environments Manual for 32-Bit Implementations of the PowerPC Architecture, Rev. 3
Freescale Semiconductor xi
Contents
Paragraph
Number Title
Page
Number
6.2.2.1 Execution Synchronization...................................................................................... 6-5
6.2.2.2 Synchronous/Precise Interrupts............................................................................... 6-5
6.2.2.3 Asynchronous Interrupts.......................................................................................... 6-6
6.2.2.3.1 System Reset and Machine Check Interrupts...................................................... 6-6
6.2.2.3.2 External and Decrementer Interrupts................................................................... 6-6
6.2.3 Imprecise Interrupts..................................................................................................... 6-7
6.2.3.1 Imprecise Interrupt Status Description.................................................................... 6-7
6.2.3.2 Recoverability of Imprecise Floating-Point Interrupts............................................6-8
6.2.4 Partially Executed Instructions.................................................................................... 6-8
6.2.5 Interrupt Priorities........................................................................................................6-9
6.3 Interrupt Processing ....................................................................................................... 6-11
6.3.1 Enabling and Disabling Interrupts............................................................................. 6-13
6.3.2 Steps for Interrupt Processing.................................................................................... 6-14
6.3.3 Returning from an Interrupt Handler......................................................................... 6-14
6.4 Process Switching.......................................................................................................... 6-15
6.5 Interrupt Definitions ...................................................................................................... 6-15
6.5.1 System Reset Interrupt (0x00100).............................................................................6-16
6.5.2 Machine Check Interrupt (0x00200)..........................................................................6-17
6.5.3 Data Storage Interrupt (0x00300).............................................................................. 6-18
6.5.4 Instruction Storage Interrupt (0x00400) .................................................................... 6-20
6.5.5 External Interrupt (0x00500) ..................................................................................... 6-21
6.5.6 Alignment Interrupt (0x00600)..................................................................................6-22
6.5.6.1 Integer Alignment Interrupts ................................................................................. 6-23
6.5.6.1.1 Page Address Translation Access Considerations.............................................6-23
6.5.6.2 Little-Endian Mode Alignment Interrupts.............................................................6-24
6.5.6.3 Interpretation of the DSISR as Set by an Alignment Interrupt.............................. 6-24
6.5.7 Program Interrupt (0x00700) .................................................................................... 6-25
6.5.8 Floating-Point Unavailable Interrupt (0x00800) .......................................................6-27
6.5.9 Decrementer Interrupt (0x00900).............................................................................. 6-28
6.5.10 System Call Interrupt (0x00C00)............................................................................... 6-28
6.5.11 Trace Interrupt (0x00D00)......................................................................................... 6-29
6.5.12 Floating-Point Assist Interrupt (0x00E00) ................................................................6-30
Chapter 7
Memory Management
7.1 Overview..........................................................................................................................7-1
7.2 MMU Features.................................................................................................................7-2
7.3 MMU Overview............................................................................................................... 7-2
7.3.1 Memory Addressing .................................................................................................... 7-3
7.3.1.1 Predefined Physical Memory Locations.................................................................. 7-3
Programming Environments Manual for 32-Bit Implementations of the PowerPC Architecture, Rev. 3
xii Freescale Semiconductor
Contents
Paragraph
Number Title
Page
Number
7.3.2 MMU Organization...................................................................................................... 7-4
7.3.3 Address Translation Mechanisms................................................................................ 7-5
7.3.4 Memory Protection Facilities.......................................................................................7-6
7.3.5 Page History Information............................................................................................. 7-8
7.3.6 General Flow of MMU Address Translation............................................................... 7-8
7.3.6.1 Real Addressing Mode and Block Address Translation Selection..........................7-8
7.3.6.2 Page and Direct-Store Address Translation Selection............................................. 7-9
7.3.6.2.1 Selection of Page Address Translation.............................................................. 7-10
7.3.7 MMU Interrupts Summary ........................................................................................ 7-11
7.3.8 MMU Instructions and Register Summary................................................................ 7-12
7.3.9 TLB Entry Invalidation.............................................................................................. 7-15
7.4 Real Addressing Mode................................................................................................... 7-15
7.5 Block Address Translation............................................................................................. 7-16
7.5.1 BAT Array Organization............................................................................................ 7-16
7.5.2 Recognition of Addresses in BAT Arrays.................................................................. 7-18
7.5.3 BAT Register Implementation of BAT Array............................................................7-20
7.5.4 Block Memory Protection.......................................................................................... 7-23
7.5.5 Block Physical Address Generation .......................................................................... 7-25
7.5.6 Block Address Translation Summary........................................................................ 7-26
7.6 Memory Segment Model ............................................................................................... 7-26
7.6.1 Recognition of Addresses in Segments ..................................................................... 7-26
7.6.1.1 Selection of Memory Segments............................................................................. 7-27
7.6.1.2 Selection of Direct-Store Segments....................................................................... 7-27
7.6.2 Page Address Translation Overview.......................................................................... 7-28
7.6.2.1 Segment Register Definitions................................................................................ 7-28
7.6.2.1.1 Segment Register Format .................................................................................. 7-29
7.6.2.2 Page Table Entry (PTE) Definitions ...................................................................... 7-29
7.6.2.2.1 PTE Format........................................................................................................ 7-30
7.6.3 Page History Recording............................................................................................. 7-30
7.6.3.1 Reference Bit ......................................................................................................... 7-31
7.6.3.2 Change Bit ............................................................................................................. 7-32
7.6.3.3 Scenarios for Reference and Change Bit Recording ............................................. 7-32
7.6.3.4 Synchronization of Memory Accesses and Reference and Change
Bit Updates ........................................................................................................ 7-33
7.6.4 Page Memory Protection ........................................................................................... 7-34
7.6.5 Page Address Translation Summary.......................................................................... 7-36
7.7 Hashed Page Tables ....................................................................................................... 7-38
7.7.1 Page Table Definition ................................................................................................7-38
7.7.1.1 SDR1 Register Definitions .................................................................................... 7-39
7.7.1.2 Page Table Size...................................................................................................... 7-40
7.7.1.3 Page Table Hashing Functions............................................................................... 7-41
Programming Environments Manual for 32-Bit Implementations of the PowerPC Architecture, Rev. 3
Freescale Semiconductor xiii
Contents
Paragraph
Number Title
Page
Number
7.7.1.4 Page Table Addresses ............................................................................................ 7-42
7.7.1.5 Page Table Structure Summary.............................................................................. 7-45
7.7.1.6 Page Table Structure Examples ............................................................................. 7-45
7.7.1.7 PTEG Address Mapping Examples ....................................................................... 7-47
7.7.2 Page Table Search Operation..................................................................................... 7-50
7.7.2.1 Flow for Page Table Search Operation.................................................................. 7-50
7.7.3 Page Table Updates.................................................................................................... 7-51
7.7.3.1 Adding a Page Table Entry.................................................................................... 7-53
7.7.3.2 Deleting a Page Table Entry .................................................................................. 7-53
7.7.4 Segment Register Updates......................................................................................... 7-53
7.8 Direct-Store Segment Address Translation.................................................................... 7-53
7.8.1 Segment Registers for Direct-Store Segments...........................................................7-54
7.8.2 Direct-Store Segment Accesses................................................................................. 7-54
7.8.3 Direct-Store Segment Protection ............................................................................... 7-55
7.8.4 Instructions Not Supported in Direct-Store Segments...............................................7-55
7.8.5 Instructions with No Effect in Direct-Store Segments .............................................. 7-55
7.8.6 Direct-Store Segment Translation Summary Flow.................................................... 7-55
Chapter 8
Instruction Set
8.1 Instruction Formats..........................................................................................................8-1
8.1.1 Split-Field Notation ..................................................................................................... 8-1
8.1.2 Instruction Fields .........................................................................................................8-2
8.1.3 Notation and Conventions ........................................................................................... 8-3
8.2 Instruction Set................................................................................................................. 8-7
Appendix A
Instruction Set Listings
A.1 Instructions Sorted by Mnemonic (Decimal and Hexadecimal)..................................... A-1
A.2 Instructions Sorted by Primary Opcodes (Decimal and Hexadecimal)........................ A-17
A.3 Instructions Sorted by Mnemonic (Binary) .................................................................. A-26
A.4 Instructions Sorted by Opcode (Binary) ....................................................................... A-42
A.5 Instruction Set Legend.................................................................................................. A-51
Appendix B
Multiple-Precision Shifts
B.1 Overview..........................................................................................................................B-1
B.2 Multiple-Precision Shifts in 32-Bit Implementations......................................................B-1
Programming Environments Manual for 32-Bit Implementations of the PowerPC Architecture, Rev. 3
xiv Freescale Semiconductor
Contents
Paragraph
Number Title
Page
Number
Appendix C
Floating-Point Models
C.1 Execution Model for IEEE Operations............................................................................C-1
C.2 Multiply-Add Type Instruction Execution Model ...........................................................C-3
C.3 Floating-Point Conversions .............................................................................................C-4
C.3.1 Conversion from Floating-Point Number to Signed Fixed-Point Integer Word..........C-4
C.3.2 Conversion from Floating-Point Number to Unsigned Fixed-Point
Integer Word............................................................................................................C-5
C.4 Floating-Point Models .....................................................................................................C-5
C.4.1 Floating-Point Round to Single-Precision Model........................................................C-5
C.4.2 Floating-Point Convert to Integer Model.....................................................................C-9
C.4.3 Floating-Point Convert from Integer Model..............................................................C-11
C.5 Floating-Point Selection ................................................................................................C-12
C.5.1 Comparison to Zero ...................................................................................................C-13
C.5.2 Minimum and Maximum...........................................................................................C-13
C.5.3 Simple If-Then-Else Constructions ...........................................................................C-13
C.5.4 Notes..........................................................................................................................C-13
C.6 Floating-Point Load Instructions ...................................................................................C-14
C.7 Floating-Point Store Instructions...................................................................................C-15
Appendix D
Synchronization Programming Examples
D.1 General Information........................................................................................................ D-1
D.2 Synchronization Primitives............................................................................................. D-2
D.2.1 Fetch and No-Op......................................................................................................... D-2
D.2.2 Fetch and Store ........................................................................................................... D-2
D.2.3 Fetch and Add............................................................................................................. D-2
D.2.4 Fetch and AND........................................................................................................... D-3
D.2.5 Test and Set................................................................................................................. D-3
D.3 Compare and Swap......................................................................................................... D-3
D.4 Lock Acquisition and Release ........................................................................................ D-4
D.5 List Insertion................................................................................................................... D-5
Programming Environments Manual for 32-Bit Implementations of the PowerPC Architecture, Rev. 3
Freescale Semiconductor xv
Contents
Paragraph
Number Title
Page
Number
Appendix E
Simplified Mnemonics for PowerPC Instructions
E.1 Overview..........................................................................................................................E-1
E.2 Subtract Simplified Mnemonics ......................................................................................E-2
E.2.1 Subtract Immediate......................................................................................................E-2
E.2.2 Subtract........................................................................................................................E-2
E.3 Rotate and Shift Simplified Mnemonics..........................................................................E-2
E.3.1 Operations on Words ...................................................................................................E-3
E.4 Branch Instruction Simplified Mnemonics......................................................................E-3
E.4.1 Key Facts about Simplified Branch Mnemonics.........................................................E-5
E.4.2 Eliminating the BO Operand .......................................................................................E-5
E.4.3 Incorporating the BO Branch Prediction .....................................................................E-7
E.4.4 The BI Operand—CR Bit and Field Representations..................................................E-7
E.4.4.1 BI Operand Instruction Encoding............................................................................E-8
E.4.4.1.1 Specifying a CR Bit.............................................................................................E-8
E.4.4.1.2 The crS Operand ...............................................................................................E-10
E.4.5 Simplified Mnemonics that Incorporate the BO Operand.........................................E-10
E.4.5.1 Examples that Eliminate the BO Operand.............................................................E-12
E.4.6 Simplified Mnemonics that Incorporate CR Conditions (Eliminates BO
and Replaces BI with crS).....................................................................................E-14
E.4.6.1 Branch Simplified Mnemonics that Incorporate CR Conditions: Examples.........E-16
E.4.6.2 Branch Simplified Mnemonics that Incorporate CR Conditions: Listings............E-16
E.5 Compare Word Simplified Mnemonics .........................................................................E-19
E.6 Condition Register Logical Simplified Mnemonics......................................................E-20
E.7 Trap Instructions Simplified Mnemonics ......................................................................E-20
E.8 Simplified Mnemonics for Accessing SPRs..................................................................E-22
E.9 Recommended Simplified Mnemonics..........................................................................E-23
E.9.1 No-Op (nop) ..............................................................................................................E-23
E.9.2 Load Immediate (li)...................................................................................................E-23
E.9.3 Load Address (la) ......................................................................................................E-24
E.9.4 Move Register (mr)...................................................................................................E-24
E.9.5 Complement Register (not).......................................................................................E-24
E.9.6 Move to Condition Register (mtcr)...........................................................................E-24
E.10 Comprehensive List of Simplified Mnemonics.............................................................E-24
Appendix F
Revision History
F.1 Changes From Revision 2 to Revision 3 .........................................................................F-1
F.2 Changes From Revision 1 to Revision 2 .........................................................................F-2
Programming Environments Manual for 32-Bit Implementations of the PowerPC Architecture, Rev. 3
xvi Freescale Semiconductor
Contents
Paragraph
Number Title
Page
Number
Programming Environments Manual for 32-Bit Implementations of the PowerPC Architecture, Rev. 3
Freescale Semiconductor xvii
Figures
Figure
Number Title
Page
Number
1-1 Programming Model—PowerPC Registers ............................................................................ 1-6
1-2 Big-Endian Byte and Bit Ordering.......................................................................................... 1-7
2-1 UISA Programming Model—User-Level Registers............................................................... 2-2
2-2 General-Purpose Registers (GPRs)......................................................................................... 2-3
2-3 Floating-Point Registers (FPRs) ............................................................................................. 2-4
2-4 Condition Register (CR) ......................................................................................................... 2-5
2-5 Floating-Point Status and Control Register (FPSCR).............................................................2-7
2-6 XER Register .......................................................................................................................... 2-9
2-7 Link Register (LR)................................................................................................................ 2-10
2-8 Count Register (CTR)........................................................................................................... 2-11
2-9 VEA Programming Model—User-Level Registers Plus Time Base .................................... 2-13
2-10 Time Base (TB)..................................................................................................................... 2-14
2-11 OEA Programming Model—All Registers........................................................................... 2-16
2-12 Machine State Register (MSR) ............................................................................................. 2-18
2-13 Processor Version Register (PVR)........................................................................................ 2-21
2-14 Format of Upper BAT Register............................................................................................. 2-22
2-15 Format of Lower BAT Register ............................................................................................ 2-22
2-16 SDR1 Register Format..........................................................................................................2-24
2-17 Segment Register Format (T = 0) ......................................................................................... 2-25
2-18 Segment Register Format (T = 1) ......................................................................................... 2-25
2-19 Data Address Register (DAR)............................................................................................... 2-26
2-20 SPRG0–SPRG3..................................................................................................................... 2-26
2-21 DSISR ...................................................................................................................................2-27
2-22 Machine Status Save/Restore Register 0 (SRR0) ................................................................. 2-27
2-23 Machine Status Save/Restore Register 1 (SRR1) ................................................................. 2-28
2-24 Decrementer Register (DEC)................................................................................................ 2-29
2-25 Data Address Breakpoint Register (DABR)......................................................................... 2-30
2-26 External Access Register (EAR)........................................................................................... 2-32
2-27 Processor Identification Register (PIR) ................................................................................ 2-33
3-1 C Program Example—Data Structure S.................................................................................. 3-2
3-2 Big-Endian Mapping of Structure S........................................................................................ 3-3
3-3 Little-Endian Mapping of Structure S..................................................................................... 3-3
3-4 Little-Endian Mapping of Structure S —Alternate View........................................................ 3-4
3-5 Modified Little-Endian Structure S as Seen by the Memory Subsystem................................ 3-5
3-6 Modified Little-Endian Structure S as Seen by the Processor ................................................3-6
3-7 True Little-Endian Mapping, Word Stored at Address 05 ......................................................3-6
3-8 Word at Little-Endian Address 05 as Seen by the Memory Subsystem .................................3-7
3-9 Floating-Point Single-Precision Format................................................................................ 3-11
3-10 Floating-Point Double-Precision Format.............................................................................. 3-11
Programming Environments Manual for 32-Bit Implementations of the PowerPC Architecture, Rev. 3
xviii Freescale Semiconductor
Figures
Figure
Number Title
Page
Number
3-11 Approximation to Real Numbers.......................................................................................... 3-13
3-12 Format for Normalized Numbers.......................................................................................... 3-14
3-13 Format for Zero Numbers .....................................................................................................3-14
3-14 Format for Denormalized Numbers...................................................................................... 3-15
3-15 Format for Positive and Negative Infinities.......................................................................... 3-15
3-16 Format for NaNs ................................................................................................................... 3-15
3-17 Representation of Generated QNaN ..................................................................................... 3-16
3-18 Single-Precision Representation in an FPR .......................................................................... 3-18
3-19 Relation of Z1 and Z2 ...........................................................................................................3-19
3-20 Selection of Z1 and Z2 for the Four Rounding Modes.........................................................3-20
3-21 Rounding Flags in FPSCR.................................................................................................... 3-21
3-22 Floating-Point Status and Control Register (FPSCR)...........................................................3-21
3-23 Initial Flow for Floating-Point Exception Conditions .......................................................... 3-28
3-24 Checking of Remaining Floating-Point Exception Conditions.............................................3-32
4-1 Register Indirect with Immediate Index Addressing for Integer Loads/Stores..................... 4-25
4-2 Register Indirect with Index Addressing for Integer Loads/Stores.......................................4-26
4-3 Register Indirect Addressing for Integer Loads/Stores.........................................................4-27
4-4 Register Indirect with Immediate Index Addressing for Floating-Point Loads/Stores......... 4-33
4-5 Register Indirect with Index Addressing for Floating-Point Loads/Stores........................... 4-34
4-6 Branch Relative Addressing.................................................................................................. 4-38
4-7 Branch Conditional Relative Addressing.............................................................................. 4-39
4-8 Branch to Absolute Addressing ............................................................................................ 4-40
4-9 Branch Conditional to Absolute Addressing ........................................................................ 4-40
4-10 Branch Conditional to Link Register Addressing................................................................. 4-41
4-11 Branch Conditional to Count Register Addressing...............................................................4-42
5-1 Memory Barrier when Coherency is Required (M = 1)........................................................ 5-11
5-2 Cumulative Memory Barrier................................................................................................. 5-12
6-1 Machine Status Save/Restore Register 0 (SRR0) ................................................................. 6-11
6-2 Machine Status Save/Restore Register 1 (SRR1) ................................................................. 6-11
6-3 Machine State Register (MSR) ............................................................................................. 6-12
7-1 MMU Conceptual Block Diagram.......................................................................................... 7-4
7-2 Address Translation Types......................................................................................................7-5
7-3 General Flow of Address Translation (Real Addressing Mode and Block) ........................... 7-9
7-4 General Flow of Page and Direct-Store Address Translation............................................... 7-10
7-5 MMU Registers..................................................................................................................... 7-14
7-6 BAT Array Organization.......................................................................................................7-17
7-7 BAT Array Hit/Miss Flow..................................................................................................... 7-19
7-8 Format of Upper BAT Register............................................................................................. 7-21
7-9 Format of Lower BAT Register ............................................................................................ 7-21
7-10 Memory Protection Violation Flow for Blocks..................................................................... 7-24
7-11 Block Physical Address Generation...................................................................................... 7-25
Programming Environments Manual for 32-Bit Implementations of the PowerPC Architecture, Rev. 3
Freescale Semiconductor xix
Figures
Figure
Number Title
Page
Number
7-12 Block Address Translation Flow........................................................................................... 7-26
7-13 Page Address Translation Overview..................................................................................... 7-28
7-14 Segment Register Format for Page Address Translation......................................................7-29
7-15 Page Table Entry Format.......................................................................................................7-30
7-16 Memory Protection Violation Flow for Pages ...................................................................... 7-36
7-17 Page Address Translation Flow—TLB Hit........................................................................... 7-37
7-18 Page Memory Protection Violation Conditions
for Page Address Translation ........................................................................................... 7-38
7-19 Page Table Definitions.......................................................................................................... 7-39
7-20 SDR1 Register Format..........................................................................................................7-40
7-21 Hashing Functions for Page Tables....................................................................................... 7-42
7-22 Generation of Addresses for Page Tables ............................................................................. 7-44
7-23 Example Page Table Structure .............................................................................................. 7-46
7-24 Example Primary PTEG Address Generation....................................................................... 7-48
7-25 Example Secondary PTEG Address Generation................................................................... 7-49
7-26 Page Table Search Flow........................................................................................................7-51
7-27 Segment Register Format for Direct-Store Segments...........................................................7-54
7-28 Direct-Store Segment Translation Flow................................................................................ 7-56
8-1 Instruction Description............................................................................................................8-7
C-1 IEEE 64-Bit Execution Model................................................................................................C-1
C-2 Multiply-Add 64-Bit Execution Model...................................................................................C-3
E-1 Branch Conditional (bc) Instruction Format...........................................................................E-4
E-2 BO Field (Bits 6–10 of the Instruction Encoding)..................................................................E-5
E-3 BI Field (Bits 11–14 of the Instruction Encoding)..................................................................E-8
Programming Environments Manual for 32-Bit Implementations of the PowerPC Architecture, Rev. 3
xx Freescale Semiconductor
Figures
Figure
Number Title
Page
Number
  • Page 1 1
  • Page 2 2
  • Page 3 3
  • Page 4 4
  • Page 5 5
  • Page 6 6
  • Page 7 7
  • Page 8 8
  • Page 9 9
  • Page 10 10
  • Page 11 11
  • Page 12 12
  • Page 13 13
  • Page 14 14
  • Page 15 15
  • Page 16 16
  • Page 17 17
  • Page 18 18
  • Page 19 19
  • Page 20 20
  • Page 21 21
  • Page 22 22
  • Page 23 23
  • Page 24 24
  • Page 25 25
  • Page 26 26
  • Page 27 27
  • Page 28 28
  • Page 29 29
  • Page 30 30
  • Page 31 31
  • Page 32 32
  • Page 33 33
  • Page 34 34
  • Page 35 35
  • Page 36 36
  • Page 37 37
  • Page 38 38
  • Page 39 39
  • Page 40 40
  • Page 41 41
  • Page 42 42
  • Page 43 43
  • Page 44 44
  • Page 45 45
  • Page 46 46
  • Page 47 47
  • Page 48 48
  • Page 49 49
  • Page 50 50
  • Page 51 51
  • Page 52 52
  • Page 53 53
  • Page 54 54
  • Page 55 55
  • Page 56 56
  • Page 57 57
  • Page 58 58
  • Page 59 59
  • Page 60 60
  • Page 61 61
  • Page 62 62
  • Page 63 63
  • Page 64 64
  • Page 65 65
  • Page 66 66
  • Page 67 67
  • Page 68 68
  • Page 69 69
  • Page 70 70
  • Page 71 71
  • Page 72 72
  • Page 73 73
  • Page 74 74
  • Page 75 75
  • Page 76 76
  • Page 77 77
  • Page 78 78
  • Page 79 79
  • Page 80 80
  • Page 81 81
  • Page 82 82
  • Page 83 83
  • Page 84 84
  • Page 85 85
  • Page 86 86
  • Page 87 87
  • Page 88 88
  • Page 89 89
  • Page 90 90
  • Page 91 91
  • Page 92 92
  • Page 93 93
  • Page 94 94
  • Page 95 95
  • Page 96 96
  • Page 97 97
  • Page 98 98
  • Page 99 99
  • Page 100 100
  • Page 101 101
  • Page 102 102
  • Page 103 103
  • Page 104 104
  • Page 105 105
  • Page 106 106
  • Page 107 107
  • Page 108 108
  • Page 109 109
  • Page 110 110
  • Page 111 111
  • Page 112 112
  • Page 113 113
  • Page 114 114
  • Page 115 115
  • Page 116 116
  • Page 117 117
  • Page 118 118
  • Page 119 119
  • Page 120 120
  • Page 121 121
  • Page 122 122
  • Page 123 123
  • Page 124 124
  • Page 125 125
  • Page 126 126
  • Page 127 127
  • Page 128 128
  • Page 129 129
  • Page 130 130
  • Page 131 131
  • Page 132 132
  • Page 133 133
  • Page 134 134
  • Page 135 135
  • Page 136 136
  • Page 137 137
  • Page 138 138
  • Page 139 139
  • Page 140 140
  • Page 141 141
  • Page 142 142
  • Page 143 143
  • Page 144 144
  • Page 145 145
  • Page 146 146
  • Page 147 147
  • Page 148 148
  • Page 149 149
  • Page 150 150
  • Page 151 151
  • Page 152 152
  • Page 153 153
  • Page 154 154
  • Page 155 155
  • Page 156 156
  • Page 157 157
  • Page 158 158
  • Page 159 159
  • Page 160 160
  • Page 161 161
  • Page 162 162
  • Page 163 163
  • Page 164 164
  • Page 165 165
  • Page 166 166
  • Page 167 167
  • Page 168 168
  • Page 169 169
  • Page 170 170
  • Page 171 171
  • Page 172 172
  • Page 173 173
  • Page 174 174
  • Page 175 175
  • Page 176 176
  • Page 177 177
  • Page 178 178
  • Page 179 179
  • Page 180 180
  • Page 181 181
  • Page 182 182
  • Page 183 183
  • Page 184 184
  • Page 185 185
  • Page 186 186
  • Page 187 187
  • Page 188 188
  • Page 189 189
  • Page 190 190
  • Page 191 191
  • Page 192 192
  • Page 193 193
  • Page 194 194
  • Page 195 195
  • Page 196 196
  • Page 197 197
  • Page 198 198
  • Page 199 199
  • Page 200 200
  • Page 201 201
  • Page 202 202
  • Page 203 203
  • Page 204 204
  • Page 205 205
  • Page 206 206
  • Page 207 207
  • Page 208 208
  • Page 209 209
  • Page 210 210
  • Page 211 211
  • Page 212 212
  • Page 213 213
  • Page 214 214
  • Page 215 215
  • Page 216 216
  • Page 217 217
  • Page 218 218
  • Page 219 219
  • Page 220 220
  • Page 221 221
  • Page 222 222
  • Page 223 223
  • Page 224 224
  • Page 225 225
  • Page 226 226
  • Page 227 227
  • Page 228 228
  • Page 229 229
  • Page 230 230
  • Page 231 231
  • Page 232 232
  • Page 233 233
  • Page 234 234
  • Page 235 235
  • Page 236 236
  • Page 237 237
  • Page 238 238
  • Page 239 239
  • Page 240 240
  • Page 241 241
  • Page 242 242
  • Page 243 243
  • Page 244 244
  • Page 245 245
  • Page 246 246
  • Page 247 247
  • Page 248 248
  • Page 249 249
  • Page 250 250
  • Page 251 251
  • Page 252 252
  • Page 253 253
  • Page 254 254
  • Page 255 255
  • Page 256 256
  • Page 257 257
  • Page 258 258
  • Page 259 259
  • Page 260 260
  • Page 261 261
  • Page 262 262
  • Page 263 263
  • Page 264 264
  • Page 265 265
  • Page 266 266
  • Page 267 267
  • Page 268 268
  • Page 269 269
  • Page 270 270
  • Page 271 271
  • Page 272 272
  • Page 273 273
  • Page 274 274
  • Page 275 275
  • Page 276 276
  • Page 277 277
  • Page 278 278
  • Page 279 279
  • Page 280 280
  • Page 281 281
  • Page 282 282
  • Page 283 283
  • Page 284 284
  • Page 285 285
  • Page 286 286
  • Page 287 287
  • Page 288 288
  • Page 289 289
  • Page 290 290
  • Page 291 291
  • Page 292 292
  • Page 293 293
  • Page 294 294
  • Page 295 295
  • Page 296 296
  • Page 297 297
  • Page 298 298
  • Page 299 299
  • Page 300 300
  • Page 301 301
  • Page 302 302
  • Page 303 303
  • Page 304 304
  • Page 305 305
  • Page 306 306
  • Page 307 307
  • Page 308 308
  • Page 309 309
  • Page 310 310
  • Page 311 311
  • Page 312 312
  • Page 313 313
  • Page 314 314
  • Page 315 315
  • Page 316 316
  • Page 317 317
  • Page 318 318
  • Page 319 319
  • Page 320 320
  • Page 321 321
  • Page 322 322
  • Page 323 323
  • Page 324 324
  • Page 325 325
  • Page 326 326
  • Page 327 327
  • Page 328 328
  • Page 329 329
  • Page 330 330
  • Page 331 331
  • Page 332 332
  • Page 333 333
  • Page 334 334
  • Page 335 335
  • Page 336 336
  • Page 337 337
  • Page 338 338
  • Page 339 339
  • Page 340 340
  • Page 341 341
  • Page 342 342
  • Page 343 343
  • Page 344 344
  • Page 345 345
  • Page 346 346
  • Page 347 347
  • Page 348 348
  • Page 349 349
  • Page 350 350
  • Page 351 351
  • Page 352 352
  • Page 353 353
  • Page 354 354
  • Page 355 355
  • Page 356 356
  • Page 357 357
  • Page 358 358
  • Page 359 359
  • Page 360 360
  • Page 361 361
  • Page 362 362
  • Page 363 363
  • Page 364 364
  • Page 365 365
  • Page 366 366
  • Page 367 367
  • Page 368 368
  • Page 369 369
  • Page 370 370
  • Page 371 371
  • Page 372 372
  • Page 373 373
  • Page 374 374
  • Page 375 375
  • Page 376 376
  • Page 377 377
  • Page 378 378
  • Page 379 379
  • Page 380 380
  • Page 381 381
  • Page 382 382
  • Page 383 383
  • Page 384 384
  • Page 385 385
  • Page 386 386
  • Page 387 387
  • Page 388 388
  • Page 389 389
  • Page 390 390
  • Page 391 391
  • Page 392 392
  • Page 393 393
  • Page 394 394
  • Page 395 395
  • Page 396 396
  • Page 397 397
  • Page 398 398
  • Page 399 399
  • Page 400 400
  • Page 401 401
  • Page 402 402
  • Page 403 403
  • Page 404 404
  • Page 405 405
  • Page 406 406
  • Page 407 407
  • Page 408 408
  • Page 409 409
  • Page 410 410
  • Page 411 411
  • Page 412 412
  • Page 413 413
  • Page 414 414
  • Page 415 415
  • Page 416 416
  • Page 417 417
  • Page 418 418
  • Page 419 419
  • Page 420 420
  • Page 421 421
  • Page 422 422
  • Page 423 423
  • Page 424 424
  • Page 425 425
  • Page 426 426
  • Page 427 427
  • Page 428 428
  • Page 429 429
  • Page 430 430
  • Page 431 431
  • Page 432 432
  • Page 433 433
  • Page 434 434
  • Page 435 435
  • Page 436 436
  • Page 437 437
  • Page 438 438
  • Page 439 439
  • Page 440 440
  • Page 441 441
  • Page 442 442
  • Page 443 443
  • Page 444 444
  • Page 445 445
  • Page 446 446
  • Page 447 447
  • Page 448 448
  • Page 449 449
  • Page 450 450
  • Page 451 451
  • Page 452 452
  • Page 453 453
  • Page 454 454
  • Page 455 455
  • Page 456 456
  • Page 457 457
  • Page 458 458
  • Page 459 459
  • Page 460 460
  • Page 461 461
  • Page 462 462
  • Page 463 463
  • Page 464 464
  • Page 465 465
  • Page 466 466
  • Page 467 467
  • Page 468 468
  • Page 469 469
  • Page 470 470
  • Page 471 471
  • Page 472 472
  • Page 473 473
  • Page 474 474
  • Page 475 475
  • Page 476 476
  • Page 477 477
  • Page 478 478
  • Page 479 479
  • Page 480 480
  • Page 481 481
  • Page 482 482
  • Page 483 483
  • Page 484 484
  • Page 485 485
  • Page 486 486
  • Page 487 487
  • Page 488 488
  • Page 489 489
  • Page 490 490
  • Page 491 491
  • Page 492 492
  • Page 493 493
  • Page 494 494
  • Page 495 495
  • Page 496 496
  • Page 497 497
  • Page 498 498
  • Page 499 499
  • Page 500 500
  • Page 501 501
  • Page 502 502
  • Page 503 503
  • Page 504 504
  • Page 505 505
  • Page 506 506
  • Page 507 507
  • Page 508 508
  • Page 509 509
  • Page 510 510
  • Page 511 511
  • Page 512 512
  • Page 513 513
  • Page 514 514
  • Page 515 515
  • Page 516 516
  • Page 517 517
  • Page 518 518
  • Page 519 519
  • Page 520 520
  • Page 521 521
  • Page 522 522
  • Page 523 523
  • Page 524 524
  • Page 525 525
  • Page 526 526
  • Page 527 527
  • Page 528 528
  • Page 529 529
  • Page 530 530
  • Page 531 531
  • Page 532 532
  • Page 533 533
  • Page 534 534
  • Page 535 535
  • Page 536 536
  • Page 537 537
  • Page 538 538
  • Page 539 539
  • Page 540 540
  • Page 541 541
  • Page 542 542
  • Page 543 543
  • Page 544 544
  • Page 545 545
  • Page 546 546
  • Page 547 547
  • Page 548 548
  • Page 549 549
  • Page 550 550
  • Page 551 551
  • Page 552 552
  • Page 553 553
  • Page 554 554
  • Page 555 555
  • Page 556 556
  • Page 557 557
  • Page 558 558
  • Page 559 559
  • Page 560 560
  • Page 561 561
  • Page 562 562
  • Page 563 563
  • Page 564 564
  • Page 565 565
  • Page 566 566
  • Page 567 567
  • Page 568 568
  • Page 569 569
  • Page 570 570
  • Page 571 571
  • Page 572 572
  • Page 573 573
  • Page 574 574
  • Page 575 575
  • Page 576 576
  • Page 577 577
  • Page 578 578
  • Page 579 579
  • Page 580 580
  • Page 581 581
  • Page 582 582
  • Page 583 583
  • Page 584 584
  • Page 585 585
  • Page 586 586
  • Page 587 587
  • Page 588 588
  • Page 589 589
  • Page 590 590
  • Page 591 591
  • Page 592 592
  • Page 593 593
  • Page 594 594
  • Page 595 595
  • Page 596 596
  • Page 597 597
  • Page 598 598
  • Page 599 599
  • Page 600 600
  • Page 601 601
  • Page 602 602
  • Page 603 603
  • Page 604 604
  • Page 605 605
  • Page 606 606
  • Page 607 607
  • Page 608 608
  • Page 609 609
  • Page 610 610
  • Page 611 611
  • Page 612 612
  • Page 613 613
  • Page 614 614
  • Page 615 615
  • Page 616 616
  • Page 617 617
  • Page 618 618
  • Page 619 619
  • Page 620 620
  • Page 621 621
  • Page 622 622
  • Page 623 623
  • Page 624 624
  • Page 625 625
  • Page 626 626
  • Page 627 627
  • Page 628 628
  • Page 629 629
  • Page 630 630
  • Page 631 631
  • Page 632 632
  • Page 633 633
  • Page 634 634
  • Page 635 635
  • Page 636 636
  • Page 637 637
  • Page 638 638
  • Page 639 639
  • Page 640 640

NXP MPC8245 Reference guide

Type
Reference guide

Ask a question and I''ll find the answer in the document

Finding information in a document is now easier with AI