NXP LPC2377FBD144 User guide

Category
Video converters
Type
User guide
UM10211
LPC23XX User manual
Rev. 4.1 — 5 September 2012 User manual
Document information
Info Content
Keywords LPC2300, LPC2361, LPC2362, LPC2364, LPC2365, LPC2366, LPC2367,
LPC2368, LPC2377, LPC2378, LPC2387, LPC2388, ARM, ARM7, 32-bit,
USB, Ethernet, CAN, I2S, Microcontroller
Abstract LPC23XX User manual revision
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LPC23XX User manual
Revision history
Rev Date Description
4.1 20120905 LPC23XX User manual
Modifications:
Corrected cross references throughout.
4 20120726 LPC23XX User manual
Modifications:
Updated numbering for CAN interfaces: CAN1 uses SCC = 0, CAN2 uses SCC = 1.
See Section 12.14 “ID look-up table RAM” and Section 12.16 “Configuration and search
algorithm”.
Registers CANWAKEFLAGS and CANSLEEPCLR added. See Table 220 “CAN Wake
and Sleep registers”.
CCR register bit description updated. See Table 505 “Clock Control Register (CCR -
address 0xE002 4008) bit description”.
Flash erase time corrected in Section 1.3 “Features”.
Reset value of the SCS register changed to 0x8 in Table 31.
Write restriction for RTC register appended in Section 26.8 “RTC usage notes”.
ADC self-test pin set-up removed. See Table 520 “A/D pin description”.
Update RTC usage notes: Do not ground VBAT. See Table 501 and Section 26.8.
Description of Ethernet initialization updated in Section 11.9.
Glitch filter constant for EINTx pins changed to 10 ns in Table 97 to Table 100.
Editorial updates.
3 20090825 LPC23XX User manual
Modifications:
Deep power-down mode functionality added (see Section 4–8 “Power control” and
Section 26–26.7 “RTC Usage Notes”).
Register containing device revision added (implemented starting with revision D, see
Section 29–7.11).
Part id for part LPC2387 updated (Table 29–542).
XTAL1 input selection and PCB layout guidelines added (see Section 4–4.2).
Editorial updates throughout the user manual.
LPC2361 flash sectors added in Table 29–526.
ISP1301 replaced by ISP1302 in Section 15–7.
Fractional baud rate generator disabled in UART0/1/2/3 auto baud mode.
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Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
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LPC23XX User manual
2 20090211 LPC23XX User manual
Modifications:
Parts LPC2361 and LPC2362 added.
Numerous editorial updates.
AHB configuration registers AHBCFG1 and AHBCFG2 added.
UARTs: minimum setting for DLL value updated.
1 20080311 LPC2364/65/66/67/68/77/78/87/88 User manual
Revision history
…continued
Rev Date Description
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1.1 Introduction
LPC23xx series are ARM-based microcontrollers for applications requiring serial
communications for a variety of purposes. These microcontrollers typically incorporate a
10/100 Ethernet MAC, USB 2.0 Full Speed interface, four UARTs, two CAN channels, an
SPI interface, two Synchronous Serial Ports (SSP), three I2C interfaces, an I
2
S interface,
and a MiniBus (8-bit data/16-bit address parallel bus).
1.2 How to read this manual
The term “LPC23xx“ in the following text will be used as a generic name for all parts
covered in this user manual:
LPC2361/62
LPC2364/65/66/67/68
LPC2377/78
LPC2387
LPC2388
Only when needed, a specific device name will be used to distinguish the part. See
Table 1
to find information about a particular part.
1.3 Features
1.3.1 General features
ARM7TDMI-S processor, running at up to 72 MHz.
Up to 512 kB on-chip Flash Program Memory with In-System Programming (ISP) and
In-Application Programming (IAP) capabilities. Single Flash sector or full-chip erase in
100 ms. Flash program memory is on the ARM local bus for high performance CPU
access.
Up to 64 kB of SRAM on the ARM local bus for high performance CPU access.
UM10211
Chapter 1: LPC23xx Introductory information
Rev. 4.1 — 5 September 2012 User manual
Table 1. LPC23xx overview
Part Features Ordering info Ordering options Block diagram
LPC2361/62 Section 1.3.1
,
Section 1.3.2
Table 3 Table 4 Figure 1
LPC2364/65/66/67/68 Section 1.3.1 Table 3 Table 5 Figure 2
LPC2377/78 Section 1.3.1,
Section 1.3.3
Table 3 Table 6 Figure 3
LPC2387 Section 1.3.1,
Section 1.3.4
Table 3 Table 7 Figure 4
LPC2388 Section 1.3.1,
Section 1.3.4
Table 3 Table 8 Figure 5
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Chapter 1: LPC23xx Introductory information
16 kB Static RAM for Ethernet interface. Can also be used as general purpose SRAM.
8 kB Static RAM for general purpose or USB interface.
Dual AHB system that provides for simultaneous Ethernet DMA, USB DMA, and
program execution from on-chip flash with no contention between those functions. A
bus bridge allows the Ethernet DMA to access the other AHB subsystem.
Advanced Vectored Interrupt Controller, supporting up to 32 vectored interrupts.
General Purpose DMA controller (GPDMA) on AHB that can be used with the SSP
serial interfaces, the I
2
S port, and the SD/MMC card port, as well as for
memory-to-memory transfers.
Serial Interfaces:
Ethernet MAC with associated DMA controller. These functions reside on an
independent AHB bus.
On LPC2364/66/68, LPC2378, LPC2387, LPC2388: USB 2.0 device controller
with on-chip PHY and associated DMA controller.
On LPC2388: USB Host/OTG controller.
Four UARTs with fractional baud rate generation, one with modem control I/O, one
with IrDA support, all with FIFO. These reside on the APB bus.
SPI controller, residing on the APB bus.
Two SSP controllers with FIFO and multi-protocol capabilities. One is an alternate
for the SPI port, sharing its interrupt. The SSP controllers can be used with the
GPDMA controller and reside on the APB bus.
Three I
2
C interfaces reside on the APB bus. The second and third I
2
C interfaces
are expansion I
2
C interfaces with standard port pins rather than special open-drain
I
2
C pins.
I
2
S (Inter-IC Sound) interface for digital audio input or output, residing on the APB
bus. The I
2
S interface can be used with the GPDMA.
On LPC2364/66/68, LPC2378, LPC2387, LPC2388: Two CAN channels with
Acceptance Filter/FullCAN mode residing on the APB bus.
Other APB Peripherals:
On LPC2367/68, LPC2377/78, LPC2387, LPC2388: Secure Digital (SD) /
MultiMediaCard (MMC) memory card interface.
Up to 70 (100 pin packages) or 104 (144 pin packages) general purpose I/O pins.
10 bit A/D converter with input multiplexing among 6 pins (100 pin packages) or 8
pins (144 pin packages).
10 bit D/A converter.
Four general purpose timers with two capture inputs each and up to four compare
output pins each. Each timer block has an external count input.
One PWM/Timer block with support for three-phase motor control. The PWM has
two external count inputs.
Real-Time Clock (RTC) with separate power pin; clock source can be the RTC
oscillator or the APB clock.
2 kB Static RAM powered from the RTC power pin, allowing data to be stored
when the rest of the chip is powered off.
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Chapter 1: LPC23xx Introductory information
Watchdog Timer. The watchdog timer can be clocked from the internal RC
oscillator, the RTC oscillator, or the APB clock.
Standard ARM Test/Debug interface for compatibility with existing tools.
Emulation Trace Module.
Support for real-time trace.
Single 3.3 V power supply (3.0 V to 3.6 V).
Four reduced power modes: Idle, Sleep, Power-down, and Deep power-down modes.
Four external interrupt inputs. In addition every PORT0/2 pin can be configured as an
edge sensing interrupt.
Processor wake-up from Power-down mode via any interrupt able to operate during
Power-down mode (includes external interrupts, RTC interrupt, and Ethernet walk-up
interrupt).
Two independent power domains allow fine tuning of power consumption based on
needed features.
Brownout detect with separate thresholds for interrupt and forced reset.
On-chip Power On Reset (POR).
On-chip crystal oscillator with an operating range of 1 MHz to 24 MHz.
4 MHz internal RC oscillator that can optionally be used as the system clock. For USB
and CAN application, the use of an external clock source is suggested.
On-chip PLL allows CPU operation up to the maximum CPU rate without the need for
a high-frequency crystal. May be run from the main oscillator, the internal RC
oscillator, or the RTC oscillator.
Boundary scan for simplified board testing is available in LPC2364FET100,
LPC2368FET100 (TFBGA packages), LPC2377/78, and LPC2388.
Versatile pin function selections allow more possibilities for using on-chip peripheral
functions.
1.3.2 Features available on LPC2361/62
Device/Host/OTG controller available.
No Ethernet on LPC2361.
1.3.3 Features available in LPC2377/78 and LPC2388
External memory controller that supports static devices such as Flash and SRAM. An 8-bit
data/16-bit address parallel bus is available.
1.3.4 Features available in LPC2387 and LPC2388
64 kB of SRAM on the ARM local bus for high performance CPU access.
16 kB Static RAM for USB interface. Can also be used as general purpose SRAM.
1.3.5 Overview
The following table shows the differences between LPC23xx parts. Features that are the
same for all parts are not included.
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Chapter 1: LPC23xx Introductory information
1.4 Applications
Industrial control
Medical systems
1.5 Ordering information and options
For ordering information for all LPC23xx parts, see Table 3. For ordering options, see
Table 4 for LPC2361/62 parts.
Table 5 for LPC2364/65/66/67/68 parts.
Table 6 for LPC2377/78.
Table 7 for LPC2387.
Table 8 for LPC2388.
Table 2. LPC23xx features overview
Part Local
bus
SRAM
(kB)
Flash
(kB)
EMC USB/
GP
SRAM
(kB)
USB
device
USB
host/
OTG
Ethernet Ethernet
GP
SRAM
(kB)
CAN
channels
SD/
MMC
ADC
channels
GPIO
pins
LPC2361 8 64 no 8 yes yes no 16 2 no 6 70
LPC2362 32 128 no 8 yes yes yes 16 2 no 6 70
LPC2364 8 128 no 8 yes no yes 16 2 no 6 70
LPC2365 32 256 no 8 no no yes 16 - no 6 70
LPC2366 32 256 no 8 yes no yes 16 2 no 6 70
LPC2367 32 512 no 8 no no yes 16 - yes 6 70
LPC2368 32 512 no 8 yes no yes 16 2 yes 6 70
LPC2377 32 512 Mini 8 no no yes 16 - yes 8 104
LPC2378 32 512 Mini 8 yes no yes 16 2 yes 8 104
LPC2387 64 512 no 16 yes yes yes 16 2 yes 6 70
LPC2388 64 512 Mini 16 yes yes yes 16 2 yes 8 104
Table 3. LPC23xx ordering information
Type number Package
Name Description Version
LPC2361FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 14 1.4 mm SOT407-1
LPC2362FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 14 1.4 mm SOT407-1
LPC2364FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 14 1.4 mm SOT407-1
LPC2364FET100 TFBGA100 plastic thin fine-pitch ball grid array package; 100 balls; body 9 9 0.7 mm SOT926-1
LPC2365FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 14 1.4 mm SOT407-1
LPC2366FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 14 1.4 mm SOT407-1
LPC2367FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 14 1.4 mm SOT407-1
LPC2368FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 14 1.4 mm SOT407-1
LPC2368FET100 TFBGA100 plastic thin fine-pitch ball grid array package; 100 balls; body 9 9 0.7 mm SOT926-1
LPC2377FBD144 LQFP144 plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm SOT486-1
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Chapter 1: LPC23xx Introductory information
[1] Available as general purpose SRAM for the LPC2361.
LPC2378FBD144 LQFP144 plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm SOT486-1
LPC2387FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 14 1.4 mm SOT407-1
LPC2388FBD144 LQFP144 plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm SOT486-1
Table 3. LPC23xx ordering information
…continued
Type number Package
Name Description Version
Table 4. LPC2361/62 Ordering options
Type number Flash
(kB)
SRAM (kB) Ethernet USB
device +
4kB
FIFO
GP
DMA
Channels Temp range
Local bus
Ethernet buffer
GP/USB
RTC
Total
CAN ADC DAC
LPC2361FBD100 64 8 16
[1]
8234- yes yes 2 6 1 40 C to +85 C
LPC2362FBD100 128 32 16 8 2 58 RMII yes yes 2 6 1 40 C to +85 C
Table 5. LPC2364/65/66/67/68 Ordering options
Type number Flash
(kB)
SRAM (kB) Ether
net
USB
device
+ 4 kB
FIFO
SD/
MMC
GP
DMA
Channels Temp
range
Local
bus
Ethernet
buffers
GP/
USB
RTC Total CAN ADC DAC
LPC2364FBD100 128 8 16 8 2 34 RMII yes no yes 2 6 1 40 C
to
+85 C
LPC2364FET100 128 8 16 8 2 34 RMII yes no yes 2 6 1 40 C
to
+85 C
LPC2365FBD100 256 32 16 8 2 58 RMII no no yes - 6 1 40 C
to
+85 C
LPC2366FBD100 256 32 16 8 2 58 RMII yes no yes 2 6 1 40 C
to
+85 C
LPC2367FBD100 512 32 16 8 2 58 RMII no yes yes - 6 1 40 C
to
+85 C
LPC2368FBD100 512 32 16 8 2 58 RMII yes yes yes 2 6 1 40 C
to
+85 C
LPC2368FET100 512 32 16 8 2 58 RMII yes yes yes 2 6 1 40 C
to
+85 C
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Chapter 1: LPC23xx Introductory information
1.6 Architectural overview
The LPC2300 consists of an ARM7TDMI-S CPU with emulation support, the ARM7 Local
Bus for closely coupled, high speed access to the majority of on-chip memory, the AMBA
Advanced High-performance Bus (AHB) interfacing to high speed on-chip peripherals and
external memory, and the AMBA Advanced Peripheral Bus (APB) for connection to other
on-chip peripheral functions. The microcontroller permanently configures the
ARM7TDMI-S processor for little-endian byte order.
The microcontroller implements two AHB buses in order to allow the Ethernet block to
operate without interference caused by other system activity. The primary AHB, referred
to as AHB1, includes the Vectored Interrupt Controller, General Purpose DMA Controller,
External Memory Controller, USB interface, and 8/16 kB SRAM primarily intended for use
by the USB.
Table 6. LPC2377/78 ordering options
Type number Flash
(kB)
SRAM (kB) External bus Ether
net
USB
device
+ 4 kB
FIFO
CAN channels
SD/
MMC
GP
DMA
ADC channels
DAC channels
Temp
range
Local bus
Ethernet buffer
GP/USB
RTC
Total
LPC2377FBD144 512 32 16 8 2 58 MiniBus: 8 data, 16
address, and 2 chip
select lines
RMII no - yes yes 8 1 40 C to
+85 C
LPC2378FBD144 512 32 16 8 2 58 MiniBus: 8 data, 16
address, and 2 chip
select lines
RMII yes 2 yes yes 8 1 40 C to
+85 C
Table 7. LPC2387 ordering options
Type number Flash
(kB)
SRAM (kB) Ether
net
USB
device
OTG
host +
4kB
FIFO
SD/
MMC
GP
DMA
Channels Temp
range
Local
bus
Ethernet
buffers
GP/
USB
RTC Total CAN ADC DAC
LPC2387FBD100 512 64 16 16 2 98 RMII yes yes yes 2 6 1 40 C
to
+85 C
Table 8. LPC2388 ordering options
Type number Flash
(kB)
SRAM (kB) External bus Ether
net
USB
device
host
OTG+
4kB
FIFO
CAN channels
SD/
MMC
GP
DMA
ADC channels
DAC channels
Temp
range
Local bus
Ethernet buffer
GP/USB
RTC
Total
LPC2388FBD144 512 64 16 16 2 98 MiniBus: 8 data, 16
address, and 2 chip
select lines
RMII yes 2 yes yes 8 1 40 C to
+85 C
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Chapter 1: LPC23xx Introductory information
The second AHB, referred to as AHB2, includes only the Ethernet block and an
associated 16 kB SRAM. In addition, a bus bridge is provided that allows the secondary
AHB to be a bus master on AHB1, allowing expansion of Ethernet buffer space into
off-chip memory or unused space in memory residing on AHB1.
In summary, bus masters with access to AHB1 are the ARM7 itself, the USB block, the
General Purpose DMA function, and the Ethernet block (via the bus bridge from AHB2).
Bus masters with access to AHB2 are the ARM7 and the Ethernet block.
AHB peripherals are allocated a 2 MB range of addresses at the very top of the 4 GB
ARM memory space. Each AHB peripheral is allocated a 16 kB address space within the
AHB address space. Lower speed peripheral functions are connected to the APB bus.
The AHB to APB bridge interfaces the APB bus to the AHB bus. APB peripherals are also
allocated a 2 MB range of addresses, beginning at the 3.5 GB address point. Each APB
peripheral is allocated a 16 kB address space within the APB address space.
1.7 ARM7TDMI-S processor
The ARM7TDMI-S is a general purpose 32 bit microprocessor, which offers high
performance and very low power consumption. The ARM architecture is based on
Reduced Instruction Set Computer (RISC) principles, and the instruction set and related
decode mechanism are much simpler than those of microprogrammed Complex
Instruction Set Computers. This simplicity results in a high instruction throughput and
impressive real-time interrupt response from a small and cost-effective processor core.
Pipeline techniques are employed so that all parts of the processing and memory systems
can operate continuously. Typically, while one instruction is being executed, its successor
is being decoded, and a third instruction is being fetched from memory.
The ARM7TDMI-S processor also employs a unique architectural strategy known as
THUMB, which makes it ideally suited to high-volume applications with memory
restrictions, or applications where code density is an issue.
The key idea behind THUMB is that of a super-reduced instruction set. Essentially, the
ARM7TDMI-S processor has two instruction sets:
The standard 32 bit ARM instruction set.
A 16 bit THUMB instruction set.
The THUMB set’s 16 bit instruction length allows it to approach twice the density of
standard ARM code while retaining most of the ARM’s performance advantage over a
traditional 16 bit processor using 16 bit registers. This is possible because THUMB code
operates on the same 32 bit register set as ARM code.
THUMB code is able to provide up to 65% of the code size of ARM, and 160% of the
performance of an equivalent ARM processor connected to a 16 bit memory system.
The ARM7TDMI-S processor is described in detail in the ARM7TDMI-S Data sheet that
can be found on official ARM web site.
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Chapter 1: LPC23xx Introductory information
1.8 On-chip flash memory system
The LPC2300 includes a Flash memory system with up to 512 kB. This memory may be
used for both code and data storage. Programming of the Flash memory may be
accomplished in several ways. It may be programmed In System via the serial port. The
application program may also erase and/or program the Flash while the application is
running, allowing a great degree of flexibility for data storage field firmware upgrades, etc.
The Flash is 128 bits wide and includes pre-fetching and buffering techniques to allow it to
operate at SRAM speeds.
1.9 On-chip Static RAM
The LPC2300 includes a static RAM memory up to 64 kB in size, that may be used for
code and/or data storage.
The SRAM controller incorporates a write-back buffer in order to prevent CPU stalls
during back-to-back writes. The write-back buffer always holds the last data sent by
software to the SRAM. The data is only written to the SRAM when software does another
write. After a "warm" chip reset, the SRAM does not reflect the last write operation. Two
identical writes to a location guarantee that the data will be present after a Reset.
Alternatively, a dummy write operation before entering idle or power-down mode will
similarly guarantee that the last data written will be present after a subsequent Reset.
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Chapter 1: LPC23xx Introductory information
1.10 Block diagram
(1) LPC2362 only.
Fig 1. LPC2361/62 block diagram
PWM1
ARM7TDMI-S
PLL
EINT3 to EINT0
FLASH
P3, P4
P0, P1, P2,
LEGACY GPI/O
52 PINS TOTAL
P0, P1
SCK, SCK0
MOSI, MOSI0
SSEL, SSEL0
SCK1
MOSI1
MISO1
SSEL1
SCL0, SCL1, SCL2
I2SRX_CLK
I2STX_CLK
I2SRX_WS
I2STX_WS
6 × AD0
RTCX1
RTCX2
RXD0, RXD2, RXD3
TXD1
RXD1
RD1, RD2
TD1, TD2
CAN1, CAN2
USB port 1
XTAL1
TCK TDO
EXTIN0
XTAL2
RESET
TRST
TDITMS
HIGH-SPEED
GPI/O
70 PINS
TOTAL
LPC2361/62
8/32 kB
SRAM
64/128 kB
FLASH
INTERNAL
CONTROLLERS
TEST/DEBUG
INTERFACE
EMULATION
TRACE MODULE
trace signals
AHB
BRIDGE
AHB
BRIDGE
ETHERNET
MAC WITH
DMA
(1)
16 kB
SRAM
MASTER
PORT
AHB TO
AHB BRIDGE
SLAVE
PORT
system
clock
SYSTEM
FUNCTIONS
INTERNAL RC
OSCILLATOR
V
DDA
V
DD(3V3)
VREF
V
SSA
, V
SS
VECTORED
INTERRUPT
CONTROLLER
8 kB
SRAM
USB WITH
4 kB RAM
AND DMA
GP DMA
CONTROLLER
I
2
S INTERFACE
SPI, SSP0 INTERFACE
I2SRX_SDA
I2STX_SDA
MISO, MISO0
SSP1 INTERFACE
TXD0, TXD2, TXD3
UART0, UART2, UART3
UART1
DTR1, RTS1
DSR1, CTS1, DCD1,
RI1
I
2
C0, I
2
C1, I
2
C2
SDA0, SDA1, SDA2
EXTERNAL INTERRUPTS
CAPTURE/COMPARE
TIMER0/TIMER1/
TIMER2/TIMER3
A/D CONVERTER
D/A CONVERTER
2 kB BATTERY RAM
RTC
OSCILLATOR
REAL-
TIME
CLOCK
WATCHDOG TIMER
SYSTEM CONTROL
2 × CAP0/CAP1/
CAP2/CAP3
4 × MAT2,
2 × MAT0/MAT1/
MAT3
6 × PWM1
2 × PCAP1
AOUT
VBAT
AHB TO
APB BRIDGE
SRAM
RMII(8)
V
BUS
002aad964
P0, P2
power domain 2
AHB2
AHB1
power domain 2
V
DD(DCDC)(3V3)
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Chapter 1: LPC23xx Introductory information
(1) LPC2367/68 only.
(2) LPC2364/66/68 only.
Fig 2. LPC2364/65/66/67/68 block diagram
PWM1
ARM7TDMI-S
PLL
EINT3 to EINT0
FLASH
P3, P4
P0, P1, P2,
LEGACY GPI/O
52 PINS TOTAL
P0, P1
SCK, SCK0
MOSI, MOSI0
SSEL, SSEL0
SCK1
MOSI1
MISO1
SSEL1
SCL0, SCL1, SCL2
I2SRX_CLK
I2STX_CLK
I2SRX_WS
I2STX_WS
6 × AD0
RTCX1
RTCX2
MCICLK, MCIPWR
RXD0, RXD2, RXD3
TXD1
RXD1
RD1, RD2
TD1, TD2
CAN1, CAN2
(2)
USB_D+, USB_D
XTAL1
TCK TDO
EXTIN0
XTAL2
RESET
TRST
TDITMS
HIGH-SPEED
GPI/O
70 PINS
TOTAL
LPC2364/65/66/67/68
8/32 kB
SRAM
128/256/
512 kB
FLASH
INTERNAL
CONTROLLERS
TEST/DEBUG
INTERFACE
EMULATION
TRACE MODULE
trace signals
AHB
BRIDGE
AHB
BRIDGE
ETHERNET
MAC WITH
DMA
16 kB
SRAM
MASTER
PORT
AHB TO
AHB BRIDGE
SLAVE
PORT
system
clock
SYSTEM
FUNCTIONS
INTERNAL RC
OSCILLATOR
V
DDA
V
DD(3V3)
VREF
V
SSA
, V
SS
VECTORED
INTERRUPT
CONTROLLER
8 kB
SRAM
USB WITH
4 kB RAM
AND DMA
(2)
GP DMA
CONTROLLER
I
2
S INTERFACE
SPI, SSP0 INTERFACE
I2SRX_SDA
I2STX_SDA
MISO, MISO0
SSP1 INTERFACE
SD/MMC CARD
INTERFACE
(1)
MCICMD,
MCIDAT[3:0]
TXD0, TXD2, TXD3
UART0, UART2, UART3
UART1
DTR1, RTS1
DSR1, CTS1, DCD1,
RI1
I
2
C0, I
2
C1, I
2
C2
SDA0, SDA1, SDA2
EXTERNAL INTERRUPTS
CAPTURE/COMPARE
TIMER0/TIMER1/
TIMER2/TIMER3
A/D CONVERTER
D/A CONVERTER
2 kB BATTERY RAM
RTC
OSCILLATOR
REAL-
TIME
CLOCK
WATCHDOG TIMER
SYSTEM CONTROL
2 × CAP0/CAP1/
CAP2/CAP3
4 × MAT2,
2 × MAT0/MAT1/
MAT3
6 × PWM1
2 × PCAP1
AOUT
VBAT
AHB TO
APB BRIDGE
SRAM
RMII(8)
V
BUS
USB_CONNECT
USB_UP_LED
002aac566
P0, P2
power domain 2
AHB2
AHB1
power domain 2
V
DD(DCDC)(3V3)
UM10211 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
User manual Rev. 4.1 — 5 September 2012 13 of 708
NXP Semiconductors
UM10211
Chapter 1: LPC23xx Introductory information
(1) LPC2378 only.
Fig 3. LPC2377/78 block diagram
power domain 2
LPC2377/78
A[15:0]
D[7:0]
EXTERNAL
MEMORY
CONTROLLER
ALARM
002aac574
PWM1
ARM7TDMI-S
PLL
EINT3 to EINT0
FLASH
P3, P4
P0, P1, P2,
LEGACY GPI/O
56 PINS TOTAL
P0, P1
SCK, SCK0
MOSI, MOSI0
SSEL, SSEL0
SCK1
MOSI1
MISO1
SSEL1
SCL0, SCL1, SCL2
I2SRX_CLK
I2STX_CLK
I2SRX_WS
I2STX_WS
8 × AD0
RTCX1
RTCX2
MCICLK, MCIPWR
RXD0, RXD2, RXD3
TXD1
RXD1
RD1, RD2
TD1, TD2
CAN1, CAN2
(1)
2 × USB_D+/USB_D
XTAL1
TCK TDO
EXTIN0
XTAL2
TRST
TDITMS
HIGH-SPEED
GPI/O
104 PINS
TOTAL
32 kB
SRAM
512 kB
FLASH
INTERNAL
CONTROLLERS
TEST/DEBUG
INTERFACE
EMULATION
TRACE MODULE
trace signals
AHB
BRIDGE
AHB
BRIDGE
ETHERNET
MAC WITH
DMA
16 kB
SRAM
MASTER
PORT
AHB TO
AHB BRIDGE
SLAVE
PORT
system
clock
SYSTEM
FUNCTIONS
INTERNAL RC
OSCILLATOR
V
DDA
V
DD(3V3)
V
DD(DCDC)(3V3)
VREF
V
SSA
, V
SS
VECTORED
INTERRUPT
CONTROLLER
8 kB
SRAM
USB WITH
4 kB RAM
AND DMA
(1)
GP DMA
CONTROLLER
I
2
S INTERFACE
SPI, SSP0 INTERFACE
I2SRX_SDA
I2STX_SDA
MISO, MISO0
SSP1 INTERFACE
SD/MMC CARD
INTERFACE
MCICMD,
MCIDAT[3:0]
TXD0, TXD2, TXD3
UART0, UART2, UART3
UART1
DTR1, RTS1
DSR1, CTS1, DCD1,
RI1
I
2
C0, I
2
C1, I
2
C2
SDA0, SDA1, SDA2
EXTERNAL INTERRUPTS
CAPTURE/COMPARE
TIMER0/TIMER1/
TIMER2/TIMER3
A/D CONVERTER
D/A CONVERTER
2 kB BATTERY RAM
RTC
OSCILLATOR
REAL-
TIME
CLOCK
WATCHDOG TIMER
SYSTEM CONTROL
2 × CAP0/CAP1/
CAP2/CAP3
4 × MAT2,
2 × MAT0/MAT1/
MAT3
6 × PWM1
2 × PCAP1
AOUT
VBAT
AHB TO
APB BRIDGE
SRAM
RMII(8)
RESET
V
BUS
2 × USB_CONNECT
2 × USB_UP_LED
DBGEN
P0, P2
AHB2 AHB1
OE, CS0, CS1,
BLS0
UM10211 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
User manual Rev. 4.1 — 5 September 2012 14 of 708
NXP Semiconductors
UM10211
Chapter 1: LPC23xx Introductory information
Fig 4. LPC2387 block diagram
PWM1
ARM7TDMI-S
PLL
EINT3 to EINT0
FLASH
P3, P4
P0, P1, P2,
LEGACY GPI/O
52 PINS TOTAL
P0, P1
SCK, SCK0
MOSI, MOSI0
SSEL, SSEL0
SCK1
MOSI1
MISO1
SSEL1
SCL0, SCL1, SCL2
I2SRX_CLK
I2STX_CLK
I2SRX_WS
I2STX_WS
6 × AD0
RTCX1
RTCX2
MCICLK, MCIPWR
RXD0, RXD2, RXD3
TXD1
RXD1
RD1, RD2
TD1, TD2
CAN1, CAN2
USB port 1
XTAL1
TCK TDO
EXTIN0
XTAL2
RESET
TRST
TDITMS
HIGH-SPEED
GPIO
70 PINS
TOTAL
LPC2387
64 kB
SRAM
512 kB
FLASH
INTERNAL
CONTROLLERS
TEST/DEBUG
INTERFACE
EMULATION
TRACE MODULE
trace signals
AHB
BRIDGE
AHB
BRIDGE
ETHERNET
MAC WITH
DMA
16 kB
SRAM
MASTER
PORT
AHB TO
AHB BRIDGE
SLAVE
PORT
system
clock
SYSTEM
FUNCTIONS
INTERNAL RC
OSCILLATOR
V
DDA
V
DD(3V3)
VREF
V
SSA
, V
SS
VECTORED
INTERRUPT
CONTROLLER
16 kB
SRAM
USB WITH
4 kB RAM
AND DMA
GP DMA
CONTROLLER
I
2
S INTERFACE
SPI, SSP0 INTERFACE
I2SRX_SDA
I2STX_SDA
MISO, MISO0
SSP1 INTERFACE
SD/MMC CARD
INTERFACE
MCICMD,
MCIDAT[3:0]
TXD0, TXD2, TXD3
UART0, UART2, UART3
UART1
DTR1, RTS1
DSR1, CTS1, DCD1,
RI1
I
2
C0, I
2
C1, I
2
C2
SDA0, SDA1, SDA2
EXTERNAL INTERRUPTS
CAPTURE/COMPARE
TIMER0/TIMER1/
TIMER2/TIMER3
A/D CONVERTER
D/A CONVERTER
2 kB BATTERY RAM
RTC
OSCILLATOR
REAL-
TIME
CLOCK
WATCHDOG TIMER
SYSTEM CONTROL
2 × CAP0/CAP1/
CAP2/CAP3
4 × MAT2,
2 × MAT0/MAT1/
MAT3
6 × PWM1
2 × PCAP1
AOUT
VBAT
AHB TO
APB BRIDGE
SRAM
RMII(8)
V
BUS
002aad328
P0, P2
power domain 2
AHB2
AHB1
power domain 2
V
DD(DCDC)(3V3)
UM10211 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
User manual Rev. 4.1 — 5 September 2012 15 of 708
NXP Semiconductors
UM10211
Chapter 1: LPC23xx Introductory information
Fig 5. LPC2388 block diagram
PWM1
ARM7TDMI-S
PLL
EINT3 to EINT0
FLASH
P3, P4
P0, P1, P2,
LEGACY GPI/O
56 PINS TOTAL
P0, P1
SCK, SCK0
MOSI, MOSI0
SSEL, SSEL0
SCK1
MOSI1
MISO1
SSEL1
SCL0, SCL1, SCL2
I2SRX_CLK
I2STX_CLK
I2SRX_WS
I2STX_WS
8 × AD0
RTCX1
RTCX2
MCICLK, MCIPWR
RXD0, RXD2, RXD3
TXD1
RXD1
RD1, RD2
TD1, TD2
CAN1, CAN2
USB port 1
XTAL1
TCK TDO
EXTIN0
XTAL2
RESET
TRST
TDITMS
HIGH-SPEED
GPI/O
104 PINS
TOTAL
LPC2388
USB port 2
64 kB
SRAM
512 kB
FLASH
INTERNAL
CONTROLLERS
TEST/DEBUG
INTERFACE
EMULATION
TRACE MODULE
trace signals
AHB
BRIDGE
AHB
BRIDGE
ETHERNET
MAC WITH
DMA
16 kB
SRAM
MASTER
PORT
AHB TO
AHB BRIDGE
SLAVE
PORT
system
clock
SYSTEM
FUNCTIONS
INTERNAL RC
OSCILLATOR
V
DDA
V
DD(3V3)
VREF
V
SSA
, V
SS
VECTORED
INTERRUPT
CONTROLLER
16 kB
SRAM
USB WITH
4 kB RAM
AND DMA
GP DMA
CONTROLLER
I
2
S INTERFACE
SPI, SSP0 INTERFACE
I2SRX_SDA
I2STX_SDA
MISO, MISO0
SSP1 INTERFACE
SD/MMC CARD
INTERFACE
MCICMD,
MCIDAT[3:0]
TXD0, TXD2, TXD3
UART0, UART2, UART3
UART1
DTR1, RTS1
DSR1, CTS1, DCD1,
RI1
I
2
C0, I
2
C1, I
2
C2
SDA0, SDA1, SDA2
EXTERNAL INTERRUPTS
CAPTURE/COMPARE
TIMER0/TIMER1/
TIMER2/TIMER3
A/D CONVERTER
D/A CONVERTER
2 kB BATTERY RAM
RTC
OSCILLATOR
REAL-
TIME
CLOCK
WATCHDOG TIMER
SYSTEM CONTROL
2 × CAP0/CAP1/
CAP2/CAP3
4 × MAT2,
2 × MAT0/MAT1/
MAT3
6 × PWM1
2 × PCAP1
AOUT
VBAT
AHB TO
APB BRIDGE
SRAM
RMII(8)
V
BUS
002aad332
P0, P2
power domain 2
AHB2
AHB1
power domain 2
V
DD(DCDC)(3V3)
A[15:0]
D[7:0]
EXTERNAL
MEMORY
CONTROLLER
OE, CS0, CS1,
BLS0
ALARM
UM10211 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
User manual Rev. 4.1 — 5 September 2012 16 of 708
2.1 Memory map and peripheral addressing
ARM processors have a single 4 GB address space. The following table shows how this
space is used on NXP embedded ARM devices. For memory option details see Table 2
.
2.2 Memory maps
The LPC2300 incorporates several distinct memory regions, shown in the following
figures. Figure 7
, Figure 8, and Figure 9 show the overall map of the entire address space
from the user program viewpoint following reset. The interrupt vector area supports
address remapping, which is described later in this section.
UM10211
Chapter 2: LPC23XX Memory addressing
Rev. 4.1 — 5 September 2012 User manual
Table 9. LPC2300 memory usage
Address range General use Address range details and description
0x0000 0000 to
0x3FFF FFFF
on-chip
NV memory
and fast I/O
0x0000 0000 - 0x0007 FFFF flash memory (up to 512 kB)
0x3FFF C000 - 0x3FFF FFFF fast GPIO registers
0x4000 0000 to
0x7FFF FFFF
on-chip RAM 0x4000 0000 - 0x4000 7FFF RAM (up to 32 kB)
0x4000 0000 - 0x4000 FFFF RAM (64 kB for LPC2387/88)
0x7FD0 0000 - 0x7FD0 1FFF USB RAM (8 kB)
0x7FD0 0000 - 0x7FD0 3FFF USB RAM (16 kB for LPC2387/88)
0x7FE0 0000 - 0x7FE0 3FFF Ethernet RAM (16 kB)
0x8000 0000 to
0xDFFF FFFF
off-chip memory Two static memory banks, 64 KB each (LPC2377/78 and LPC2388 only):
0x8000 0000 - 0x8000 FFFF static memory bank 0, 64 KB
0x8100 0000 - 0x8100 FFFF static memory bank 1, 64 KB
0xE000 0000 to
0xEFFF FFFF
APB peripherals 0xE000 0000 - 0xE008 FFFF 36 peripheral blocks, 16 kB each (some unused),
see Tab le 10
.
0xE01F C000 - 0xE01F FFFF System Control Block
0xF000 0000 to
0xFFFF FFFF
AHB peripherals 0xFFE0 0000 - 0xFFE0 3FFF Ethernet Controller (not LPC2361)
0xFFE0 4000 - 0xFFE0 7FFF General Purpose DMA Controller
0xFFE0 8000 - 0xFFE0 BFFF External Memory Controller (EMC) (LPC2377/78,
LPC2388 only)
0xFFE0 C000 - 0xFFE0 FFFF USB Controller (LPC2361/62/64/66/68, LPC2378,
LPC2387, and LPC2388 only).
0xFFFF F000 - 0xFFFF FFFF Vectored Interrupt Controller (VIC)
UM10211 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
User manual Rev. 4.1 — 5 September 2012 17 of 708
NXP Semiconductors
UM10211
Chapter 2: LPC23XX Memory addressing
Fig 6. LPC2461/63 memory map
0.0 GB
1.0 GB
TOTAL OF 64 kB ON-CHIP NON-VOLATILE MEMORY (LPC2361)
TOTAL OF 128 kB ON-CHIP NON-VOLATILE MEMORY (LPC2362)
0x0000 0000
0x0000 FFFF
0x0001 0000
0x0001 FFFF
0x0002 0000
RESERVED FOR ON-CHIP MEMORY
8 kB LOCAL ON-CHIP STATIC RAM (LPC2361)
32 kB LOCAL ON-CHIP STATIC RAM (LPC2362)
RESERVED ADDRESS SPACE
RESERVED ADDRESS SPACE
0x4000 0000
0x4000 2000
0x4000 8000
0x7FD0 0000
0x7FE0 0000
0x7FD0 1FFF
0x7FE0 3FFF
0x4000 1FFF
0x4000 7FFF
2.0 GB
0x8000 0000
BOOT ROM AND BOOT FLASH
(BOOT FLASH REMAPPED FROM ON-CHIP FLASH)
3.0 GB 0xC000 0000
RESERVED ADDRESS SPACE
3.75 GB
4.0 GB
3.5 GB
AHB PERIPHERALS
APB PERIPHERALS
0xE000 0000
0xF000 0000
0xFFFF FFFF
GENERAL PURPOSE OR USB RAM (8 KB)
ETHERNET RAM (16 kB)
002aae283
UM10211 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
User manual Rev. 4.1 — 5 September 2012 18 of 708
NXP Semiconductors
UM10211
Chapter 2: LPC23XX Memory addressing
Fig 7. LPC2364/65/66/67/68 system memory map
0.0 GB
1.0 GB
TOTAL OF 128 kB ON-CHIP NON-VOLATILE MEMORY (LPC2364)
TOTAL OF 512 kB ON-CHIP NON-VOLATILE MEMORY (LPC2367/68)
TOTAL OF 256 kB ON-CHIP NON-VOLATILE MEMORY (LPC2365/66)
0x0000 0000
0x0001 FFFF
0x0002 0000
0x0003 FFFF
0x0007 FFFF
0x0008 0000
0x0004 0000
RESERVED FOR ON-CHIP MEMORY
8 kB LOCAL ON-CHIP STATIC RAM (LPC2364)
32 kB LOCAL ON-CHIP STATIC RAM (LPC2365/66/67/68)
RESERVED ADDRESS SPACE
RESERVED ADDRESS SPACE
0x4000 0000
0x4000 2000
0x4000 8000
0x7FD0 0000
0x7FE0 0000
0x7FD0 1FFF
0x7FE0 3FFF
0x4000 1FFF
0x4000 7FFF
2.0 GB
0x8000 0000
BOOT ROM AND BOOT FLASH
(BOOT FLASH REMAPPED FROM ON-CHIP FLASH)
3.0 GB 0xC000 0000
RESERVED ADDRESS SPACE
3.75 GB
4.0 GB
3.5 GB
AHB PERIPHERALS
APB PERIPHERALS
0xE000 0000
0xF000 0000
0xFFFF FFFF
GENERAL PURPOSE OR USB RAM (8 KB)
ETHERNET RAM (16 kB)
002aac577
UM10211 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
User manual Rev. 4.1 — 5 September 2012 19 of 708
NXP Semiconductors
UM10211
Chapter 2: LPC23XX Memory addressing
Fig 8. LPC2377/78 system memory map
0.0 GB
1.0 GB
TOTAL OF 512 kB ON-CHIP NON-VOLATILE MEMORY
0x0000 0000
0x0007 FFFF
0x0008 0000
RESERVED ADDRESS SPACE
32 kB LOCAL ON-CHIP STATIC RAM
RESERVED ADDRESS SPACE
RESERVED ADDRESS SPACE
0x4000 0000
0x4000 8000
0x7FD0 0000
0x7FE0 0000
0x7FD0 1FFF
0x7FE0 3FFF
0x4000 7FFF
2.0 GB
0x8000 0000
0x8000 FFFF
0x8100 FFFF
0x8100 0000
BOOT ROM AND BOOT FLASH
(BOOT FLASH REMAPPED FROM ON-CHIP FLASH)
3.0 GB 0xC000 0000
RESERVED ADDRESS SPACE
3.75 GB
4.0 GB
3.5 GB
AHB PERIPHERALS
APB PERIPHERALS
0xE000 0000
0xF000 0000
0xFFFF FFFF
GENERAL PURPOSE OR USB RAM (8 kB)
ETHERNET RAM (16 kB)
002aac585
EXTERNAL MEMORY BANK 0 (64 kB)
EXTERNAL MEMORY BANK 1 (64 kB)
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NXP LPC2377FBD144 User guide

Category
Video converters
Type
User guide

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