Hand Held Products IT4300 Integration Manual

Type
Integration Manual
Integration Manual
IMAGETEAM™ 4X00 Series
For the following imagers:
IT4000SR, SF, or HD, IT4100SR, SF, or HD, and
IT4300SR, SF, or HD
Disclaimer
Hand Held Products, Inc. (“Hand Held Products”) reserves the right to make changes in specifications and other information
contained in this document without prior notice, and the reader should in all cases consult Hand Held Products to determine
whether any such changes have been made. The information in this publication does not represent a commitment on the part
of Hand Held Products.
Hand Held Products shall not be liable for technical or editorial errors or omissions contained herein; nor for incidental or
consequential damages resulting from the furnishing, performance, or use of this material.
This document contains proprietary information that is protected by copyright. All rights are reserved. No part of this document
may be photocopied, reproduced, or translated into another language without the prior written consent of Hand Held Products.
© 2002-2005 Hand Held Products, Inc. All rights reserved.
Web Address: www.handheld.com
Microsoft
®
Visual C/C++
®
, Windows
®
95, Windows
®
98, Windows
®
2000, and Windows NT
®
are either registered trademarks
or trademarks of Microsoft Corporation in the United States and/or other countries.
Other product names mentioned in this document may be trademarks or registered trademarks of other companies and are the
property of their respective owners.
Note: Specification drawings are for reference only. Please contact Hand Held Products for the most current drawing.
FCC/CE
The IMAGETEAM™ (IT) 4X00 Series Image Engine, integrated into an OEM device, may require testing by the OEM to insure
compliance with the following federal regulations:
47 CFR Part 15
EC’s Electromagnetic Compatibility Directive (89/336/EEC) and Low Voltage Directive (73/23/EEC)
For CE-related inquiries, please contact:
Hand Held Products, Inc.
Nijverheidsweg 9
5627 BT Eindhoven
The Netherlands
Hand Held Products shall not be liable for use of our product with equipment (i.e., power supplies, personal computers, etc.) that
is not CE marked and does not comply with the Low Voltage Directive.
LED Eye Safety Statement for IT4000/IT4100 Series Engines
The IT4000/IT4100 series engine meets the requirements of a Class 1 Product as specified in IEC 825-1:1993 and EN 60825-
1:1994 when tested in a standard IT4410 and IT4710.
It is the OEM manufacturer’s responsibility to comply with applicable regulation(s) in regard to standards for specific equipment
combinations.
Caution - Use of controls or adjustments or performance of procedures other than those specified herein may result in hazardous
radiation exposure.
Laser Eye Safety Statement for IT4300 Series Engines
The IT4300 is intended for use in CDRH/IEC Class 2 devices.
Note: It is the OEM manufacturer’s responsibility to comply with applicable regulation(s) in regard to standards for specific
equipment combinations.
Caution - Use of controls or adjustments or performance of procedures other than those specified herein may result in hazardous
radiation exposure.
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i
Chapter 1 - Introduction and Installation
About the 2D Image Engine................................................................................................................1-1
ESD Precautions..................................................................................................................................1-1
Dust and Dirt .......................................................................................................................................1-1
Product Specifications.........................................................................................................................1-1
Interface Connector .............................................................................................................................1-2
Connector View ............................................................................................................................1-2
Connector Mechanical ..................................................................................................................1-2
Imager Orientation........................................................................................................................1-3
Connector Position and Flex Orientation......................................................................................1-3
Connector.............................................................................................................................................1-3
Connector Pinout...........................................................................................................................1-3
Electrical Interface Considerations......................................................................................................1-4
Chapter 2 - Working with the IT4X00 Series
Serial Command Interface (I
2
C)..........................................................................................................2-1
Data Write Sequence.....................................................................................................................2-1
Data Read Sequence......................................................................................................................2-1
I2C Style Interface Basic Waveforms...........................................................................................2-2
Timing Chain.......................................................................................................................................2-2
Control Register Table..................................................................................................................2-2
Vertical Considerations.................................................................................................................2-2
Horizontal Considerations.............................................................................................................2-3
Active Pixel Window Alignment ........................................................................................................2-3
Vertical..........................................................................................................................................2-4
Horizontal......................................................................................................................................2-4
Interdependencies................................................................................................................................2-4
Column Position of CDS Subtraction Pulse (Reg. 0x9C, 0x9B)..................................................2-4
Exposure vs. Frame Height (Number of Lines per Frame)...........................................................2-4
Changes in Exposure Value vs. Frame Height .............................................................................2-5
Exposure vs. Frame Width (Number of Pixel Clocks per Line/Row) ..........................................2-5
Exposure Control Method and Exposure/Data Clock Out Timeline...................................................2-5
The Effects of Timing on Noise ..........................................................................................................2-6
Register Settings and Associated Timing Diagrams for Windowed Image Acquisition ....................2-6
Initial Configuration (FPGA, ASIC).............................................................................................2-6
Preliminary Intel PXA27X Interface ............................................................................................2-7
Illumination/Aimer Control...............................................................................................................2-10
Aimer Modes...............................................................................................................................2-10
Laser Aimer Thermal Considerations.........................................................................................2-11
LED Power Control PWM..........................................................................................................2-11
LED Current for Selected Duty Cycle Settings ..........................................................................2-11
Table of Contents
ii
Chapter 3 - Electrical
DC Characteristics...............................................................................................................................3-1
Operating Voltage ........................................................................................................................3-1
Imager Input/Output Voltage........................................................................................................3-1
LED Input Voltage........................................................................................................................3-1
Current ..........................................................................................................................................3-1
AC Characteristics...............................................................................................................................3-2
Frame Timing................................................................................................................................3-2
Line Timing...................................................................................................................................3-3
Pixel Clock Edge Transition Detail ..............................................................................................3-3
AC Timing 30 Frames per Second................................................................................................3-3
Imager Startup Timing..................................................................................................................3-4
LED Power Supply Startup Timing..............................................................................................3-4
Image Acquisition Timeline..........................................................................................................3-4
Standard Mounting Configuration for IT4000 ....................................................................................3-6
Optional Mounting Configuration for IT4000.....................................................................................3-7
Standard Mounting Configuration for IT4100 ....................................................................................3-8
Optional Mounting Configuration for IT4100.....................................................................................3-9
Standard Mounting Configuration for IT4300 ..................................................................................3-11
Optional Mounting Configuration for IT4300...................................................................................3-12
Chapter 4 - Optics and Illumination
Window Placement..............................................................................................................................4-1
Distance from Window.................................................................................................................4-1
Window Size and Material Requirements...........................................................................................4-1
Code Presentation Angle .....................................................................................................................4-2
Ambient Light......................................................................................................................................4-2
Eye Safety Standard for IT4000/IT4100 Series Engines.....................................................................4-3
Eye Safety Standard for IT4300 Series Engines .................................................................................4-3
LEDs....................................................................................................................................................4-3
Chapter 5 - Customer Support
Product Service and Repair .................................................................................................................5-1
Online Product Service and Repair Assistance.............................................................................5-1
Technical Assistance ...........................................................................................................................5-2
Online Technical Assistance.........................................................................................................5-2
Limited Warranty ................................................................................................................................5-2
Appendix A - FPGA/ASIC Imager Interface
Appendix B - FIFO Depth Based on System Assessment
Appendix C - Imager Power Supply Noise and PCB Layout
Considerations and Methods for the Power Supply.....................................................................C-1
Appendix D - Hardware and Software Interdependencies
IMAGETEAM™ 4X00 Series Integration Manual 1 - 1
1
Introduction and Installation
About the 2D Image Engine
The IMAGETEAM™ (IT) 4X00 Series are small image engines designed for integration into handheld portable data terminals or
other OEM devices. The IT4X00 Series are input devices for reading and decoding linear, stacked linear (PDF417), and 2D
matrix bar code symbologies. The IT4X00 Series incorporate the latest CMOS-based area array sensors. This technology is
being adopted in other markets and products, for example, digital cameras, PC-based video conferencing, video surveillance,
automobiles, and toys. The IT4X00 Series 2D Image Engines function like digital cameras and add functionality and value to an
OEM product by adding additional capabilities such as digital image capture, document lift, signature capture, and reading OCR
A and B characters.
The IT4X00 Series Image Engines are specifically designed for easy integration into most existing portable data terminals. The
size and current draw of the devices allow the engines to drop in with few mechanical modifications. The decoder module
supports a TTL standard RS-232 interface that, in most cases, does not require any hardware modifications to existing platforms.
To ease integration efforts, a Software Developers Kit provides a simple software interface (APIs).
ESD Precautions
The IT4X00 Series engine is shipped in ESD safe packaging. Use care when handling the scan engine outside its packaging.
Be sure grounding wrist straps and properly grounded work areas are used.
Dust and Dirt
The IT4X00 Series engine must be sufficiently enclosed to prevent dust particles from gathering on the imager and lens. Dust
and other external contaminants will eventually degrade unit performance.
Product Specifications
1. Measured from the end of the lens tube.
Parameter Specification
Dimensions
See page 3-6 or page 3-7.
Weight Less than 2 ounces (56 g) (Decode Module and Image Module - less than 1 ounce (28.4 g) each)
Illumination Source 626 +
30 nm red LEDs
Aiming Pattern Source
526 +30 nm green LEDs
optional 626±30 nm red LEDs (IT4000 only)
Laser Aimer
650 nm +10 nm/-5 nm
Resolution
SR/SF
5 mil minimum, Linear symbol
15 mil (.38mm) minimum, 2D Matrix symbol
HD
4 mil (.10mm) minimum, Linear symbol
9 mil (.23mm) minimum, 2D Matrix symbol
Rotational Sensitivity
360° around optical axis
Viewing Angle
±40° at the nominal operating distance
Motion Sensitivity approx. 2 inches (5 cm) per second of lateral motion
Ambient Light Total darkness to 100,000 Lux (sunlight)
Temperature Ranges
Operating 14° F to +122° F (-10C to +50C)
Storage -40° F to +158° F (-40C to +70C)
Humidity
95% RH non-condensing
1 - 2 IMAGETEAM™ 4X00 Series Integration Manual
Interface Connector
Molex FFC/FPC Connector 54393-2192 drawings taken from Molex Catalog page MX01. 0.3 mm (0.012 in.) pitch, Right Angle,
SMT, ZIF, Bottom Contact.
Connector View
Connector Mechanical
Units = Millimeters
Inches
IMAGETEAM™ 4X00 Series Integration Manual 1 - 3
Imager Orientation
When the IT4X00 Series is mounted with the label pointing up, captured images appear right side up.
Connector Position and Flex Orientation
Connector
The interface connector is a Molex 0.30mm (.012") Easy-On™ Type Right Angle, SMT, ZIF, Bottom Contact Style Receptacle
part number 54393-2192. See Interface Connector on page 1-2 for details.
Connector Pinout
Pin Signal Description
1 Ground Power and signal ground.
2 LED Current Control PWM Input - Controls the LED current. A pulse width modulated signal based on a frequency of 7.5K Hz
reduces the current of the LED power supply. The relationship of current to duty cycle is inversely pro-
portional (the longer the duty cycle, the lower the current). Leave this pin unconnected if not using this
feature.
3 Ground Power and signal ground.
4 Horizontal Sync (H Data Valid) Output - Definition varies according to the setting of the image registers. For the configuration defined in
this document, this signal is used as a data valid window. Polarity of this signal is selectable in register
address 0x01, Bit 1. Hand Held Products setting is 1 = active high window.
5 Vertical Sync (V Data Valid) Output - Definition varies according to the setting of the image registers. For the configuration defined in
this document, this signal is used as a data valid window. Polarity of this signal is selectable in register
address 0x01, Bit 2. Hand Held Products setting is 0 = active low window.
6 Aimer On Input - Active high on this line enables the LED power supply and turns on the 2 aiming LEDs. This line
may be pulse width modulated many times per horizontal line (based on pixel clock) in order to reduce
power.
7 Illumination On Input - Active high on this line enables the LED power supply and turns on the 4 illumination LEDs. This
line may be pulse width modulated many times per horizontal line (based on pixel clock) in order to
reduce power.
8 Power Enable Input - Active high enables the imager. A low on this line places the imager in a power down state.
9
I
2
C Data (SDA)
Imager follows slave protocols with respect to this signal.
10
I
2
C Clock (SCL)
Imager follows slave protocols with respect to this signal.
Top
Flex
1 - 4 IMAGETEAM™ 4X00 Series Integration Manual
Electrical Interface Considerations
When designing the host system circuitry with a switched V
In
imager, you must make sure there is no leakage path from the host
into the imager I/O lines. Leakage back into the imager I/O causes the imager V
In
to be back powered via the imager’s internal
pull-ups, protection diodes, and parasitic FET diodes. This results in unwanted current draw and causes the imager's power up
reset system to fail. A power up reset failure causes the imager to behave erratically and it may not respond correctly to I
2
C
commands.
11 Vin LED +3V to +9V - Power supply input for LED illumination and aiming.
12 D0 Output - Pixel data. Data lines change on each falling edge of pixel clock. Data is considered valid on
the rising edge of pixel clock.
13 Vin Imager Vin Imager, +3.3V - Power supply for the imager. Care must be taken to ensure this supply is heavily
decoupled and is protected from cross coupling to high frequency signals of the processing/decoding cir-
cuitry. A broad band filter may be needed to obtain adequate isolation. See Considerations and Methods
for the Power Supply on page C-1.
When designing the host system circuitry with a switched V
In
imager, you must guarantee there is no
leakage path from the host into the imager I/O lines. Leakage back into the imager I/O causes the
imager V
In
to be back powered via the imager’s internal pull-ups, protection diodes, and parasitic FET
diodes. This results in unwanted current draw and the imager's power up reset system will fail. The
imager behaves erratically and may not respond correctly to I2C commands when there is a power up
reset failure.
14 D1
Output - Pixel data. Data lines change on each falling edge of pixel clock. Data is considered valid on
the rising edge of pixel clock.
15 D2
16 D3
17 D4
18 D5
19 D6
20 D7
21 Pixel Clock (PCLK) Output - Imager timing signal that clocks pixel data. Data is valid on the rising edge of this signal.
Pin Signal Description
IMAGETEAM™ 4X00 Series Integration Manual 2 - 1
2
Working with the IT4X00 Series
Serial Command Interface (I
2
C)
The imager on the IT4X00 Series engine uses an I
2
C style interface to write and read the internal control registers.
Note: The register address pointer does NOT automatically increment the register pointer.
Each write to a sequential register requires the sub address (register address) be written with one byte of data. Each read from
a register other than the register last accessed (read or write) must have the sub address set using a “no data” write sequence
followed by the actual read. Only one byte of data should be clocked out when performing this read.
Slave Read/Write Address:Write Slave address40 Hex
Read Slave address41 Hex
Data Write Sequence
The following is an example of an I
2
C write to the IT4X00 Series sequence:
Data Read Sequence
An I
2
C read consists of a two step process. The first step is a transmit in write mode of the slave address, the sub address and
then a termination (a no data write). The first step sets the register address pointer inside the imager in preparation for the read.
The second step is the actual read of the data from the register of interest.
The following example shows the two step address write/read sequence:
Start Slave Address (7) R/W Ack Sub Address Ack Data Ack Stop
Master Slave
(bit)
(Reg Add)
0
(byte)
Master
(byte)
Slave
(bit)
Slave
(bit)
Master
(byte)
Start Slave Address (7) R/W Ack Sub Address Ack Stop
Master Slave
(bit)
(Reg Add)
0
(byte)
Master
(byte)
Slave
(bit)
Start Slave Address (7) R/W Ack Sub Address Ack Stop
Master Slave
(bit)
(Reg Add)
0
(byte)
Master
(byte)
Slave
(bit)
Start Slave Address (7) R/W Ack Data Ack Stop
Master Slave
(bit)
1
(byte)
Master
(bit)
Slave
(byte)
2 - 2 IMAGETEAM™ 4X00 Series Integration Manual
I
2
C Style Interface Basic Waveforms
The following information is provided for reference. The I
2
C-Bus Specification should be consulted for a complete understanding
of the this interface.
Timing Chain
Control Register Table
*Value is 20 pixels > 640 active plus 10 light shielded pixels to ensure a good dark region for CDS subtractive pulse sample.
**5 lines > active plus 10 light shielded lines.
Vertical Considerations
When you change the value of the row start register you do
not
delay the data output. The value of this register sets a row pointer
that is allowed to roll over. The result is the output of all data from frame 10 during the frame 10 scan out period.
Example: If the row start value is set to 520 in a 525 row frame, then the active row number 4 of frame 10 is actually seen at
the beginning of frame 10 (not 11), and the first 5 lines of frame 10 occur at the end of 10. This means that a
movement of the active row start appears as a delay in time until the value set in registers 0x15, 0x14 reaches a
number that, when added to the active row count of 490, is greater than the frame height. Therefore, a start row of
50 causes the last 15 active rows to be output first, followed by 35 inactive rows, then the first 475.
525 - (490+50) = -15
Control Register
Address
Description Min/Max (Dec)
0x0D,0x0C Frame Width (columns/pixel clocks) 670* / 1023
0x0E, 0x0f Frame Height (rows/lines) 495** / 1023
0x11, 0x11 Column to start output of active pixels 0 / 1023
0x15, 0x14 Row to start output of active pixels 0 / 1023
0x19, 0x18 Hsync end column (width) 1 / FW-1
0x1A,0x1B Vsync end row (width) 1 / FH-1
0x9C, 0x9B CDS Subtractive Pulse Column position 1 / FW-1
Stop
SCL
SDA
Start
Sp
89
ACK
St
2 21
ACK
SCL
8
SDA
1 9
Start and Stop condition waveforms:
Data Transfer waveforms:
IMAGETEAM™ 4X00 Series Integration Manual 2 - 3
Frame start of row/line 10 appears as a delay of ten lines from Vertical:
Frame start set to row/line 50 causes the last lines of the frame to occur first:
Horizontal Considerations
When you change the value of the column start register you do
not
delay the data output. The value of this register sets a column
pointer that is allowed to roll over. The result is the output of all data from row 120 during the row 120 scan out period.
Example: If the column start value is set to 840 in an 858 column row, then the active column number 632 of row 120 is actually
seen at the beginning of row 120 (not 121), and the first 18 lines of row 120 occur at the end of 120. This means that
a movement of the active column start appears as a delay in time until the value set in registers 0x11, 0x10 reaches
a number that, when added to the active column count of 650, is greater than the frame width. For a start of 840, the
last 632 pixels are output first, with the first 18 output at the end of the row.
858 - (650+840) = -632
Typical row with column start set to 180, frame width 858:
Row with column start set to 840, frame width 858:
Active Pixel Window Alignment
The following settings are used to generate the timing signals that create a data valid window from the vertical and horizontal
synchronization signals from the IC Media ICM-105A.
Vertical
Frame Start
Row Data
F4:R90
0 525
Beg Fr 5
F4:R10
Vertical
End Fr 3
Row Data
F4:R490 F4:R50
Frame Start
Beg Fr 5
Horizontal
Column Start
Pixel Data
R20:C180 R20:C650
Horizontal
Pixel Data
End Row 19
R20:P19 R20:P650 R20:C840 Row 21
Column Start
2 - 4 IMAGETEAM™ 4X00 Series Integration Manual
Ver ti cal
The vertical timing is configured with the active row start value (reg 0x15, 0x14) where the last 485 active rows, or lines of video,
of a 525 row frame are output immediately after the leading edge of the vertical signal, and the first five rows appear at the end
of the frame. The vertical pulse end is set to occur at row 480. The acquisition circuit acquires while the vertical signal is low.
Therefore, the circuit acquires data only during the low vertical window created by these settings.
Vertical data valid window data alignment:
The window is derived so the first and last 5 light shielded rows are ignored. Other row count value combinations are possible.
Horizontal
The horizontal pixel alignment and timing is similar to the vertical. The imager inverts the horizontal signal, Hsync end is set to
640, frame width (row length) is 858 pixel clocks per row, and the data is positioned at column start 853. This configuration
creates a window that presents the last 853 pixels first (640 + 5 light shielded + 28 blanks), and the first 5 light shielded pixels at
the end of the row.
Horizontal data valid window data alignment:
Interdependencies
Column Position of CDS Subtraction Pulse (Reg. 0x9C, 0x9B)
The register value for the CDS subtractive pulse must be considered when adjusting the frame width (FW) and the start of active
data column settings. As noted in the Control Register Table (see page 2-2), this value must be less than the value entered for
FW. If CDS is greater than FW, the imager produces very strange video data results.
The IT4X00 Series engine does not perform the Correlated Double Sampling (CDS) method as the pixel’s value is read and
converted. The correlation samples are taken on a row basis. This means that the correlation samples for an entire row (line)
are taken when the row is reset prior the start of integration. The position of this correlation sample, selected by these registers,
determines when the correlation sample value is subtracted from the integration value of the video samples for each horizontal
line. The ideal column setting for the CDS subtractive pulse is at the end of the row after the active pixel data. Placing the
subtractive pulse during active pixel data leads to unpredictable results.
Exposure vs. Frame Height (Number of Lines per Frame)
The exposure is controlled by setting the number of rows (lines) to allow the pixels to acquire charge (row as a measure of
integration time based on RowCount * T
row
). The frame height must be set to a minimum value equal to the total number of active
lines (490),
or
to a number of rows that is greater than or equal to the exposure setting, but not greater than the maximum value
of 1023 ( [490 or Exp] < FH < 1023).
Vertical
Row Data
Horizontal
Row Data
IMAGETEAM™ 4X00 Series Integration Manual 2 - 5
Changes in Exposure Value vs. Frame Height
The time (measured in frames) for a new exposure to fully take effect is dependent on the absolute value of the change in
exposure (in rows) as it relates to the difference of the frame height (FH) minus the last active video row (LAVR). An exposure
change that is greater than the frame height/last active row difference requires two frames before the new exposure takes full
effect. An exposure change that is less than or equal to the difference takes one frame to take full effect.
This may be expressed as:
If |dExposure| <= (FH - LAVR) then Frames to full effect = 1
If |dExposure| > (FH - LAVR) then Frames to full effect = 2
Example: For a video configuration of Frame Height (FH) = 525 and a last active video row position of 500 (490 rows with active
frame start at row 10), a change in exposure of 26 rows requires 2 frames to full effect.
Exposure vs. Frame Width (Number of Pixel Clocks per Line/Row)
The exposure is controlled by setting the number of rows (lines) to allow the pixels to acquire charge. Changing frame width,
measured in columns or Pixel Clocks per Row, has the greatest impact on exposure. Since the time to scan one row (T
row
) is
the basis for defining integration time, the exposure or integration time as a function of row count is:
T
I
= RowCount * T
row
and is therefore directly proportional to the time to scan one row.
T
row
= PixClkPerRow * T
PixClk
Exposure Control Method and Exposure/Data Clock Out Timeline
The exposure is controlled by an electronic shutter (see Electronic Shutter Exposure Method, page 2-5). The pixel array is
always exposed to light in this method of exposure control (unlike the mechanical shutter method that shields the imager array
from incoming light when not exposing). Therefore the image array must have some way of adjusting the system so that only
the charge collected for the desired time of exposure is read out of the imager. The exposure control circuitry of the imager
performs this task by allowing the photo diode array to collect charge until the time the next vertical minus the exposure
(measured in rows) is reached. The unwanted charge collected to this point is then removed from the photodiodes and the
charge is allowed to build again over the desired exposure interval. The wanted charge is collected at the end of the line.
Electronic Shutter Exposure Method
Since the charge is collected at the end of the frame, this charge data is not clocked out of the imager during this frame. The
data is clocked during the next frame interval. Therefore, the data read from the imager is delayed by one frame time:
Vert
Charge on
Photo Diode
Charge is dumped
(reset)
Exposure Time
(wanted charge)
Expose
Read Out
Frame 1 Frame 2 Frame 3
1st 2nd 3rd
Frame 1 Frame 2
1st 2nd
2 - 6 IMAGETEAM™ 4X00 Series Integration Manual
The Effects of Timing on Noise
IC Media has admitted that the settings and active area output timing selection can affect the noise levels within a given image.
Noise injection changes as the A/D samples are aligned with different points in the timing sequence. The best settings keep the
active pixels away from specific timing regions such as vertical and horizontal synchronization pulses which cause a flurry of
switching signal occurrences.
Register Settings and Associated Timing Diagrams for Windowed Image Acquisition
Initial Configuration (FPGA, ASIC)
The register settings of the initial Hand Held Products configuration are shown in the following table. The configuration generates
timing signals that create data acquisition windows for frame (vertical) and horizontal (row, line) data valid regions. The timing
is based on the IC Media default frame height and line width that provide a frame rate of 30 fps.
Initial Hand Held Products Register Settings for IC Media ICM105A
Register
Hex
Address
Initial Hand Held
Products
Hex Dec
Timing Control 02, 01 001B -
Frame Width (pclk) 0D, 0C 035A 858
Frame Height (lines) 0F, 0E 020D 525
Beg act pix out (pclk)
1
1.These values may be changed to meet the hardware timing requirements of the host
system.
11,10 0355 853
Beg act frame out (lines)
1
15, 14 0208 520
Horiz pulse width (pclk) 19, 18 0280 640
Vert Pulse Width (lines) 1B, 1A 01E0 480
CDS subt pulse pos (pclk)
Must be FW - 1 or placed after last active pixel
9C, 9B 0342 834
Exp time (pclk) 1D, 1C FF00 65280
IMAGETEAM™ 4X00 Series Integration Manual 2 - 7
Timing Control LSB (Address O1)
Initial Hand Held Products Configuration Vertical Timing
Note the row/line data relationship within each frame. The data presented within each line is the data from that line. The IT4X00
Series engine does not present data rolled over from a previous frame, nor is data rolled back from a future frame (refer to Vertical
Considerations, page 2-2).
Initial Hand Held Products Configuration Horizontal Row/Line Timing
Preliminary Intel PXA27X Interface
The Intel
®
PXA27X (Bulverde) integrates a CMOS imager interface on the chip that can be used to interface to the IT4X00 Series.
The interface uses a synchronization tracking timing circuit that is very flexible and relatively easy to use.
Reserved Reserved Reserved Reserved Reserved VSync Polarity HSync Polarity Reserved
0 0 0 1 1 0=Active Low
1=Active High
0=Active Low
1=Active High
1
Vert
Horz
Data
Vsync IRQ
012
479
520 524
First 5 light
shielded lines
35
blank
lines
Last 5
light
shielded
Active rows/lines 6 to 485
Hor
PxCLK
Data
640 Valid Data
208
858
First 5
light
shielded
pixels
Last 5
light
shielded
pixels
2 - 8 IMAGETEAM™ 4X00 Series Integration Manual
IT4X00 Series Register Settings for the PXA27XI
Register settings for the PXA27X CSI interface for use with the IT4X00 Series engines are shown in the following table.
Notes:
d Dynamic value that changes as needed for image capture control.
DMA_EN DMA request Enable. 0=disable; 1=enable.
ENB Camera interface Enable. 0=disable; 1=enable.
DIS Camera interface Disable. 0=do not disable camera interface after capture (continuous scanning); 1=disable cam-
era interface after capture is complete. See CISR CDD flag.
TOM Time-Out Mask. 0=Generate time-out condition interrupt; 1=Do not generate time-out condition interrupt (time-out
of stalled image capture).
QDM Quick Disable Mask. 0=Generate QD interrupt; 1=Do not generate QD interrupt.
CDM Disable Done Mask. 0=Generate capture interface disable done interrupt; 1=Do not generate capture interface dis-
able done interrupt.
EOFM End of Frame Mask. 0=Generate an interrupt at end of frame; 1=Do not generate EOF interrupt.
Notes:
PPL Pixels Per Line. Value of 0 to 2047 where actual number of imager pixels per line = PPL+1 (PPL = imager pixels per
line-1).
RAW_BPP Raw Bits Per Pixel. 0b00=8; 0b01=9; 0b10=10; 0b11=reserved.
DW Imager Data Width. 0b000=4; 0b001=5; 0b010=8; 0b100=10.
Register
Hex
Address
Initial Hand Held
Products
Hex Dec
Timing Control 02, 01 001D -
Frame Width (pclk) 0D, 0C 035A 858
Frame Height (lines) 0F, 0E 020D 525
Beg act pix out (pclk) 11,10 00B4 180
Beg act frame out (lines) 15, 14 0209 521
Horiz pulse width (pclk) 19, 18 0040 64
Vert Pulse Width (lines) 1B, 1A 01E0 480
CDS subt pulse pos (pclk)
Must be FW - 1 or placed after last active pixel
9C, 9B 0342 834
Exp time (pclk) 1D, 1C FF00 65280
CICR0 - Capture Interface Control Register 0
bit 313029282726252423222120191817161514131211109876543210
Setting d00dd000XXXXXXXXXXXXXXd1111dd0d1
DMA_EN
PAR_E N
SL_CAP_EN
ENB
DIS
SIM
Reserved
TOM
RDVAM
FEM
EOLM
PERRM
QDM
CDM
SOFM
EOFM
FOM
CICR1 - Capture Interface Control Register 1
bit 313029282726252423222120191817161514131211109876543210
Setting X00XXX01001111111000000000000010
TBIT
RGBT_CONV
Reserved
PPL (Pixels Per Line)
RGB_CONV
RGB_F
YCBR_F
RGB_BPP
RAW_BPP
COLOR_SP
DW
IMAGETEAM™ 4X00 Series Integration Manual 2 - 9
BLW Beginning of Line. Pixel clock wait 0 to 255. Number of pixel clocks to wait (delay) from the active edge of CIF_LV
(horizontal) to first valid data.
BFW Beginning of Frame Line Wait. 0 to 255 specifies the number of lines to wait from the start of the frame to the first
pixel capture.
LPF Lines Per Frame. 0 to 2047. Actual imager lines per frame = LPF+1 (LPF=imager lines per frame-1).
PCLK_EN Selects if imager is the source of pixel clock. 0=CIF_PCLK is not supplied by sensor (int); 1=CIF_PCLK is supplied
by sensor (ext).
PCP Select the active edge of CIF_PCLK. 0=Data sampled on rising edge of CIF_PCLK; 1=Data sampled on falling
edge of CIF_PCLK.
HSP Horizontal Sync Polarity. 0=CIF_LV is active high, inactive low; 1=CIF_LV is active low, inactive high.
VSP Vertical Sync Polarity. 0=CIF_FV is active high, inactive low; 1=CIF_FV is active low, inactive high.
FR_RATE Frame Capture Rate. Defines the frequency of capture of one video frame (or the number of frames to skip between
captures).
000Capture all incoming frames
001Capture 1 of every 2 frames
010Capture 1 of every 3 frames
011Capture 1 of every 4 frames
100Capture 1 of every 5 frames
101Capture 1 of every 6 frames
110Capture 1 of every 7 frames
111Capture 1 of every 8 frames
Time-out CIF FIFO inactivity time-out interval from 0 to (2
31
-1)
CICR2 - Capture Interface Control Register 2
bit 313029282726252423222120191817161514131211109876543210
Setting 10111001XXXXXXXXXXXXXXXXXXXXXXXX
BLW (Beginning of Line)
ELW (End of Line Wait)
HSW
(Horizontal Sync PW)
Reserved
BFPW (Beg Fr Pix Wait)
FSW
(fr stbl wt)
CICR3 - Capture Interface Control Register 3
bit 313029282726252423222120191817161514131211109876543210
Setting 00101101XXXXXXXXXXXXX00111011111
BFW (Beginning of Frame Wait)
EFW (End of Frame Wait)
VSW
(Vertical Sync PW)
LPF (Lines Per Frame)
CICR4 - Capture Interface Control Register 4
bit 313029282726252423222120191817161514131211109876543210
Setting XXXXX00010110XXXXXXXX00000000000
Reserved
MCLK_DLY
PCLK_EN
PCP
HSP
VSP
MCLK_EN
Reserved
FR_RATE
DIV
CITOR - Capture Interface Time-out Register
bit 313029282726252423222120191817161514131211109 8 7 6 5 4 3 2 1 0
Setting 00000000000000000000000000000000
Time-out
2 - 10 IMAGETEAM™ 4X00 Series Integration Manual
FTO FIFO time-out. 1=Time-out occurred.
FDAV_[2:0] FIFO Channel X data received 1=Received data available for respective channel.
FEMPTY_[2:0] FIFO Channel X empty. 1=Respective channel.
EOL End Of Line. 1=End of line detected.
PAR_ERR Parity Error in serial sync string. 1=Parity error detected.
CQD Camera Interface Quick Disable. 1=Capture interface has been quick disabled.
CDD Camera Interface Disable Done. 1=Capture interface has been disabled and active video frame is complete.
SOF Start Of Frame. 1=Capture interface has detected the start of a frame.
EOF End Of Frame. 1=Capture interface has detected the end of a frame.
IFO[2:0] FIFO overrun in corresponding channel. 1=Respective FIFO channel overrun detected.
d Dynamic value that changes as needed for image capture control.
FLVL[2:0] FIFO level 0, 1, and 2 can be set to buffer 0 to 128, 0 to 64, and 0 to 64 bytes, respectively
THL_0 Threshold Level for FIFO channel 0 (DMA requests are generated when this value is reached). 00-32 bytes; 01-64
bytes; 10-96 bytes; 11 - reserved.
RESET_F Reset input FIFO. 0=no effect; 1=all input FIFOs (and this bit) are cleared.
FEN[2:0] FIFO enable 0, 1, and 2. 0=corresponding FIFO disabled; 1=corresponding FIFO enabled.
Illumination/Aimer Control
There are two primary methods of controlling the total power draw of the illumination and aiming systems: reducing the power,
or pulsing the Illumination On or Aimer On control signals.
Note: Reducing the current/power also reduces the intensity of the illumination. This reduction in light levels directly impacts the
reading attributes of the image module. A reduction in light levels reduces reading distance to target and DOF
performance.
Aimer LEDs are typically not on for prolonged periods of time, therefore a power savings may not be seen by pulsing the Aimer
On control signal.
Pulsing the Illumination On signal can create a large reduction because the illumination LEDs are on during the entire frame time
(24 ms to 33 ms). The control line
must
be pulsed at a rate that is less than the line rate so the LEDs are flashed on and off many
times per line, and for the same number of times each line. If this is not done, light and dark bands appear throughout the image,
reducing reading and image taking performance.
Aimer Modes
Interleaved Mode
Interleaved Mode is characterized by the illumination LEDs and aiming LEDs/Laser being turned on alternately, or in an
interleaved fashion (illumination on, aimer off/illumination off, aimer on). In this mode, the aimer flashes on and off. Interleaved
Mode is the most efficient for power conservation and heat reduction.
CISR - Capture Interface Status Register (clear these flags by writing a one to the corresponding bit)
bit 313029282726252423222120191817161514131211109 8 7 6 5 4 3 2 1 0
Setting XXXXXXXXXXXXXXXX0000000000000000
Reserved
FTO
RDAV_2
RDAV_1
RDAV_0
FEMPTY_2
FEMPTY_1
FEMPTY_0
EOL
PA R_ERR
CQD
CDD
SOF
EOF
IFO_2
IFO_1
IFO_0
CIFR - Capture Interface FIFO Control Register
bit 313029282726252423222120191817161514131211109 8 7 6 5 4 3 2 1 0
Setting XX1000000100000010000000XX01d001
Reserved
FLVL2 FLVL1 FLVL0
Reserved
THL_0
RESETF
FEN2
FEN1
FEN0
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Hand Held Products IT4300 Integration Manual

Type
Integration Manual

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