Page is loading ...
© Freescale Semiconductor, Inc., 2012. All rights reserved.
Freescale Semiconductor
MPC5561RM
Rev. 2.1, 05/2012
This is the MPC5561 Reference Manual set consisting of the following files:
• MPC5561 Reference Manual Addendum, Rev 1
• MPC5561 Reference Manual, Rev 2
MPC5561 Reference Manual
© Freescale Semiconductor, Inc., 2012. All rights reserved.
Freescale Semiconductor
Reference Manual Addendum
MPC5561RMAD
Rev.1, 05/2012
Table of Contents
This errata document describes corrections to the
MPC5561 Microcontroller Reference Manual, order
number MPC5561RM. For convenience, the addenda
items are grouped by revision. Please check our website
at http://www.freescale.com/powerarchitecture for the
latest updates.
The current version available of the MPC5561
Microcontroller Reference Manual is Revision 2.0.
MPC5561 Reference Manual
Addendum
1 Addendum for Revision 2.0. . . . . . . . . . . . . . . . . . 2
2 Revision history. . . . . . . . . . . . . . . . . . . . . . . . . . 12
MPC5561 Reference Manual Addendum, Rev.1
Addendum for Revision 2.0
Freescale Semiconductor2
1 Addendum for Revision 2.0
Table 1. MPC5561RM Rev 2.0 addendum
Location Description
Section 12.4.2.7, “Size,
Alignment, and Packaging
on Transfers”/Page 12-43
Change sentence “The bytes indicated as ‘—’ are not driven during that write cycle” to read “The
bytes indicated as ‘—’ are indeterminate and may be driven during that write cycle.”
Table 12-19, “Data Bus
Contents for Write
Cycles”/Page 12-43
Replace table with the one below to correct information about data bus contents for write cycles.
Note that only two columns have changed: under “32-Bit Port Size,” columns “D0:D7” and
“D8:D15.”
Table 9-23, “DMA Request
Summary for eDMA”/Page
9-42
Change one row in the table to correct information about eSCI COMBTX DMA request. Only the
Transmit Data Register Empty and LIN Transmit Data Ready flags drive the DMA request. The
Transmit Complete flag is not used.
Transfer
Size
TSIZ
[0:1]
1
NOTES:
1
TSIZ is not enabled on the MPC5561.
Address 32-Bit Port Size 16-Bit Port Size
2
2
Also applies when DBM=1 for 16-bit data bus mode.
A30 A31 D0:D7 D8:D15 D16:D23 D24:D31 D0:D7 D8:D15
Byte 01 0 0 OP0 — — — OP0 —
01 0 1 — OP1 — — — OP1
01 1 0 — — OP2 — OP2 —
01 1 1 — — — OP3 — OP3
16-bit 10 0 0 OP0 OP1 — — OP0 OP1
10 1 0 — — OP2 OP3 OP2 OP3
32-bit 00 0 0 OP0 OP1 OP2 OP3 OP0/
OP2
3
3
This case consists of two 16-bit external transactions, the first writing OP0 and OP1,
the second writing OP2 and OP3.
OP1/OP3
DMA Request Channel Source Description
eSCIA_COMBTX 18 ESCIA.SR[TDRE] ||
ESCIA.SR[TC] ||
ESCIA.SR[TXRDY]
eSCIA combined DMA
request of the Transmit
Data Register Empty
and LIN Transmit Data
Ready DMA requests
Addendum for Revision 2.0
MPC5561 Reference Manual Addendum, Rev.1
Freescale Semiconductor 3
Figure 5-2, “Master
Privilege Control
Registers”/Page 5-5
Change read status for bits 16–23 and 28–31 from zero to reserved.
Table A-1, “Module Base
Addresses”/Page A-1
Correct names of peripheral bridge modules by adding underscore (PBRIDGEA becomes
PBRIDGE_A, PBRIDGEB becomes PBRIDGE_B). Only two rows of the table are changed.
Table A-2, “MPC5561
Detailed Register
Map”/Page A-2
Correct names of peripheral bridge A control registers by adding underscore (PBRIDGEA_x
becomes PBRIDGE_A_x).
Table 1. MPC5561RM Rev 2.0 addendum
Location Description
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
MB
W6
MT
R6
MT
W6
MP
L6
W
Reset011 1 01110111011 1
Access Field 4
Access Field 5
Access Field 6
Access Field 7
Module Base Address Page
Peripheral Bridge A (PBRIDGE_A) 0xC3F0_0000 Page A-2
Peripheral Bridge B (PBRIDGE_B) 0xFFF0_0000 Page A-23
Register Description Register Name
Used
Size
Address
Peripheral bridge A master privilege
control register
PBRIDGE_A_MPCR 32-bit Base + 0x0000
Reserved — — Base +
(0x0004-0x001F)
Peripheral bridge A peripheral access
control register 0
PBRIDGE_A_PACR0 32-bit Base + 0x0020
Reserved — — Base +
(0x0024-0x003F)
Peripheral bridge A off-platform
peripheral access control register 0
PBRIDGE_A_OPACR0 32-bit Base + 0x0040
Peripheral bridge A off-platform
peripheral access control register 1
PBRIDGE_A_OPACR1 32-bit Base + 0x0044
Peripheral bridge A off-platform
peripheral access control register 2
PBRIDGE_A_OPACR2 32-bit Base + 0x0048
Reserved — — Base + (0x004C-
0xC3F7_FFFF)
MPC5561 Reference Manual Addendum, Rev.1
Addendum for Revision 2.0
Freescale Semiconductor4
Table A-2, “MPC5561
Detailed Register
Map”/Page A-23
Correct names of peripheral bridge B control registers by adding underscore (PBRIDGEB_x
becomes PBRIDGE_B_x).
Table 1. MPC5561RM Rev 2.0 addendum
Location Description
Register Description Register Name
Used
Size
Address
Peripheral bridge B master privilege
control register
PBRIDGE_B_MPCR 32-bit Base + 0x0000
Reserved — — Base +
(0x0004-0x001F)
Peripheral bridge B peripheral access
control register 0
PBRIDGE_B_PACR0 32-bit Base + 0x0020
Reserved — — Base +
(0x0024-0x0027)
Peripheral bridge B peripheral access
control register 2
PBRIDGE_B_PACR2 32-bit Base + 0x0028
Reserved — — Base +
(0x002C-0x003F)
Peripheral bridge B off-platform
peripheral access control register 0
PBRIDGE_B_OPACR0 32-bit Base + 0x0040
Peripheral bridge B off-platform
peripheral access control register 1
PBRIDGE_B_OPACR1 32-bit Base + 0x0044
Peripheral bridge B off-platform
peripheral access control register 2
PBRIDGE_B_OPACR2 32-bit Base + 0x0048
Peripheral bridge B off-platform
peripheral access control register 3
PBRIDGE_B_OPACR3 32-bit Base + 0x004C
Reserved — — (Base + 0x0050)-
0xFFF0_3FFF)
Addendum for Revision 2.0
MPC5561 Reference Manual Addendum, Rev.1
Freescale Semiconductor 5
Figure 18-10, “Unified
Channel Block
Diagram”/Page 18-22
Reverse the arrow between the "Programmable Filter" and "Edge Detect".
Table 1. MPC5561RM Rev 2.0 addendum
Location Description
MPC5561 Reference Manual Addendum, Rev.1
Addendum for Revision 2.0
Freescale Semiconductor6
Section13.3/ Page 13-4 Remove cross-reference to Table 13-2. Add the following table and update the cross-reference.
Table 1. MPC5561RM Rev 2.0 addendum
Location Description
Addendum for Revision 2.0
MPC5561 Reference Manual Addendum, Rev.1
Freescale Semiconductor 7
Table 18-9/ Page 18-14 Bit 7—DMA: Replace the table that shows the eMIOS channels that don’t support DMA with the
following table.
Section 9.3.1 eDMA
Microarchitecture/ Page
9-32
In the Memory controller sub-bullet, delete the line "The hooks to a BIST controller for the local
TCD memory are included in this module".
Section 9.2.2.13: eDMA
Interrupt Request Register
(EDMA_IRQRL)/ Page 9-19
In the second paragraph, remove the last line "without the need to perform a read-modify-write
sequence to the EDMA_IRQRL".
Table 1. MPC5561RM Rev 2.0 addendum
Location Description
eMIOS Channel DMA = 0 DMA = 1
0 Interrupt DMA request
1 Interrupt DMA request
2 Interrupt DMA request
3 Interrupt DMA request
4 Interrupt DMA request
5 Interrupt Reserved
6 Interrupt Reserved
7 Interrupt Reserved
8 Interrupt DMA request
9 Interrupt DMA request
10 Interrupt Reserved
11 Interrupt Reserved
12 Interrupt Reserved
13 Interrupt Reserved
14 Interrupt Reserved
15 Interrupt Reserved
16 Interrupt Reserved
17 Interrupt Reserved
18 Interrupt Reserved
19 Interrupt Reserved
20 Interrupt Reserved
21 Interrupt Reserved
22 Interrupt Reserved
23 Interrupt Reserved
MPC5561 Reference Manual Addendum, Rev.1
Addendum for Revision 2.0
Freescale Semiconductor8
Section 8.3: Initialization
and Application
Information/Page 8-15
Change the sentence, “There are eight ECC check bits for each 64-bit data doubleword” to the
following:
• SRAM—Eight ECC check bits for each 64-bit SRAM data doubleword.
• Flash—Eight ECC check bits for each 64-bit flash data doubleword.
Figure 11-9, “Synthesizer
Status Register
(FMPLL_SYNSR)”/Page
11-17
Correct the figure to reflect bits 23:28 and bits 30:31 as read-only.
Section 10.3.1.3, “INTC
Interrupt Acknowledge
Register
(INTC_IACKR)”/Page 10-12
Remove the first paragraph from the “Note”:
“The INTC_IACKR must not be read speculatively while in software vector mode. Therefore, for
future compatibility, the TLB entry covering the INTC_IACKR must be configured to be guarded.”
Table 10-3. INTC Memory
Map/Page 10-9
Add the following note at the end of this table:
Note: To ensure compatibility with all PowerPC processors, the TLB entry covering the INTC
memory map must be configured as guarded, both in software and hardware vector modes.
• In software vector mode, the INTC_IACKR must not be read speculatively.
• In hardware vector mode, guarded writes to the INTC_CPR or INTC_EOIR complete before
the interrupt acknowledge signal from the processor asserts.
Table 1. MPC5561RM Rev 2.0 addendum
Location Description
Address:Base + 0x0004 Access: User R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 00 0 000 0 0000
W
Reset0000000 0 000 0 0000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
000000LOLFLOC
MO
DE
PLL
SEL
PLL
REF
LOC
KS
LOC
K
LOC
F
CAL
DO
NE
CAL
PAS
S
W
w1c w1c
Reset000000 0 0 —
1
—
1
—
1
—
1
—
2
000
1
Reset state determined during reset configuration.
2
Reset state determined during reset.
Note: “w1c” signifies that this bit is cleared by writing a 1 to it.
Synthesizer Status Register (FMPLL_SYNSR)
Addendum for Revision 2.0
MPC5561 Reference Manual Addendum, Rev.1
Freescale Semiconductor 9
Table 10-9. MPC5561
interrupt Request
Sources/Page 10-24
Update the note at the end of this table as follows:
Note: The INTC has no spurious vector support. Therefore, if an asserted peripheral or software
settable interrupt request (whose PRI value in INTC_PSRn is higher than the PRI value in
INTC_CPR) negates before the interrupt request to the processor for that peripheral or software
settable interrupt request is acknowledged, the interrupt request to the processor still can assert
or remain asserted for that peripheral or software settable interrupt request. If the interrupt
request to the processor does assert or does remain asserted:
• The interrupt vector will correspond to that peripheral or software settable interrupt request.
• The PRI value in the INTC_CPR will be updated with the corresponding PRI value in
INTC_PSRn.
Furthermore, clearing the peripheral interrupt request's enable bit in the peripheral or,
alternatively, setting its mask bit has the same consequences as clearing its flag bit.Setting its
enable bit or clearing its mask bit while its flag bit is asserted has the same effect on the INTC
as an interrupt event setting the flag bit.
Table A-2. MPC5561
Detailed Register Map/
Page A-40
Remove the Strobe Port Control Register (STBPCR) and mark the row as reserved.
Section 10.4.2.1.4, “Priority
Comparator Submodule”/
Page 10-26
Add the following paragraph to this section:
One consequence of the priority comparator design is that once a higher priority interrupt is
captured, it must be acknowledged by the CPU before a subsequent interrupt request of even
higher priority can be captured. For example, if the CPU is executing a priority level 1 interrupt,
and a priority level 2 interrupt request is captured by the INTC, followed shortly by a priority level
3 interrupt request to the INTC, the level 2 interrupt must be acknowledged by the CPU before a
new level 3 interrupt will be generated.
Table 1. MPC5561RM Rev 2.0 addendum
Location Description
MPC5561 Reference Manual Addendum, Rev.1
Addendum for Revision 2.0
Freescale Semiconductor10
Section 10.5.5.2, “Ensuring
Coherency”/ Page 10-33
Move the content of this section under a new heading Section 10.5.5.2.1, “Interrupt with Blocked
Priority”.
Add the following paragraph to this section:
Section 10.5.5.2.2: Raised Priority Preserved
Before the instruction after the GetResource system service executes, all pending transactions
have completed. These pending transactions can include an ISR for a peripheral or software
settable interrupt request whose priority was equal to or lower than the raised priority. Also,
during the epilog of the interrupt exception handler for this preempting ISR, the raised priority
has been restored from the LIFO to PRI in INTC_CPR. The shared coherent data block now can
be accessed coherently. Following figure shows the timing diagram for this scenario, and the
table explains the events. The example is for software vector mode, but except for the method of
retrieving the vector and acknowledging the interrupt request to the processor, hardware vector
mode is identical.
Raised Priority Preserved Timing Diagram
Table 1. MPC5561RM Rev 2.0 addendum
Location Description
Last In / First Out
Entry in LIFO
Write
INTC_CPR
Clock
Interrupt Request
to Processor
Hardware Vector
Enable
Interrupt
Acknowledge
Interrupt Vector
Read
INTC_IACKR
Write
INTC_EOIR
INTVEC in
INTC_IACKR
PRI in
INTC_CPR
Peripheral Interrupt
Request 100
0
108
1
208
23
Peripheral Interrupt
Request 200
030
3
A
B
C
D
E
F
G
H
I
Addendum for Revision 2.0
MPC5561 Reference Manual Addendum, Rev.1
Freescale Semiconductor 11
Section 10.5.5.2, “Ensuring
Coherency”/ Page 10-33
Section 6.3.1.121 “Pad
Configuration Register 218
(SIU_PCR218)”/Page 6-91
and Page 6-92
• Change PA field from two bits to one bit
• Figure 6-119: Change note 2 to “... set the PA field to 0b0.”
• Table 6-119. PCR218 “PA Field Definition” change as shown below:
0b0 FCK
0b1 AN[15]
Section 19.4.5.4.1
“Calibration Overview”/Page
19-88
Remove the braces from the equation “CAL_RES = GCC x (RAW_RES + OCC + 2)”.
Section 11.3.1.1
“Synthesizer Control
Register
(FMPLL_SYNCR)”/Page
11-14
Changed the last note in PREDIV field description from
“To use the 8–20 MHz OSC, the PLL predivider must be configured for divide-by-two operation
by tying PLLCFG[2] low (set PREDIV to 0b000). To use the 40 MHz OSC, the PLL predivider
must be configured for divide-by-2 operation by setting PLLCFG[2] high (set PREDIV to 0b001).
After reset, PREDIV must not be configured to less than divide-by-2 so long as a 40 MHz crystal
is used.” to
“When using an 8 to 20 MHz reference clock (crystal or external clock), PLLCFG[2] should be
set low for devices that have a PLLCFG[2] pin. This sets the default predivider (PREDIV) to
0b000. To use a crystal or external reference greater than 20 MHz (up to 40 MHz), the PLL
predivider must be configured for divide-by-2 operation by setting PLLCFG[2] high. This sets the
default predivider (PREDIV) to 0b001. After reset, PREDIV must not be configured to a value
less than divide-by-2 (with a 40 MHz crystal/reference).”
Table 1. MPC5561RM Rev 2.0 addendum
Location Description
Raised Priority Preserved Events
Event Description
A Peripheral interrupt request 200 asserts during execution of ISR108 running at
priority 1.
B Interrupt request to processor asserts. INTVEC in INTC_IACKR updates with vector
for that peripheral interrupt request.
C ISR108 writes to INTC_CPR to raise priority to 3 before accessing shared coherent
data block.
D PRI in INTC_CPR now at 3, reflecting the write. This write, just before accessing
data block, is the last instruction the processor executes before being interrupted.
E Interrupt exception handler prolog acknowledges interrupt by reading INTC_IACKR.
F PRI of 3 pushed onto LIFO. PRI in INTC_CPR updates to 2, the priority of ISR208.
G ISR208 clears its flag bit, deasserting its peripheral interrupt request.
H Interrupt exception handler epilog writes to INTC_EOIR.
I LIFO pops 3, restoring the raised priority onto PRI in INTC_CPR. Next value to pop
from LIFO is the priority from before peripheral interrupt request 100 interrupted.
ISR108 now can access data block coherently after interrupt exception handler
executes rfi instruction.
MPC5561 Reference Manual Addendum, Rev.1
Revision history
Freescale Semiconductor12
2 Revision history
Table 2 provides a revision history for this document.
Table 2. Revision history
Revision Substantive changes Date of release
1.0 • Initial release. Corrected errors in chapter 12, “External Bus Interface (EBI).”
• Corrected error in chapter 9, “Enhanced Direct Memory Access (eDMA).”
• Corrected errors in chapter 5, “Peripheral Bridge (PBRIDGE A and PBRIDGE
B).”
• Corrected peripheral bridge name errors in appendix A, “MPC5561 Register
Map.”
• Added the Internal Flash External Emulation Mode table and corrected the
cross-reference to it.
• Corrected the table shown in EMIOS_CCRn: DMA bit description.
• Clarified the description in Section 9.4.1, “eDMA Microarchitecture”.
• Clarified the description in Section 9.3.1.13, “eDMA Interrupt Request
Registers (EDMA_IRQRL).
• Clarified ECC Initialization in Section 8.3: Initialization and Application
Information.
• Clarified note in the INTC Interrupt Acknowledge Register.
• Added a note in the INTC Memory Map table.
• Clarified a note at the end of the MPC5561 Interrupt Request Sources table.
• Updated Table A-2: MPC5561 Detailed Register Map.
• Corrected unified channel block diagram in chapter 18, “Enhanced Modular
Input/Output Subsystem (eMIOS).”
• Added a paragraph to the Section 10.4.2.1.4, “Priority Comparator
Submodule”.
• Updated Section 10.5.5.2, “Ensuring Coherency”.
• Corrected table “PCR218 PA Field Definition” and figure “AN[15]_FCK Pad
Configuration Register (SIU_PCR218)” and note 2 under figure.
• Updated the last note in PREDIV field description of Synthesizer Control
Register (FMPLL_SYNCR).
05/2012
How to Reach Us:
Home Page:
www.freescale.com
Web Support:
http://www.freescale.com/support
USA/Europe or Locations Not Listed:
Freescale Semiconductor, Inc.
Technical Information Center, EL516
2100 East Elliot Road
Tempe, Arizona 85284
+1-800-521-6274 or +1-480-768-2130
www.freescale.com/support
Europe, Middle East, and Africa:
Freescale Halbleiter Deutschland GmbH
Technical Information Center
Schatzbogen 7
81829 Muenchen, Germany
+44 1296 380 456 (English)
+46 8 52200080 (English)
+49 89 92103 559 (German)
+33 1 69 35 48 48 (French)
www.freescale.com/support
Japan:
Freescale Semiconductor Japan Ltd.
Headquarters
ARCO Tower 15F
1-8-1, Shimo-Meguro, Meguro-ku,
Tokyo 153-0064
Japan
0120 191014 or +81 3 5437 9125
suppor[email protected]
Asia/Pacific:
Freescale Semiconductor China Ltd.
Exchange Building 23F
No. 118 Jianguo Road
Chaoyang District
Beijing 100022
China
+86 10 5879 8000
suppor[email protected]
For Literature Requests Only:
Freescale Semiconductor Literature Distribution Center
1-800-441-2447 or 303-675-2140
Fax: 303-675-2150
LDCForFreescaleSemiconductor@hibbertgroup.com
Information in this document is provided solely to enable system and
software implementers to use Freescale Semiconductor products. There are
no express or implied copyright licenses granted hereunder to design or
fabricate any integrated circuits or integrated circuits based on the
information in this document.
Freescale Semiconductor reserves the right to make changes without further
notice to any products herein. Freescale Semiconductor makes no warranty,
representation or guarantee regarding the suitability of its products for any
particular purpose, nor does Freescale Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation consequential or
incidental damages. “Typical” parameters that may be provided in Freescale
Semiconductor data sheets and/or specifications can and do vary in different
applications and actual performance may vary over time. All operating
parameters, including “Typicals”, must be validated for each customer
application by customer’s technical experts. Freescale Semiconductor does
not convey any license under its patent rights nor the rights of others.
Freescale Semiconductor products are not designed, intended, or authorized
for use as components in systems intended for surgical implant into the body,
or other applications intended to support or sustain life, or for any other
application in which the failure of the Freescale Semiconductor product could
create a situation where personal injury or death may occur. Should Buyer
purchase or use Freescale Semiconductor products for any such unintended
or unauthorized application, Buyer shall indemnify and hold Freescale
Semiconductor and its officers, employees, subsidiaries, affiliates, and
distributors harmless against all claims, costs, damages, and expenses, and
reasonable attorney fees arising out of, directly or indirectly, any claim of
personal injury or death associated with such unintended or unauthorized
use, even if such claim alleges that Freescale Semiconductor was negligent
regarding the design or manufacture of the part.
Freescale™ and the Freescale logo are trademarks of Freescale
Semiconductor, Inc. All other product or service names are the property
of their respective owners.© Freescale Semiconductor, Inc. 2012. All rights
reserved.
MPC5561RMAD
Rev.1
05/2012
MPC5561 Microcontroller Reference
Manual
Devices Supported:
MPC5561
MPC5561 RM
Rev. 2.0
30 May 2008
gggggggggggggggg
Information in this document is provided solely to enable system and
software implementers to use Freescale Semiconductor products. There are
no express or implied copyright licenses granted hereunder to design or
fabricate any integrated circuits or integrated circuits based on the
information in this document.
Freescale Semiconductor reserves the right to make changes without further
notice to any products herein. Freescale Semiconductor makes no warranty,
representation or guarantee regarding the suitability of its products for any
particular purpose, nor does Freescale Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation consequential or
incidental damages. “Typical” parameters that may be provided in Freescale
Semiconductor data sheets and/or specifications can and do vary in different
applications and actual performance may vary over time. All operating
parameters, including “Typicals”, must be validated for each customer
application by customer’s technical experts. Freescale Semiconductor does
not convey any license under its patent rights nor the rights of others.
Freescale Semiconductor products are not designed, intended, or authorized
for use as components in systems intended for surgical implant into the body,
or other applications intended to support or sustain life, or for any other
application in which the failure of the Freescale Semiconductor product could
create a situation where personal injury or death may occur. Should Buyer
purchase or use Freescale Semiconductor products for any such unintended
or unauthorized application, Buyer shall indemnify and hold Freescale
Semiconductor and its officers, employees, subsidiaries, affiliates, and
distributors harmless against all claims, costs, damages, and expenses, and
reasonable attorney fees arising out of, directly or indirectly, any claim of
personal injury or death associated with such unintended or unauthorized
use, even if such claim alleges that Freescale Semiconductor was negligent
regarding the design or manufacture of the part.
Freescale™ and the Freescale logo are trademarks of Freescale
Semiconductor, Inc. All other product or service names are the property
of their respective owners.© Freescale Semiconductor, Inc. 2008. All rights
reserved.
MPC5561 RM
Rev. 2.0
30 May 2008
How to Reach Us:
Home Page:
www.freescale.com
E-mail:
suppor[email protected]
USA/Europe or Locations Not Listed:
Freescale Semiconductor
Technical Information Center, CH370
1300 N. Alma School Road
Chandler, Arizona 85224
+1-800-521-6274 or +1-480-768-2130
suppor[email protected]
Europe, Middle East, and Africa:
Freescale Halbleiter Deutschland GmbH
Technical Information Center
Schatzbogen 7
81829 Muenchen, Germany
+44 1296 380 456 (English)
+46 8 52200080 (English)
+49 89 92103 559 (German)
+33 1 69 35 48 48 (French)
suppor[email protected]
Japan:
Freescale Semiconductor Japan Ltd.
Headquarters
ARCO Tower 15F
1-8-1, Shimo-Meguro, Meguro-ku,
Tokyo 153-0064, Japan
0120 191014 or +81 3 5437 9125
suppor[email protected]
Asia/Pacific:
Freescale Semiconductor Hong Kong Ltd.
Technical Information Center
2 Dai King Street
Tai Po Industrial Estate
Tai Po, N.T., Hong Kong
+800 26668334
suppor[email protected]
For Literature Requests Only:
Freescale Semiconductor Literature Distribution Center
P.O. Box 5405
Denver, Colorado 80217
1-800-441-2447 or 303-675-2140
Fax: 303-675-2150
LDCForFreescaleSemiconductor@hibbertgroup.com
gggggggggggggggg
MPC5561 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor i
Chapter 1
Introduction
1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.4 MPC5500 Family Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.5 Detailed Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.5.1 e200z6 Core Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.5.2 System Bus Crossbar Switch (XBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.5.3 Enhanced Direct Memory Access (eDMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.5.4 Interrupt Controller (INTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.5.5 Frequency Modulated Phase-Locking Loop (FMPLL) . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.5.6 External Bus Interface (EBI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.5.7 System Integration Unit (SIU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.5.8 Error Correction Status Module (ECSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.5.9 Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.5.10 Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.5.11 Static RAM (SRAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.5.12 Boot Assist Module (BAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.5.13 Enhanced Management Input/Output System (eMIOS) . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.5.14 Enhanced Queued A/D Converter (eQADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.5.15 Parallel Digital Interface (PDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.5.16 Deserial/Serial Peripheral Interface (DSPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.5.17 Enhanced Serial Communications Interface (eSCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.5.18 Flexible Controller Area Network (FlexCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.5.19 Nexus Development Interface (NDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.5.20 JTAG Controller (JTAGC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.5.21 Dual Channel FlexRay Controller (FLEXRAY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.6 MPC5500 Family Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.7 Memory Map for Multi-Master Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Chapter 2
Signal Description
2.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2.2 External Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2.1 Multiplexed Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2.2 324 Package Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2.3 Device Signals Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.3 Detailed Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.1 Reset and Configuration Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.2 External Bus Interface (EBI) Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.3 Nexus Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3.4 JTAG Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3.5 Flexible Controller Area Network (FlexCAN) Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.3.6 Enhanced Serial Communications Interface (eSCI) Signals . . . . . . . . . . . . . . . . . . . . . 20
2.3.7 Deserial/Serial Peripheral Interface (DSPI) Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.3.8 Enhanced Queued A/D Controller (eQADC) Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.3.9 External Interrupt Requests (IRQs) and Parallel Digital Interface (PDI) Signals . . . . . . 24
2.3.10 Enhanced Management Input/Output System (eMIOS) Signals . . . . . . . . . . . . . . . . . . 27
2.3.11 General Purpose Input/Output (GPIO) Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.3.12 Clock Synthesizer Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.3.13 Power and Ground Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.3.14 I/O Power and Ground Segmentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.4 eMIOS Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
gggggggggggggggg
MPC5561 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor ii
Chapter 3
e200z6 Core Complex
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.1.3.1 Instruction Unit Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.1.3.2 Integer Unit Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.1.3.3 Load/Store Unit Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.1.3.4 MMU Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1.3.5 L1 Cache Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1.3.6 BIU Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1.4 Microarchitecture Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2 Core Registers and Programmer’s Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.2.1 Power Architecture Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2.1.1 User-Level Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2.1.2 Supervisor-Level Only Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2.2 Core-Specific Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2.2.1 User-Level Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2.2.2 Supervisor-Level Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2.3 e200z6 Core Complex Features Not Supported in the Device . . . . . . . . . . . . . . . . . . . . 13
3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3.1 Memory Management Unit (MMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3.1.1 Translation Lookaside Buffer (TLB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3.1.2 Translation Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3.1.3 Effective to Real Address Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3.1.4 Permissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3.1.5 MMU Assist Registers (MAS[0]–MAS[4], MAS[6]) . . . . . . . . . . . . . . . . . . . . 17
3.3.1.5.1 MAS[0] Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3.1.5.2 MAS[1] Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.3.1.5.3 MAS[2] Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.3.1.5.4 MAS[3] Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.3.1.5.5 MAS[4] Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.3.1.5.6 MAS[6] Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.3.2 L1 Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.3.2.1 Cache Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.3.2.2 Cache Lookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.3.2.3 Cache Line Replacement Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.3.2.4 Cache Power Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.3.2.5 L1 Cache Control and Status Register 0 (L1CSR0) . . . . . . . . . . . . . . . . . . 26
3.3.2.6 L1 Cache Configuration Register 0 (L1CFG0) . . . . . . . . . . . . . . . . . . . . . . . 29
3.3.3 Interrupt Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.3.4 Bus Interface Unit (BIU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
3.3.5 Timer Facilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.3.6 Signal Processing Extension APU (SPE APU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.3.7 SPE Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.4 External References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.5 Power Architecture Instruction Extensions – VLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
gggggggggggggggg
MPC5561 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor iii
Chapter 4
Reset
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
4.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
4.2.1 Reset Input (RESET
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
4.2.2 Reset Output (RSTOUT
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
4.2.3 Reset Configuration (RSTCFG
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
4.2.4 Weak Pull Configuration (WKPCFG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
4.2.5 Boot Configuration (BOOTCFG[0:1]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
4.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
4.3.1 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
4.3.1.1 Reset Status Register (SIU_RSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
4.3.1.2 System Reset Control Register (SIU_SRCR) . . . . . . . . . . . . . . . . . . . . . . . . 5
4.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.4.1 Reset Vector Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.4.2 Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.4.2.1 FMPLL Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.4.2.2 Flash High Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.4.2.3 Reset Source Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.4.2.3.1 Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.4.2.3.2 External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.4.2.3.3 Loss-of-Lock Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.4.2.3.4 Loss-of-Clock Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.4.2.3.5 Watchdog Timer/Debug Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.4.2.3.6 Checkstop Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.4.2.3.7 JTAG Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.4.2.3.8 Software System Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.4.2.3.9 Software External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.4.3 Reset Configuration and Configuration Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.4.3.1 RSTCFG
Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.4.3.2 WKPCFG Pin (Reset Weak Pullup/Pulldown Configuration) . . . . . . . . . . . 12
4.4.3.3 BOOTCFG[0:1] Pins (MCU Configuration) . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.4.3.4 PLLCFG[0:1] Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.4.3.5 Reset Configuration Halfword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.4.3.5.1 Reset Configuration Halfword Definition . . . . . . . . . . . . . . . . . . . 13
4.4.3.5.2 Invalid RCHW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.4.3.5.3 Reset Configuration Halfword Source . . . . . . . . . . . . . . . . . . . . . 15
4.4.4 Reset Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.4.5 Reset Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Chapter 5
Peripheral Bridge (PBRIDGE A and PBRIDGE B)
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
5.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
5.1.2 Access Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
5.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
5.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
5.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
5.3 Memory Map and Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
5.3.1 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
5.3.1.1 Master Privilege Control Register (PBRIDGE_x_MPCR) . . . . . . . . . . . . . . . 5
5.3.1.2 Peripheral Access Control Registers (PBRIDGE_x_PACR) and Off-Platform
Peripheral Access Control Registers (PBRIDGE_x_OPACR) . . . . . . . . . . . 7
gggggggggggggggg
MPC5561 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor iv
5.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.4.1 Access Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.4.2 Peripheral Write Buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.4.2.1 Read Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.4.2.2 Write Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.4.2.3 Buffered Write Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.4.3 General Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Chapter 6
System Integration Unit (SIU)
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
6.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
6.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
6.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
6.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
6.2.1 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
6.2.1.1 Reset Input (RESET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
6.2.1.2 Reset Output (RSTOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
6.2.1.3 General-Purpose I/O (GPIO[0:213]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
6.2.1.4 Boot Configuration (BOOTCFG[0:1]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
6.2.1.5 I/O Weak Pullup Reset Configuration (WKPCFG) . . . . . . . . . . . . . . . . . . . . 6
6.2.1.6 External Interrupt Request Input (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
6.2.1.6.1 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
6.2.1.6.2 DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
6.2.1.6.3 Overruns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
6.2.1.6.4 Edge-Detect Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
6.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6.3.1 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6.3.1.1 MCU ID Register (SIU_MIDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6.3.1.2 Reset Status Register (SIU_RSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6.3.1.3 System Reset Control Register (SIU_SRCR) . . . . . . . . . . . . . . . . . . . . . . . 15
6.3.1.4 External Interrupt Status Register (SIU_EISR) . . . . . . . . . . . . . . . . . . . . . . 16
6.3.1.5 DMA/Interrupt Request Enable Register (SIU_DIRER) . . . . . . . . . . . . . . . 17
6.3.1.6 DMA/Interrupt Request Select Register (SIU_DIRSR) . . . . . . . . . . . . . . . . 17
6.3.1.7 Overrun Status Register (SIU_OSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3.1.8 Overrun Request Enable Register (SIU_ORER) . . . . . . . . . . . . . . . . . . . . . 19
6.3.1.9 IRQ Rising-Edge Event Enable Register (SIU_IREER) . . . . . . . . . . . . . . . 20
6.3.1.10 IRQ Falling-Edge Event Enable Register (SIU_IFEER) . . . . . . . . . . . . . . . 20
6.3.1.11 IRQ Digital Filter Register (SIU_IDFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.3.1.12 Pad Configuration Registers (SIU_PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.3.1.13 Pad Configuration Register 0 (SIU_PCR0) . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.3.1.14 Pad Configuration Registers 1–3 (SIU_PCR1–SIU_PCR3) . . . . . . . . . . . . 25
6.3.1.15 Pad Configuration Registers 4–7 (SIU_PCR4–SIU_PCR7) . . . . . . . . . . . . 26
6.3.1.16 Pad Configuration Registers 8–22 (SIU_PCR8–SIU_PCR22) . . . . . . . . . . 26
6.3.1.17 Pad Configuration Registers 23–25 (SIU_PCR23–SIU_PCR25) . . . . . . . . 27
6.3.1.18 Pad Configuration Registers 26–27 (SIU_PCR26–SIU_PCR27) . . . . . . . . 28
6.3.1.19 Pad Configuration Registers 28–43 (SIU_PCR28–SIU_PCR43) . . . . . . . . 28
6.3.1.20 Pad Configuration Registers 44–48 (SIU_PCR44–SIU_PCR48) . . . . . . . . 29
6.3.1.21 Pad Configuration Registers 49 (SIU_PCR49) . . . . . . . . . . . . . . . . . . . . . . 29
6.3.1.22 Pad Configuration Registers 50 (SIU_PCR50) . . . . . . . . . . . . . . . . . . . . . . 30
6.3.1.23 Pad Configuration Registers 51 (SIU_PCR51) . . . . . . . . . . . . . . . . . . . . . . 31
6.3.1.24 Pad Configuration Registers 52 (SIU_PCR52) . . . . . . . . . . . . . . . . . . . . . . 31
6.3.1.25 Pad Configuration Registers 53 (SIU_PCR53) . . . . . . . . . . . . . . . . . . . . . . 32
6.3.1.26 Pad Configuration Registers 54 (SIU_PCR54) . . . . . . . . . . . . . . . . . . . . . . 33
gggggggggggggggg
/
