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Document Number: MCIMX27RM
Rev. 0.4
06/2012
MCIMX27 Applications Processor Reference Manual, Rev. 0.4
Freescale Semiconductor iii
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Co nt ents
Chapter 1
Introduction to the i.MX27 Multimedia Applications Processor
1.1 i.MX27 Applications Processor Block Diagram ............................................................. 1-2
1.2 Summary of Core and Modules ....................................................................................... 1-2
1.2.1 ARM9™ Platform ....................................................................................................... 1-2
1.2.2 System Control ............................................................................................................ 1-4
1.2.2.1 Clock Controller Module (CCM) ............................................................................ 1-4
1.2.2.2 JTAG Controller (JTAGC) ....................................................................................... 1-4
1.2.3 Standard System Resources......................................................................................... 1-4
1.2.3.1 General Purpose Timer (GPT) ................................................................................. 1-5
1.2.3.2 Pulse-Width Modulator (PWM) .............................................................................. 1-5
1.2.3.3 Real Time Clock (RTC)........................................................................................... 1-5
1.2.3.4 Watchdog Timer Module (WDOG) ......................................................................... 1-5
1.2.3.5 General-Purpose I/O Ports (GPIO).......................................................................... 1-6
1.2.3.6 Direct Memory Access Controller (DMAC) ........................................................... 1-6
1.2.4 Power Management and Backup Modes...................................................................... 1-6
1.2.4.1 SCC, RTC, and Oscillator Power Supply ................................................................ 1-6
1.2.4.2 Enter/Exit Mode....................................................................................................... 1-7
1.2.4.3 Reset Strategy ..................................................................................................... 1-7
1.2.5 System Security ........................................................................................................... 1-7
1.2.5.1 Security Controller Module (SCC).......................................................................... 1-7
1.2.5.2 Symmetric/Asymmetric Hashing and Random Accelerator (SAHARA2) ............. 1-7
1.2.5.3 Run-Time Integrity Checkers (RTIC)...................................................................... 1-8
1.2.5.4 IC Identification Module (IIM)................................................................................ 1-8
1.2.6 Connectivity................................................................................................................. 1-9
1.2.6.1 Configurable Serial Peripheral Interfaces (CSPI).................................................... 1-9
1.2.6.2 Inter-IC Connectivity (I
2
C) Bus Module ............................................................... 1-10
1.2.6.3 Synchronous Serial Interface (SSI) ....................................................................... 1-10
1.2.6.4 Bus Control ............................................................................................................ 1-10
1.2.6.4.1 AHB-Lite IP Interface Module (AIPI) .............................................................. 1-11
1.2.6.4.2 ARM926EJ-S Interrupt Controller (AITC) ....................................................... 1-11
1.2.6.4.3 Intellectual Property Bus Multiplexer (IPMUX)............................................... 1-11
1.2.6.4.4 Multi-Layer AHB Crossbar Switch (MAX)...................................................... 1-11
1.2.7 Wireline Connectivity................................................................................................ 1-11
1.2.7.1 Universal Asynchronous Receiver/Transmitter (UART)....................................... 1-11
1.2.7.2 High Speed USB 2.0 Interface (USB) ................................................................... 1-12
1.2.7.3 1-Wire Interface (1-Wire) ...................................................................................... 1-12
1.2.7.4 Advanced Technology Attachment (ATA)............................................................. 1-12
1.2.7.5 Fast Ethernet Controller (FEC).............................................................................. 1-12
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1.2.8 External Memory Interface........................................................................................ 1-13
1.2.8.1 Multi-Master Memory Interface (M3IF) ............................................................... 1-13
1.2.8.2 SDRAM Controller (SDRAMC) ........................................................................... 1-14
1.2.8.3 NAND Flash Controller (NFC) ............................................................................. 1-15
1.2.8.4 Personal Computer Memory Card International Association (PCMCIA)............. 1-15
1.2.8.5 External Interface Module (EIM) .......................................................................... 1-16
1.2.9 Memory Expansion.................................................................................................... 1-16
1.2.9.1 Memory Stick Host Controller (MSHC) ............................................................... 1-16
1.2.9.2 Secured Digital Host Controller (SDHC) .............................................................. 1-17
1.2.10 Video Codec and enhanced Multimedia Accelerator Lite (eMMA_lt) ..................... 1-17
1.2.10.1 Video Codec........................................................................................................... 1-17
1.2.10.2 enhanced Multimedia Accelerator Lite (eMMA_lt).............................................. 1-19
1.2.10.2.1 Image Pre-Processor (PrP)................................................................................. 1-20
1.2.10.2.2 Post-Processor (PP) ........................................................................................... 1-21
1.2.10.3 Digital Audio Multiplexer (AUDMUX) ................................................................ 1-22
1.2.11 MultiMedia Interface ................................................................................................. 1-23
1.2.11.1 CMOS Sensor Interface (CSI) ............................................................................... 1-23
1.2.12 Human Interface ........................................................................................................ 1-23
1.2.12.1 Liquid Crystal Display Controller (LCDC)........................................................... 1-24
1.2.12.2 Smart Liquid Crystal Display Controller (SLCDC) .............................................. 1-24
1.2.12.3 Keypad Port (KPP) ................................................................................................ 1-25
1.2.13 Packaging Information............................................................................................... 1-25
Chapter 2
System Memory and Register Map
2.1 Introduction...................................................................................................................... 2-1
2.2 Memory Space .................................................................................................................2-1
2.2.1 Detailed Memory Map................................................................................................. 2-1
2.3 Register Map .................................................................................................................... 2-7
Chapter 3
Clocks, Power Management, and Reset Control
3.1 Introduction...................................................................................................................... 3-1
3.2 Clock Controller Architecture Block Diagram ................................................................ 3-1
3.2.1 High Frequency Clock Source and Distribution.......................................................... 3-4
3.2.2 Output Frequency Calculations ................................................................................... 3-5
3.3 Power Management ......................................................................................................... 3-5
3.3.1 PLL Operation at Power-Up ........................................................................................ 3-5
3.3.2 PLL Operation at Wake-Up ......................................................................................... 3-5
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3.3.3 i.MX27 Processor Low-Power Modes......................................................................... 3-5
3.3.3.1 Doze Mode............................................................................................................... 3-6
3.3.3.2 Sleep Mode .............................................................................................................. 3-6
3.3.4 SDRAM Power Modes ................................................................................................ 3-8
3.3.5 Power Management in the PLL Clock Controller ....................................................... 3-8
3.3.6 Power Management Using Frequency Control............................................................ 3-8
3.4 Memory Map and Register Definition ............................................................................. 3-9
3.4.1 Register Summary........................................................................................................ 3-9
3.4.2 Clock Source Control Register (CSCR) .................................................................... 3-10
3.4.3 MPLL Control Register 0 (MPCTL0) ....................................................................... 3-13
3.4.4 MCU and System PLL Control Register 1 (MPCTL1) ............................................. 3-15
3.4.5 Programming the Serial Peripheral PLL (SPLL)....................................................... 3-16
3.4.6 SPLL Control Register 0 (SPCTL0).......................................................................... 3-17
3.4.7 SPLL Control Register 1 (SPCTL1).......................................................................... 3-19
3.4.8 Oscillator 26M Register............................................................................................. 3-20
3.4.8.1 Adjusting the 26 MHz Oscillator Trim.................................................................. 3-20
3.4.9 Peripheral Clock Divider Register 0 (PCDR0).......................................................... 3-21
3.4.10 Peripheral Clock Divider Register 1 (PCDR1).......................................................... 3-23
3.4.11 Peripheral Clock Control Register 0 (PCCR0) .......................................................... 3-25
3.4.12 Peripheral Clock Control Register 1 (PCCR1) .......................................................... 3-28
3.4.13 Clock Control Status Register (CCSR)...................................................................... 3-31
3.4.14 Wakeup Guard Mode Control Register (WKGDCTL) .............................................. 3-33
3.5 Functional Description of the Reset Module ................................................................. 3-34
3.5.1 Global Reset...............................................................................................................3-34
3.5.2 ARM9 Platform Reset ............................................................................................... 3-36
Chapter 4
System Control
4.1 Introduction...................................................................................................................... 4-1
4.2 Memory Map and Register Definition ............................................................................. 4-1
4.2.1 Chip ID Register (CID)................................................................................................ 4-3
4.2.2 Function Multiplexing Control Register (FMCR) ....................................................... 4-4
4.2.3 Global Peripheral Control Register (GPCR) ............................................................... 4-7
4.2.4 Well Bias System ......................................................................................................... 4-8
4.2.5 Well Bias Control Register (WBCR)........................................................................... 4-9
4.2.6 Drive Strength Control Register 1 (DSCR1) ............................................................. 4-11
4.2.7 Drive Strength Control Register 2 (DSCR2) ............................................................. 4-13
4.2.8 Drive Strength Control Register 3 ............................................................................. 4-15
4.2.9 Drive Strength Control Register 4 ............................................................................. 4-17
4.2.10 Drive Strength Control Register 5 ............................................................................. 4-19
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4.2.11 Drive Strength Control Register 6 ............................................................................. 4-21
4.2.12 Drive Strength Control Register 7 ............................................................................. 4-24
4.2.13 Drive Strength Control Register 8 ............................................................................. 4-26
4.2.14 Drive Strength Control Register 9 ............................................................................. 4-28
4.2.15 Drive Strength Control Register 10 ........................................................................... 4-31
4.2.16 Drive Strength Control Register 11 ........................................................................... 4-33
4.2.17 Drive Strength Control Register 12 ........................................................................... 4-35
4.2.18 Drive Strength Control Register 13 ........................................................................... 4-37
4.2.19 Pull Strength Control Register (PSCR) ..................................................................... 4-39
4.2.20 Priority Control and Select Register (PCSR)............................................................. 4-41
4.2.21 Power Management Control Register (PMCR) ......................................................... 4-42
4.2.22 DPTC Comparator Value Register 0 (DCVR0) ......................................................... 4-44
4.2.23 DPTC Comparator Value Register 1 (DCVR1) ......................................................... 4-44
4.2.24 DPTC Comparator Value Register 2.......................................................................... 4-45
4.2.25 DPTC Comparator Value Register 3.......................................................................... 4-46
4.2.26 PMIC Pad Control Register (PPCR).......................................................................... 4-46
4.3 System Boot Mode Selection......................................................................................... 4-47
Chapter 5
Signal Descriptions and Pin Assignments
5.1 Introduction...................................................................................................................... 5-1
5.2 Signal Descriptions ..........................................................................................................5-1
5.3 I/O Power Supply and Signal Multiplexing Scheme ....................................................... 5-9
5.3.1 Pull/Pull Strength/Open Drain Descriptions.............................................................. 5-10
5.3.2 GPIO Default and Pull-Up Configuration ................................................................. 5-10
5.3.3 I/O Mode and Supply Level....................................................................................... 5-10
Chapter 6
General-Purpose I/O (GPIO)
6.1 Introduction...................................................................................................................... 6-1
6.2 Overview.......................................................................................................................... 6-3
6.3 GPIO Features.................................................................................................................. 6-3
6.4 External Signals Description ........................................................................................... 6-4
6.5 Interrupts .......................................................................................................................... 6-4
6.6 Memory Map and Register Definitions ........................................................................... 6-4
6.6.1 Register Summary........................................................................................................ 6-8
6.6.2 Data Direction Register (PTn_DDIR) ......................................................................... 6-9
6.6.3 Output Configuration Register 1 (OCR1).................................................................. 6-10
6.6.4 Output Configuration Register 2 (OCR2).................................................................. 6-11
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6.6.5 Input Configuration Register A1 (ICONFA1) ........................................................... 6-12
6.6.6 Input Configuration Register A2 (ICONFA2) ........................................................... 6-13
6.6.7 Input Configuration Register B1 (ICONFB1) ........................................................... 6-14
6.6.8 Input Configuration Register B2 (ICONFB2) ........................................................... 6-15
6.6.9 Data Register (DR) .................................................................................................... 6-16
6.6.10 GPIO IN USE Registers (GIUS) ............................................................................... 6-17
6.6.11 GPIO IN USE Register Reset Values ........................................................................ 6-17
6.6.11.1 GPIO IN USE Register A (PTA_GIUS)................................................................ 6-18
6.6.11.2 GPIO IN USE Register B (PTB_GIUS)................................................................ 6-18
6.6.11.3 GPIO IN USE Register C (PTC_GIUS)................................................................ 6-19
6.6.11.4 GPIO IN USE Register D (PTD_GIUS) ............................................................... 6-19
6.6.11.5 GPIO IN USE Register E (PTE_GIUS) ................................................................ 6-20
6.6.11.6 GPIO IN USE Register F (PTF_GIUS)................................................................. 6-20
6.6.12 Sample Status Register (SSR).................................................................................... 6-21
6.6.13 Interrupt Configuration Register 1 (ICR1) ................................................................ 6-22
6.6.14 Interrupt Configuration Register 2 (ICR2) ................................................................ 6-23
6.6.15 Interrupt Mask Register (IMR) .................................................................................. 6-24
6.6.16 Interrupt Status Register (ISR) .................................................................................. 6-25
6.6.17 General Purpose Register (GPR) ............................................................................... 6-26
6.6.18 Software Reset Register (SWR)................................................................................. 6-27
6.6.19 Pull-Up Enable Register (PUEN) .............................................................................. 6-28
6.6.20 Port Interrupt Mask Register (PMASK) .................................................................... 6-29
Chapter 7
JTAG Controller (JTAGC)
7.1 Introduction...................................................................................................................... 7-1
7.2 Features............................................................................................................................ 7-1
7.3 Implementation ................................................................................................................ 7-1
7.4 JTAG Controller Pin List ................................................................................................. 7-2
7.5 JTAG Overview................................................................................................................7-3
7.6 JTAG Modes .................................................................................................................... 7-3
7.6.1 ARM926 Platform mode ............................................................................................ 7-3
7.6.2 i.MX27 JTAG Controller mode .................................................................................. 7-3
7.7 Boundary Scan Register................................................................................................... 7-3
7.8 Instruction Register.......................................................................................................... 7-4
7.8.1 EXTEST Instruction .................................................................................................... 7-4
7.8.2 SAMPLE/PRELOAD Instruction................................................................................ 7-4
7.8.3 IDCODE Instruction .................................................................................................... 7-5
7.8.4 ENABLE_ExtraDebug Instruction .............................................................................. 7-5
7.8.5 HIGHZ Instruction....................................................................................................... 7-5
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7.8.6 CLAMP Instruction ..................................................................................................... 7-6
7.8.7 BYPASS Instruction .................................................................................................... 7-6
7.9 TMS Sequences ............................................................................................................... 7-6
7.9.1 TMS Sequence to Check ID Code............................................................................... 7-6
7.9.2 TMS Sequence to Write to ExtraDebug Register ........................................................ 7-7
7.9.3 TMS Sequence to Read ExtraDebug Register............................................................. 7-8
7.10 i.MX27 JTAG Restrictions............................................................................................... 7-8
Chapter 8
Bootstrap Mode Operation
8.1 Introduction...................................................................................................................... 8-1
8.2 UART/USB Configuration............................................................................................... 8-1
8.3 Enter Bootstrap Mode Configuration............................................................................... 8-1
8.4 Bootstrap Flow................................................................................................................. 8-2
8.4.1 Bootstrap Protocol and Definition ............................................................................... 8-3
8.4.1.1 Synchronization Operation ...................................................................................... 8-3
8.4.1.2 Write Register Operation ......................................................................................... 8-3
8.4.1.3 Download Operation................................................................................................ 8-4
8.4.1.4 Bootstrap End Indication Operation ........................................................................ 8-5
Chapter 9
ARM9 Platform
9.1 Introduction.................................................................................................................... 10-1
9.1.1 Design Methodology Summary ................................................................................. 10-2
9.1.2 Performance Characteristics ...................................................................................... 10-3
9.1.2.1 Performance Target................................................................................................ 10-3
9.2 ARM9 Platform Sub-Modules....................................................................................... 10-3
9.2.1 ARM926EJ-S Processor ............................................................................................ 10-3
9.2.1.1 ARM926EJ-S Co-Processor Interface ................................................................... 10-3
9.2.1.2 TCM Interfaces...................................................................................................... 10-4
9.2.2 ARM9 Embedded Trace Macrocell and Embedded Trace Buffer............................. 10-4
9.2.3 The 6 x 3 Multi-Layer AHB Crossbar Switch (MAX).............................................. 10-4
9.2.3.1 MAX Configuration Registers............................................................................... 10-4
9.2.3.2 Master Ports ........................................................................................................... 10-5
9.2.3.3 Slave Ports ............................................................................................................. 10-5
9.2.3.4 Debug Support ....................................................................................................... 10-5
9.2.4 ARM Interrupt Controller (AITC)............................................................................. 10-5
9.2.5 Memory Controller and BIST Engine (MCTL)......................................................... 10-6
9.2.5.1 RAM ...................................................................................................................... 10-6
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9.2.5.2 ROM ...................................................................................................................... 10-6
9.2.6 AHB IP Bus Interface (AIPI)..................................................................................... 10-7
9.2.7 PAHBMUX–Primary AHB Mux............................................................................... 10-7
9.2.8 ROMPATCH .............................................................................................................. 10-7
9.2.8.1 External Boot ......................................................................................................... 10-7
9.2.9 Clock Control Module (CLKCTL)............................................................................ 10-8
9.2.10 JAM............................................................................................................................ 10-8
9.2.11 Test Wrapper.............................................................................................................. 10-9
9.3 ARM9 Platform Hierarchy ............................................................................................ 10-9
9.4 JTAG ID Register......................................................................................................... 10-10
9.5 System Memory Map................................................................................................... 10-10
9.5.1 ARM9 Platform Memory Map ................................................................................ 10-10
9.5.2 External Peripheral Space........................................................................................ 10-11
9.5.3 External Boot ........................................................................................................... 10-11
9.5.4 Memory Map Considerations .................................................................................. 10-12
9.6 Platform Clocking........................................................................................................ 10-12
9.6.1 ARM926EJ-S Clock Considerations ....................................................................... 10-12
9.6.2 ARM926EJ-S JTAG Port Clocking Considerations ................................................ 10-14
9.6.2.1 JTAG_TCK .......................................................................................................... 10-14
9.6.3 External Alternate Bus Master Interfaces................................................................ 10-14
9.6.4 External Secondary AHB Ports ............................................................................... 10-14
9.7 Platform Resets ............................................................................................................ 10-15
9.7.1 HRESET .................................................................................................................. 10-15
9.7.2 POR and JTAG_TRST............................................................................................. 10-15
9.8 Power Management ..................................................................................................... 10-16
9.8.1 Register Level Clock Gating.................................................................................... 10-16
9.8.2 Block Level Clock Gating ....................................................................................... 10-16
9.8.3 External Clock Gating ............................................................................................. 10-16
9.8.4 Well Biasing............................................................................................................. 10-17
9.9 Platform AHB Interfaces ............................................................................................. 10-18
9.9.1 Definition of AHB-Lite ........................................................................................... 10-18
9.9.2 Alternate Bus Master Ports ...................................................................................... 10-18
9.9.3 Single Master Seamless Connection to ABM Port.................................................. 10-19
9.9.4 Multiple External Masters Connection to ABM Port .............................................. 10-20
9.9.5 Alternate Bus Master Design Considerations.......................................................... 10-20
9.9.5.1 Edge Based Design.............................................................................................. 10-21
9.9.5.2 htrans [1:0]........................................................................................................... 10-21
9.9.5.3 hlock/hmastlock................................................................................................... 10-21
9.9.5.4 hmaster................................................................................................................. 10-21
9.9.5.5 hresp0—Bus Error ............................................................................................... 10-22
9.9.5.6 Unaligned Transfers............................................................................................. 10-22
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9.9.5.7 Alternate Bus Master Throttle Control ................................................................ 10-22
9.9.5.8 Halt Request (ccm_br)......................................................................................... 10-22
9.9.6 MAX AHB Slave Ports............................................................................................ 10-23
9.9.6.1 Slave Port 0—Primary AHB (Internal) ............................................................... 10-23
9.9.6.2 Secondary AHB Slave Ports 1 and 2 ................................................................... 10-24
9.9.7 Endian Modes .......................................................................................................... 10-25
9.9.7.1 Affected Modules ................................................................................................ 10-26
9.9.7.2 Unaffected Modules............................................................................................. 10-26
9.9.7.3 Un-Aligned Transfers .......................................................................................... 10-26
9.9.7.4 Endian Mode and Alternate Bus Masters ............................................................ 10-26
9.9.7.5 Little Endian Operation ....................................................................................... 10-26
9.9.7.6 Big Endian Operation .......................................................................................... 10-27
9.10 Preliminary Size Estimate............................................................................................ 10-28
9.11 Power Consumption..................................................................................................... 10-29
9.12 ARM9 Platform I/O Signal List................................................................................... 10-30
9.13 Electrical Specifications............................................................................................... 10-38
9.13.1 Conditions................................................................................................................ 10-39
9.13.2 Well Bias Mode ....................................................................................................... 10-39
9.13.2.1 Functional Operation in Well Bias Mode ............................................................ 10-39
9.13.3 clk and jtag_tck Relationship................................................................................... 10-39
9.13.4 Clocks and Reset Timing ......................................................................................... 10-39
9.13.5 Alternate Bus Master (ABM) Interface Timing....................................................... 10-40
9.13.6 Secondary AHB Timing .......................................................................................... 10-42
9.13.7 RAM and ROM Interface Timing............................................................................ 10-44
Chapter 10
ARM926EJ-S Interrupt Controller (AITC)
10.1 Overview........................................................................................................................ 11-1
10.1.1 Features...................................................................................................................... 11-2
10.1.2 Modes of Operation ................................................................................................... 11-2
10.2 Memory Map and Register Definition ........................................................................... 11-3
10.2.1 Memory Map ............................................................................................................. 11-3
10.2.2 Register Summary...................................................................................................... 11-4
10.2.3 Interrupt Control Register (INTCNTL) ..................................................................... 11-8
10.2.4 Normal Interrupt Mask Register (NIMASK)........................................................... 11-10
10.2.5 Interrupt Enable Number Register (INTENNUM).................................................. 11-11
10.2.6 Interrupt Disable Number Register (INTDISNUM)................................................ 11-12
10.2.7 Interrupt Enable Register High (INTENABLEH) and Low (INTENABLEL)........ 11-13
10.2.8 Interrupt Type Register High (INTTYPEH) and Low (INTTYPEL) ...................... 11-14
10.2.9 Normal Interrupt Priority Level Registers (NIPRIORITYn)................................... 11-15
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10.2.10 Normal Interrupt Vector and Status Register (NIVECSR) ...................................... 11-23
10.2.11 Fast Interrupt Vector and Status Register (FIVECSR) ............................................ 11-24
10.2.12 Interrupt Source Register High (INTSRCH) and Low (INTSRCL)........................ 11-25
10.2.12.1 Interrupt Assignments High................................................................................. 11-26
10.2.12.2 Interrupt Assignments Low ................................................................................. 11-27
10.2.13 Interrupt Force Register High (INTFRCH) and Low (INTFRCL) .......................... 11-28
10.2.14 Normal Interrupt Pending Register High (NIPNDH) and Low (NIPNDL)............. 11-29
10.2.15 Fast Interrupt Pending Register High (FIPNDH) and Low (FIPNDL).................... 11-30
10.3 ARM926EJ-S Interrupt Controller Operation ............................................................. 11-31
10.3.1 ARM926EJ-S Prioritization of Exception Sources ................................................. 11-31
10.3.2 AITC Prioritization of Interrupt Sources ................................................................. 11-31
10.3.3 Assigning and Enabling Interrupt Sources .............................................................. 11-32
10.3.4 Enabling Interrupt Sources ...................................................................................... 11-32
10.3.5 Typical Interrupt Entry Sequences........................................................................... 11-32
10.3.6 Writing Reentrant Normal Interrupt Routines ......................................................... 11-33
10.3.7 AHB Interface of AITC ........................................................................................... 11-34
Chapter 11
Security Controller (SCC)
11.1 Overview........................................................................................................................ 12-2
11.2 External Signal Description ........................................................................................... 12-2
Chapter 12
Symmetric/Asymmetric Hashing and Random Accelerator (SAHARA2)
12.1 Features.......................................................................................................................... 13-1
Chapter 13
Run-Time Integrity Checker (RTIC)
13.1 Features.......................................................................................................................... 14-1
13.1.1 Modes of Operation ................................................................................................... 14-2
13.2 Initialization/Application Information........................................................................... 14-2
13.2.1 System Application.................................................................................................... 14-2
Chapter 14
IC Identification (IIM)
14.1 Overview........................................................................................................................ 15-1
14.1.1 Features...................................................................................................................... 15-1
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Chapter 15
External Memory Interface (EMI)
15.1 Overview........................................................................................................................ 16-1
15.2 Features.......................................................................................................................... 16-3
15.3 PCMCIA Host Adapter.................................................................................................. 16-4
15.3.1 Interrupt Generation................................................................................................... 16-5
15.3.2 Card Extraction.......................................................................................................... 16-5
15.3.3 TrueIDE Support........................................................................................................ 16-5
15.4 NAND Flash Controller (NFC)...................................................................................... 16-5
15.4.1 Operation ................................................................................................................... 16-6
15.4.1.1 Internal and External Communications ................................................................. 16-6
15.4.1.2 Sharing of I/O Pins ................................................................................................ 16-7
15.5 Enhanced SDRAM Controller (ESDRAMC) ................................................................ 16-7
15.6 M3IF AHB MUX........................................................................................................... 16-7
15.6.1 Overview of EMI AHB MUX Operation .................................................................. 16-7
15.7 M3IF I/O MUX.............................................................................................................. 16-7
15.7.1 Overview of EMI I/O MUX Operation ..................................................................... 16-8
15.7.2 EMI Input/Output Signals........................................................................................ 16-22
15.8 Memory Map and Register Definitions ....................................................................... 16-29
Chapter 16
Multi-Master Memory Interface (M3IF)
16.1 Overview........................................................................................................................ 17-1
16.1.1 M3IF Interfaces.......................................................................................................... 17-1
16.1.2 Features...................................................................................................................... 17-3
16.2 External Signal Description ........................................................................................... 17-4
16.2.1 Overview.................................................................................................................... 17-4
16.3 Memory Map and Register Definition ........................................................................... 17-6
16.3.1 Memory Map ............................................................................................................. 17-6
16.3.2 Register Summary...................................................................................................... 17-7
16.3.3 Register Descriptions............................................................................................... 17-10
16.3.3.1 M3IF Control Register (M3IFCTL) .................................................................... 17-10
16.3.3.2 M3IF Snooping Configuration Register 0 (M3IFSCFG0) .................................. 17-12
16.3.3.3 M3IF Snooping Configuration Register 1–2 (M3IFSCFG1–2) .......................... 17-13
16.3.3.4 M3IF Snooping Status Register 0–1 (M3IFSSR0–1).......................................... 17-15
16.3.3.5 M3IF Master Lock WEIM CSx Register (M3IFMLWEx).................................. 17-17
16.4 Functional Description................................................................................................. 17-18
16.4.1 Master Port Gasket (MPG) ...................................................................................... 17-18
16.4.1.1 Overview of MPG Operation............................................................................... 17-18
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16.4.1.2 MPG Basic Transfer ............................................................................................ 17-23
16.4.1.3 MPG Transfer Type ............................................................................................. 17-24
16.4.1.4 MPG Transfer Response...................................................................................... 17-25
16.4.1.5 MPG Burst Operation .......................................................................................... 17-26
16.4.1.6 MPG Early Burst Termination............................................................................. 17-27
16.4.1.7 Multi-Endianness................................................................................................. 17-28
16.4.2 Master Port Gasket 64 (MPG64) ............................................................................. 17-29
16.4.2.1 Overview.............................................................................................................. 17-29
16.4.2.2 MPG64 Basic Transfer ........................................................................................ 17-31
16.4.2.3 MPG64 Transfer Type ......................................................................................... 17-31
16.4.2.4 Mpg64 Transfer Response ................................................................................... 17-32
16.4.2.5 MPG64 Burst Operation...................................................................................... 17-32
16.4.2.6 MPG64 Early Burst Termination......................................................................... 17-32
16.4.2.7 Multi Endianness ................................................................................................. 17-32
16.4.3 M3IF Arbitration (M3A) ......................................................................................... 17-33
16.4.3.1 Overview.............................................................................................................. 17-33
16.4.3.2 M3A–Find First 1 (FF1) Algorithm .................................................................... 17-35
16.4.3.3 Bus_free Signal Algorithm.................................................................................. 17-37
16.4.4 Master Arbitration and Buffering (MAB)................................................................ 17-37
16.4.4.1 Overview of MAB Operation .............................................................................. 17-37
16.4.4.2 M3B–Find First 1 (FF1) Algorithm..................................................................... 17-37
16.4.4.3 M3IF Operation During HMASTLOCK Accesses ............................................. 17-39
16.4.5 Snooping Logic........................................................................................................ 17-40
16.5 Initialization/Application Information ......................................................................... 17-41
16.5.1 M3IF in a System..................................................................................................... 17-41
Chapter 17
Wireless External Interface Module (WEIM)
17.1 Features.......................................................................................................................... 18-1
17.2 Overview........................................................................................................................ 18-1
17.3 External Signal Description ........................................................................................... 18-3
17.4 Detailed Signal Descriptions ......................................................................................... 18-4
17.5 Memory Map and Register Definition ........................................................................... 18-7
17.5.1 Memory Map ............................................................................................................. 18-8
17.5.2 Register Summary...................................................................................................... 18-9
17.5.3 Register Descriptions............................................................................................... 18-10
17.5.3.1 Chip Select x Upper Control Register (CSCRxU) .............................................. 18-13
17.5.3.2 Chip Select x Lower Control Register (CSCRxL)............................................... 18-17
17.5.3.3 Chip Select x Additional Control Register (CSCRxA) ....................................... 18-20
17.5.3.4 WEIM Configuration Register (WCR)................................................................ 18-23
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17.6 Functional Description................................................................................................. 18-24
17.6.1 Configurable Bus Sizing.......................................................................................... 18-24
17.6.2 WEIM Operational Modes....................................................................................... 18-25
17.6.3 Burst Mode Memory Operation............................................................................... 18-25
17.6.4 Burst Clock Divisor ................................................................................................. 18-26
17.6.5 Burst Clock Start...................................................................................................... 18-26
17.6.6 Page Mode Emulation.............................................................................................. 18-26
17.6.7 PSRAM Mode Operation......................................................................................... 18-27
17.6.8 Multiplexed Address/Data mode ............................................................................. 18-27
17.6.9 Mixed AHB/Memory Burst Modes Support ........................................................... 18-27
17.6.10 AHB Bus Cycles Support ........................................................................................ 18-27
17.6.11 DTACK Mode.......................................................................................................... 18-29
17.6.12 Internal Input Data Capture ..................................................................................... 18-29
17.6.13 Error Conditions ...................................................................................................... 18-29
17.7 Initialization/Application Information ......................................................................... 18-30
17.8 External Bus Timing Diagrams.................................................................................... 18-30
17.8.1 Asynchronous Memory Accesses Timing Diagrams............................................... 18-32
17.8.1.1 AHB Halfword Access to Halfword Width Memory .......................................... 18-32
17.8.1.2 AHB Word Access to Halfword Width Memory................................................. 18-39
17.8.2 Page Mode Timing Diagrams .................................................................................. 18-50
17.8.2.1 AHB Word Accesses to Halfword Width Memory ............................................. 18-50
17.8.3 DTACK Mode Memory Accesses Timing Diagrams .............................................. 18-51
17.8.3.1 AHB Word Accesses to Word-Width Memory.................................................... 18-51
17.8.4 Burst Memory Accesses Timing Diagrams ............................................................. 18-54
17.8.4.1 AHB Word Accesses to Halfword Width Memory ............................................. 18-54
17.8.4.2 AHB Accesses to Word-Width Burst Memory.................................................... 18-57
17.8.5 Synchronous Accesses Timing Diagrams with PSRAM ......................................... 18-65
17.8.5.1 AHB Sequential Accesses to Halfword Width PSRAM Memory....................... 18-65
17.8.5.2 AHB Sequential Accesses to Word-Width PSRAM Memory............................. 18-67
17.8.6 Multiplexed A/D Mode............................................................................................ 18-68
17.8.6.1 Asynchronous Word Accesses to Word-Width Memory..................................... 18-68
17.8.6.2 Synchronous Accesses with Word-Width Memory............................................. 18-70
Chapter 18
Enhanced SDRAM Controller (ESDRAMC)
18.1 Overview........................................................................................................................ 19-1
18.1.1 SDRAM Command Controller .................................................................................. 19-1
18.1.2 Bank Model................................................................................................................ 19-1
18.1.3 Decoder and Address MUX....................................................................................... 19-1
18.1.4 ESDRAMC Control and Configuration Registers ..................................................... 19-3
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18.1.5 Refresh Sequencer ..................................................................................................... 19-3
18.1.6 Command Sequencer ................................................................................................. 19-3
18.1.7 Size Logic .................................................................................................................. 19-3
18.1.8 Mobile/Low Power DDR (LPDDR) Interface ........................................................... 19-3
18.1.8.1 Power Down Timer................................................................................................ 19-4
18.1.9 Features...................................................................................................................... 19-4
18.1.10 Modes of Operation ................................................................................................... 19-5
18.2 External Signal Description ........................................................................................... 19-6
18.2.1 Detailed Signal Descriptions ..................................................................................... 19-7
18.3 Memory Map and Register Definition ........................................................................... 19-9
18.3.1 Memory Map ............................................................................................................. 19-9
18.3.2 Register Summary.................................................................................................... 19-10
18.3.3 Register Descriptions............................................................................................... 19-13
18.3.3.1 ESDCTL0 and ESDCTL1 Control Registers ...................................................... 19-14
18.3.3.2 ESDRAMC Configuration Registers (ESDCFG0 /ESDCFG1) .......................... 19-18
18.3.3.3 ESDMISC Miscellaneous Register (ESDMISC)................................................. 19-31
18.3.3.4 MDDR Delay Line 1–5 Configuration Debug Register ...................................... 19-33
18.3.3.5 MDDR Delay Line Cycle Length Debug Register .............................................. 19-35
18.4 Functional Description................................................................................................. 19-36
18.4.1 Enhanced SDRAM Controller Optimization Strategy............................................. 19-37
18.4.1.1 MIF1—No optimization/Sequential Accesses .................................................... 19-41
18.4.1.2 MIF2—Medium Level Optimization/Command Anticipation............................ 19-42
18.4.1.3 Latency Hiding .................................................................................................... 19-42
18.4.2 Address Multiplexing .............................................................................................. 19-44
18.4.2.1 Multiplexed Address Bus..................................................................................... 19-44
18.4.2.2 Bank Addresses ................................................................................................... 19-47
18.4.3 Multiplexed Address Bus—During “Special” Mode (SMODE 1 or 3)................... 19-47
18.4.4 Refresh..................................................................................................................... 19-47
18.4.5 Low Power Operating Modes .................................................................................. 19-49
18.4.5.1 Self Refresh Mode for SDRAM/LPDDR Devices .............................................. 19-49
18.4.5.2 Manual Self Refresh Mode for SDRAM/LPDDR Devices ................................. 19-51
18.4.5.3 Precharge Power Down Mode ............................................................................. 19-53
18.4.5.3.1 SDRAM Precharge Power Down Mode .......................................................... 19-53
18.4.5.4 Active Power Down Mode................................................................................... 19-57
18.4.5.4.1 SDRAM/LPDDR Active Power Down Mode ................................................. 19-57
18.4.5.5 Precharge Bank(s)—Low Power Mode ............................................................... 19-60
18.4.5.6 LPDDR Frequency Change ................................................................................. 19-60
18.4.6 SDRAM (SDR and LPDDR) Command Encoding................................................. 19-60
18.4.6.1 Reset .................................................................................................................... 19-61
18.4.7 Normal READ/WRITE Mode ................................................................................. 19-61
18.4.7.1 SDR Cycle Accurate Enhanced SDRAM Controller Accesses........................... 19-84
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18.4.7.1.1 Single Read Word Access to 16-Bit Memory.................................................. 19-84
18.4.7.1.2 Misaligned INCR4 Burst Read Access to 16-Bit Memory ............................. 19-85
18.4.7.1.3 Misaligned WRAP8 Burst Read Access to 32-Bit Memory ........................... 19-87
18.4.7.2 Single Write Word Access to 32-Bit Memory..................................................... 19-89
18.4.7.2.1 INCR4 Burst Write Word Access to 32-Bit Memory...................................... 19-90
18.4.7.3 SDRAM Command Sequence for Burst Accesses .............................................. 19-91
18.4.8 Precharge Command Mode ..................................................................................... 19-92
18.4.9 Auto-Refresh Mode ................................................................................................. 19-93
18.4.10 Manual Self Refresh Mode...................................................................................... 19-94
18.4.11 Set Mode Register Mode ......................................................................................... 19-94
18.5 Initialization/Application Information ......................................................................... 19-96
18.5.1 Memory Device Selection........................................................................................ 19-96
18.5.2 Configuring Controller for SDRAM Memory Array .............................................. 19-96
18.5.3 CAS Latency............................................................................................................ 19-96
18.5.4 SDRAM/LPDDR Initialization Sequence ............................................................... 19-97
18.5.4.1 SDRAM Initialization.......................................................................................... 19-97
18.5.4.1.1 SDR SDRAM Initialization............................................................................. 19-97
18.5.4.1.2 LPDDR SDRAM Initialization ....................................................................... 19-98
18.5.4.2 SDR SDRAM Load Mode Register .................................................................. 19-100
18.5.4.3 SDRAM Memory Configuration Examples ...................................................... 19-101
18.5.4.3.1 Single 64Mb (4Mx16) SDRAM Configuration............................................. 19-102
18.5.4.3.2 Single 128 Mb (8MBx16) SDRAM Configuration ....................................... 19-103
18.5.4.3.3 Single 256 Mb (16MBx16) SDRAM Configuration ..................................... 19-104
18.5.4.3.4 Single 512 Mb (32MBx16) SDRAM Configuration ..................................... 19-105
18.5.4.3.5 Single 1-Gb (64MBx16) SDRAM Configuration ......................................... 19-106
18.5.4.3.6 Dual 64 Mb (4MBx16) SDRAM Configuration ........................................... 19-107
18.5.4.3.7 Dual 128 Mb (8MBx16) SDRAM Configuration ......................................... 19-108
18.5.4.3.8 Dual 256 Mb (16MBx16) SDRAM Configuration ....................................... 19-109
18.5.4.3.9 Single 64-Mbyte (2MBx32) SDRAM Configuration.................................... 19-110
18.5.4.3.10 Single 128-Mbyte (4MBx32) SDRAM Configuration.................................. 19-111
18.5.4.3.11 Single 256-Mb (8MBx32) SDRAM Configuration....................................... 19-112
18.5.4.3.12 Single 512-Mb (16MBx32) SDRAM Configuration..................................... 19-113
18.5.4.3.13 Single 1-Gb (32Mx32) SDRAM Configuration ............................................ 19-114
18.5.4.3.14 Single 2-Gb (64MBx32) SDRAM Configuration ......................................... 19-115
18.5.4.3.15 Single 512-Mb (16MBx32) Mobile DDR SDRAM Configuration............... 19-116
18.5.4.3.16 Single 512-Mb (32MBx16) Mobile DDR SDRAM Configuration............... 19-117
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Chapter 19
NAND Flash Controller (NFC)
19.1 Overview........................................................................................................................ 20-1
19.2 Operation ....................................................................................................................... 20-2
19.3 Features.......................................................................................................................... 20-2
19.4 External Signal Description ........................................................................................... 20-3
19.4.1 Overview.................................................................................................................... 20-3
19.4.2 Detailed Signal Descriptions ..................................................................................... 20-3
19.5 NFC Buffer Memory Space ........................................................................................... 20-5
19.5.1 Main and Spare Area Buffers .................................................................................... 20-5
19.6 Memory Map and Register Definition ........................................................................... 20-7
19.6.1 Memory Map ............................................................................................................. 20-7
19.6.2 Register Summary...................................................................................................... 20-8
19.7 Register Descriptions ..................................................................................................... 20-9
19.7.1 Internal SRAM SIZE (NFC_BUFSIZE).................................................................... 20-9
19.7.2 Buffer Number for Page Data Transfer (RAM_BUFFER_ADDRESS).................. 20-10
19.7.3 NAND Flash Address (NAND_FLASH_ADD)...................................................... 20-10
19.7.4 NAND Flash Command (NAND_FLASH_CMD).................................................. 20-11
19.7.5 NFC Internal Buffer Lock Control (NFC_CONFIGURATION)............................. 20-11
19.7.6 Controller Status and Result of Flash Operation (ECC_STATUS_RESULT)......... 20-12
19.7.7 ECC Error Position of Main Area Data Error x8
(ECC_RSLT_MAIN_AREA).............................................................................. 20-12
19.7.8 ECC Error Position of Main Area Data Error x16
(ECC_RSLT_MAIN_AREA).............................................................................. 20-13
19.7.9 ECC Error Position of Spare Area Data Error x8
(ECC_RSLT_SPARE_AREA) ............................................................................ 20-14
19.7.10 ECC Error Position of Spare Area Data Error x16
(ECC_RSLT_SPARE_AREA) ............................................................................ 20-14
19.7.11 NAND Flash Write Protection (NF_WR_PROT).................................................... 20-15
19.7.12 Address to Unlock in Write Protection Mode—Start
(UNLOCK_START_BLK_ADD) ....................................................................... 20-15
19.7.13 Address to Unlock in Write Protection Mode—End
(UNLOCK_END_BLK_ADD) ........................................................................... 20-16
19.7.14 NAND Flash Write Protection Status (NAND_FLASH_WR_PR_ST) .................. 20-16
19.7.15 NAND Flash Operation Configuration (NAND_FLASH_CONFIG1) ................... 20-17
19.7.16 NAND Flash Operation Configuration 2 (NAND_FLASH_CONFIG2) ................ 20-18
19.8 Functional Description................................................................................................. 20-19
19.8.1 Modes of Operation ................................................................................................. 20-19
19.8.2 Booting From a NAND Flash Device...................................................................... 20-20
19.8.3 NAND Flash Control ............................................................................................... 20-22
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19.8.4 Error Code Correction (ECC) Control..................................................................... 20-23
19.8.5 Address Control ....................................................................................................... 20-23
19.8.6 RAM Buffer (SRAM).............................................................................................. 20-24
19.8.7 Registers (Command, Address, Status, and Others.)............................................... 20-24
19.8.8 Read and Write Control ........................................................................................... 20-24
19.8.9 Data Output Control................................................................................................. 20-24
19.8.10 Host Control............................................................................................................. 20-24
19.8.11 AHB BUS INTERFACE.......................................................................................... 20-24
19.8.11.1 Big/Little Endian ................................................................................................. 20-24
19.8.11.2 Burst Access Support........................................................................................... 20-25
19.8.12 I/O Pins Sharing....................................................................................................... 20-25
19.9 Initialization/Application Information ......................................................................... 20-25
19.9.1 Normal Operation .................................................................................................... 20-26
19.9.1.1 Fundamental Building Block Operations ............................................................ 20-26
19.9.1.1.1 Preset Operation .............................................................................................. 20-26
19.9.1.1.2 NAND Flash Command Input Operation ........................................................ 20-27
19.9.1.1.3 NAND Flash Address Input Operation............................................................ 20-28
19.9.1.1.4 NAND Flash Data Input Operation ................................................................. 20-29
19.9.1.1.5 NAND Flash Data Output Operation .............................................................. 20-30
19.9.1.2 NAND Flash ID Read Operation......................................................................... 20-31
19.9.1.2.1 NAND Flash ID Data Formats ........................................................................ 20-31
19.9.1.3 NAND Flash Status Read Operation ................................................................... 20-32
19.9.1.3.1 NAND Flash Status Data Format .................................................................... 20-32
19.9.1.4 Read NAND Flash Data Operation ..................................................................... 20-33
19.9.1.5 Program NAND Flash Data Operation................................................................ 20-34
19.9.1.6 Erase NAND Flash Data Operation..................................................................... 20-35
19.9.1.7 Hot Reset (Controller and NAND Flash Reset)................................................... 20-35
19.9.2 ECC Operation......................................................................................................... 20-36
19.9.2.1 ECC Normal Operation ....................................................................................... 20-36
19.9.2.2 ECC Bypass Operation ........................................................................................ 20-36
19.9.2.3 How to Operate ECC ........................................................................................... 20-36
19.9.3 Write Protection Operation...................................................................................... 20-37
19.9.3.1 Write Protection for RAM Buffer (LSB 1 Kbyte)............................................... 20-37
19.9.3.2 Write Protection Modes....................................................................................... 20-38
19.9.3.3 Write Protection Commands................................................................................ 20-38
19.9.3.4 Write Protection Status ........................................................................................ 20-39
19.9.3.4.1 Lock Sequence................................................................................................. 20-39
19.9.3.4.2 Unlock Sequence ............................................................................................. 20-40
19.9.3.4.3 Lock-tight Sequence ........................................................................................ 20-40
19.9.4 Memory Configuration Examples ........................................................................... 20-40
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Chapter 20
Personal Computer Memory Card International Association (PCMCIA) Controller
20.1 Overview........................................................................................................................ 21-1
20.2 Features.......................................................................................................................... 21-3
20.3 External Signal Description ........................................................................................... 21-3
20.3.1 Detailed Signal Descriptions ..................................................................................... 21-3
20.4 Memory Map and Register Definition ........................................................................... 21-6
20.4.1 Register Summary...................................................................................................... 21-7
20.4.1.1 PCMCIA Input Pins Register (PIPR) .................................................................... 21-9
20.4.1.2 PCMCIA Status Change Register (PSCR) .......................................................... 21-10
20.4.1.3 PCMCIA Enable Register (PER)......................................................................... 21-12
20.4.1.4 PCMCIA Base Registers 0–4 (PBR0–PBR4)...................................................... 21-14
20.4.1.5 PCMCIA Option Registers 0–4 (POR0–POR4).................................................. 21-15
20.4.1.6 PCMCIA Offset Registers 0–4 (POFR0–POFR4)............................................... 21-18
20.4.1.7 PCMCIA General Control Register (PGCR)....................................................... 21-19
20.4.1.8 PCMCIA General Status Register (PGSR).......................................................... 21-20
20.5 Functional Description................................................................................................. 21-21
20.5.1 Modes of Operation ................................................................................................. 21-21
20.5.2 Windowing Capabilities........................................................................................... 21-21
20.5.2.1 Window Overlapping........................................................................................... 21-21
20.5.3 WAIT Signal ............................................................................................................ 21-21
20.5.4 Interrupts.................................................................................................................. 21-22
20.5.4.1 Error Interrupt Conditions ................................................................................... 21-22
20.5.5 Power Control .......................................................................................................... 21-23
20.5.6 Reset and Three-Score Control................................................................................ 21-23
20.5.7 Write Protect ............................................................................................................ 21-23
20.5.8 16-Bit/8-Bit Support ................................................................................................ 21-24
20.5.9 Data and Control Signals Relations ......................................................................... 21-24
20.5.10 True IDE Mode Access............................................................................................ 21-25
20.5.11 Card Extraction ........................................................................................................ 21-26
20.5.12 TrueIDE Support...................................................................................................... 21-26
20.5.13 Endianness Support.................................................................................................. 21-27
20.6 Timing Diagrams ......................................................................................................... 21-28
Chapter 21
1-Wire Interface (1-Wire)
21.1 Overview........................................................................................................................ 22-1
21.2 Port Definitions.............................................................................................................. 22-2
21.3 Pin Configuration........................................................................................................... 22-2
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21.4 Clock Enable and AIPI Configuration........................................................................... 22-3
21.5 Functional Description................................................................................................... 22-3
21.5.1 Low-Power Modes..................................................................................................... 22-3
21.5.2 Reset Sequence with Reset Pulse Presence Pulse...................................................... 22-3
21.5.3 Write 0 ....................................................................................................................... 22-4
21.5.4 Write 1 and Read Data............................................................................................... 22-4
21.5.5 Program Pulse ............................................................................................................ 22-5
21.6 Memory Map and Register Definition ........................................................................... 22-5
21.6.1 Register Summary...................................................................................................... 22-5
21.6.1.1 Control Register (CONTROL) .............................................................................. 22-7
21.6.2 Time Divider Register (TIME_DIVIDER)................................................................ 22-9
21.6.3 Reset Register .......................................................................................................... 22-11
Chapter 22
Advanced Technology Attachment (ATA)
22.1 Overview........................................................................................................................ 23-1
22.2 Features.......................................................................................................................... 23-2
22.3 Operation ....................................................................................................................... 23-3
22.4 PIO Mode....................................................................................................................... 23-3
22.4.1 DMA Mode (Multi-Word DMA and Ultra DMA) .................................................... 23-3
22.5 External Signal Description ........................................................................................... 23-4
22.5.1 Detailed Signal Descriptions ..................................................................................... 23-5
22.5.1.1 ipp_do_ata_reset_b (out) ....................................................................................... 23-5
22.5.1.2 ipp_do_ata_dior (out) ............................................................................................ 23-5
22.5.1.3 ipp_do_ata_diow (out)........................................................................................... 23-5
22.5.1.4 ipp_do_ata_cs0, ipp_do_ata_cs1, ipp_do_ata_da2, ipp_do_ata_da1,
ipp_do_ata_da0 (out)......................................................................................... 23-5
22.5.1.5 ipp_ind_ata_dmarq (in) ......................................................................................... 23-5
22.5.1.6 ipp_do_ata_dmack (out) ........................................................................................ 23-5
22.5.1.7 ipp_ind_ata_intrq (in) ............................................................................................ 23-5
22.5.1.8 ipp_ind_ata_iordy (in) ........................................................................................... 23-5
22.5.1.9 ipp_do_ata_data[15:0] (out) .................................................................................. 23-6
22.6 Memory Map and Register Definition ........................................................................... 23-6
22.6.1 Memory Map ............................................................................................................. 23-6
22.6.2 Register Summary...................................................................................................... 23-7
22.6.3 Register Descriptions............................................................................................... 23-10
22.6.3.1 Timing Registers.................................................................................................. 23-10
22.6.3.1.1 TIME_CONFIG0............................................................................................. 23-11
22.6.3.1.2 TIME_CONFIG1............................................................................................. 23-12
22.6.3.1.3 TIME_CONFIG2............................................................................................. 23-13
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