2. NXP
  3. MCF51JE
MCF51JE

NXP MCF51JE Reference guide

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MCF51JE256 Reference Manual
An Energy-Efficient Solution from Freescale
Devices Supported:
MCF51JE256
MCF51JE128
Document Number: MCF51JE256
Rev. 2
12/2010
MCF51JE256 Reference Manual, Rev. 2
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MCF51JE256RM
Rev. 2
12/2010
MCF51JE256 Reference Manual, Rev. 2
Freescale Semiconductor iii
Contents
Chapter 1
Device Overview
1.1 The MCF51JE256 Series Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.1.1 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.1.2 Devices in the MCF51JE256 series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.2 MCF51JE256/128 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.2.1 Functional Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.2.2 Functional Versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1.3 V1 ColdFire Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1.3.1 User Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
1.3.2 Supervisor Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
1.4 System Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
1.4.1 System Clock Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
1.4.2 System Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
1.4.3 Clock Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
1.4.4 MCG Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
1.4.5 MCG Mode State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
Chapter 2
Pins and Connections
2.1 Device Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.2 104-Pin MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.3 100-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.4 81-Pin MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.5 80-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2.6 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.6.1 Pinout Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.6.2 Recommended System Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
2.6.3 Interfacing the SCIs to Off-Chip Opto-Isolators . . . . . . . . . . . . . . . . . . . . . . . 2-22
2.6.4 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
2.6.5 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23
2.6.6 PTD1/CMPP2/RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24
2.6.7 PTE4/CMPP3/TPMCLK/IRQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24
2.6.8 Background / Mode Select (PTD0/BKGD/MS) . . . . . . . . . . . . . . . . . . . . . . . . 2-24
2.6.9 ADC Reference Pins (V
REFH
, V
REFL
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25
2.6.10 Bootloader Mode Select (BLMS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25
2.6.11 USB Data Pins (USB_DP, USB_DN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25
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iv Freescale Semiconductor
2.6.12 General-Purpose I/O and Peripheral Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25
Chapter 3
Modes of Operation
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.4 Secure Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
3.5 Bootloader Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
3.5.1 Entering Bootloader Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
3.5.2 Entering User mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
3.5.3 Active Background Mode and Bootloader Mode Arbitrage . . . . . . . . . . . . . . . . 3-7
3.5.4 Bootloader Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
3.6 Run Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
3.6.1 Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
3.6.2 Low-Power Run Mode (LPrun) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
3.7 Wait Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
3.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
3.7.2 Low-Power Wait Mode (LPwait) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
3.8 Stop Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
3.8.1 Stop2 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
3.8.2 Stop3 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
3.8.3 Stop4 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
3.9 On-Chip peripheral Modules in Stop and Low-power Modes . . . . . . . . . . . . . . . . . . . 3-14
3.10 Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
Chapter 4
Memory
4.1 MCF51JE256 Series Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.1.1 Register Addresses and Bit Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4.1.2 Detailed register addresses and bit assignments . . . . . . . . . . . . . . . . . . . . . . . 4-3
4.1.3 Flash Module Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17
4.1.4 ColdFire Rapid GPIO Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18
4.1.5 ColdFire Interrupt Controller Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18
4.2 RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19
4.3 Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20
4.3.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21
4.3.2 Dual Flash Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21
4.3.3 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22
4.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-28
4.4.1 Flash Command Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-28
4.4.2 Flash Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-30
4.4.3 Illegal Flash Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-37
4.4.4 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-38
4.4.5 Flash Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-38
MCF51JE256 Reference Manual, Rev. 2
Freescale Semiconductor v
4.4.6 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-39
4.5 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-39
4.5.1 Unsecuring the MCU using Backdoor Key Access . . . . . . . . . . . . . . . . . . . . . 4-40
Chapter 5
Resets, Interrupts, and General System Control
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5.3 Microcontroller Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5.3.1 Computer Operating Properly (COP) Watchdog . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.3.2 Illegal Opcode Detect (ILOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
5.3.3 Illegal Address Detect (ILAD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
5.4 Interrupts & Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
5.4.1 External Interrupt Request (IRQ) Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
5.4.2 Interrupt Vectors, Sources, and Local Masks . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
5.5 Low-Voltage Detect (LVD) System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
5.5.1 Power-On Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
5.5.2 LVD Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
5.5.3 LVD Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
5.5.4 Low-Voltage Warning (LVW) Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . 5-10
5.6 Peripheral Clock Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
5.7 Reset, Interrupt, and System Control Registers and Control Bits . . . . . . . . . . . . . . . . 5-10
5.7.1 Interrupt Pin Request Status and Control Register (IRQSC) . . . . . . . . . . . . . 5-11
5.7.2 System Reset Status Register (SRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
5.7.3 System Options 1 (SOPT1) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
5.7.4 System Options 2 (SOPT2) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
5.7.5 SIM Clock Set and Select Register (SIMCO) . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
5.7.6 System Device Identification Register (SDIDH, SDIDL) . . . . . . . . . . . . . . . . . 5-16
5.7.7 System Clock Gating Control 1 Register (SCGC1) . . . . . . . . . . . . . . . . . . . . 5-17
5.7.8 System Clock Gating Control 2 Register (SCGC2) . . . . . . . . . . . . . . . . . . . . 5-18
5.7.9 System Clock Gating Control 3 Register (SCGC3) . . . . . . . . . . . . . . . . . . . . 5-18
5.7.10 System Options 3 Register (SOPT3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19
5.7.11 System Options 4 Register (SOPT4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21
5.7.12 System Options 5 Register (SOPT5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22
5.7.13 SIM Internal Peripheral Select Register (SIMIPS) . . . . . . . . . . . . . . . . . . . . . 5-22
5.7.14 Signature Register (Signature) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23
5.7.15 System Power Management Status and Control 1 Register (SPMSC1) . . . . 5-23
5.7.16 System Power Management Status and Control 2 Register (SPMSC2) . . . . 5-24
5.7.17 System Power Management Status and Control 3 Register (SPMSC3) . . . . 5-25
5.7.18 Flash Protection Disable Register (FPROTD) . . . . . . . . . . . . . . . . . . . . . . . . 5-26
5.7.19 Mini-FlexBus Pin Control 1 (MFBPC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27
5.7.20 Mini-FlexBus Pin Control 2 (MFBPC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28
5.7.21 Mini-FlexBus Pin Control 3 (MFBPC3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29
5.7.22 Mini-FlexBus Pin Control 4 (MFBPC4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-30
MCF51JE256 Reference Manual, Rev. 2
vi Freescale Semiconductor
Chapter 6
Parallel Input/Output Control
6.1 Port Data and Data Direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
6.2 Pull-up, Slew Rate, and Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
6.2.1 Port Internal Pull-up Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
6.2.2 Port Slew Rate Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
6.2.3 Port Drive Strength Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
6.2.4 Port Input Filter Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
6.3 ColdFire V1 Rapid GPIO Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
6.4 Keyboard Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
6.4.1 Edge Only Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
6.4.2 Edge and Level Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
6.4.3 Pull-up/Pull-down Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
6.4.4 Keyboard Interrupt Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
6.5 Pin Behavior in Stop Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
6.6 Parallel I/O, Keyboard Interrupt, and Pin Control Registers . . . . . . . . . . . . . . . . . . . . . . 6-5
6.6.1 Port A Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
6.6.2 Port B Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
6.6.3 Port C Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11
6.6.4 Port D Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13
6.6.5 Port E Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16
6.6.6 Port F Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19
6.6.7 Port G Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21
6.6.8 Port H Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24
6.6.9 Port J Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26
6.6.10 Keyboard Interrupt 1 (KBI1) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-29
6.6.11 Keyboard Interrupt 2 (KBI2) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-30
Chapter 7
ColdFire Core
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
7.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
7.2 Memory Map/Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
7.2.1 Data Registers (D0–D7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
7.2.2 Address Registers (A0–A6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
7.2.3 Supervisor/User Stack Pointers (A7 and OTHER_A7) . . . . . . . . . . . . . . . . . . . 7-5
7.2.4 Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
7.2.5 Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6
7.2.6 Vector Base Register (VBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7
7.2.7 CPU Configuration Register (CPUCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7
7.2.8 Status Register (SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8
7.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
7.3.1 Instruction Set Architecture (ISA_C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
7.3.2 Exception Processing Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
7.3.3 Processor Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13
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7.3.4 Instruction Execution Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-21
Chapter 8
Multiply-Accumulate Unit (MAC)
8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
8.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
8.2 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
8.2.1 MAC Status Register (MACSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
8.2.2 Mask Register (MASK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
8.2.3 Accumulator Register (ACC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5
8.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6
8.3.1 Fractional Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7
8.3.2 MAC Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8
8.3.3 MAC Instruction Execution Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9
8.3.4 Data Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9
8.3.5 MAC Opcodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9
Chapter 9
Rapid GPIO (RGPIO)
9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
9.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
9.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
9.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
9.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
9.2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
9.2.2 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
9.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4
9.3.1 RGPIO Data Direction (RGPIO_DIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5
9.3.2 RGPIO Data (RGPIO_DATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5
9.3.3 RGPIO Pin Enable (RGPIO_ENB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6
9.3.4 RGPIO Clear Data (RGPIO_CLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6
9.3.5 RGPIO Set Data (RGPIO_SET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7
9.3.6 RGPIO Toggle Data (RGPIO_TOG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7
9.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8
9.5 Initialization Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8
9.6 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8
9.6.1 Application 1: Simple Square-Wave Generation . . . . . . . . . . . . . . . . . . . . . . . . 9-9
9.6.2 Application 2: 16-bit Message Transmission using SPI Protocol . . . . . . . . . . . 9-9
Chapter 10
Interrupt Controller (CF1_INTC)
10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13
10.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14
10.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15
10.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-16
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10.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-16
10.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-16
10.3.1 Force Interrupt Register (INTC_FRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17
10.3.2 INTC Programmable Level 6, Priority {7,6} Registers (INTC_PL6P{7,6}) . . . 10-18
10.3.3 INTC Wakeup Control Register (INTC_WCR) . . . . . . . . . . . . . . . . . . . . . . . 10-19
10.3.4 INTC Set Interrupt Force Register (INTC_SFRC) . . . . . . . . . . . . . . . . . . . . 10-20
10.3.5 INTC Clear Interrupt Force Register (INTC_CFRC) . . . . . . . . . . . . . . . . . . . 10-21
10.3.6 INTC Software and Level-n IACK Registers (n = 1,2,3,...,7) . . . . . . . . . . . . . 10-21
10.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-22
10.4.1 Handling of Non-Maskable Level 7 Interrupt Requests . . . . . . . . . . . . . . . . 10-23
10.5 Initialization Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-23
10.6 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-23
10.6.1 Emulation of the HCS08’s 1-Level IRQ Handling . . . . . . . . . . . . . . . . . . . . . 10-23
10.6.2 Using INTC_PL6P{7,6} Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-24
10.6.3 More on Software IACKs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-24
Chapter 11
Programmable Analog Comparator (S08PRACMPV1)
11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
11.1.1 PRACMP Configuration Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
11.1.2 PRACMP/TPM Configuration Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
11.1.3 PRACMP Clock Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
11.1.4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
11.1.5 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
11.1.6 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
11.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4
11.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5
11.3.1 PRACMP Control and Status Register (PRACMPCS) . . . . . . . . . . . . . . . . . . 11-5
11.3.2 PRACMP Control Register 0 (PRACMPC0) . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6
11.3.3 PRACMP Control Register 1 (PRACMPC1) . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7
11.3.4 PRACMP Control Register 2 (PRACMPC2) . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8
11.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8
11.5 Setup and Operation of PRACMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9
11.6 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9
11.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10
Chapter 12
Analog-to-Digital Converter (S08ADC12V1)
12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
12.1.1 ADC Reference Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
12.1.2 Module Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
12.1.3 ADC Clock Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3
12.1.4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5
12.1.5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5
12.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6
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12.2.1 Analog Power (V
DDAD
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7
12.2.2 Analog Ground (V
SSAD
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7
12.2.3 Voltage Reference High (V
REFH
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7
12.2.4 Voltage Reference Low (V
REFL
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7
12.2.5 Analog Channel Inputs (ADx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7
12.3 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7
12.3.1 Status and Control Register 1 (ADCSC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8
12.3.2 Configuration Register 1(ADCCFG1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9
12.3.3 Configuration Register 2 (ADCCFG2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10
12.3.4 Data Result Registers (ADCRH:ADCRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-11
12.3.5 Compare Value High Register (ADCCVH) . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12
12.3.6 Compare Value Low Register (ADCCVL) . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12
12.3.7 Status and Control Register 2 (ADCSC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-13
12.3.8 Status and Control Register 3 (ADCSC3) . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-14
12.3.9 ADC Offset Correction Register (ADCOFSH:ADCOFSL) . . . . . . . . . . . . . . . 12-14
12.3.10ADC Plus-Side Gain Register (ADCPGH:ADCPGL) . . . . . . . . . . . . . . . . . . 12-15
12.3.11ADC Minus-Side Gain Register (ADCMGH:ADCMGL) . . . . . . . . . . . . . . . . 12-15
12.3.12ADC Plus-Side General Calibration Value Registers (ADCCLPx) . . . . . . . . 12-16
12.3.13ADC Minus-Side General Calibration Value Registers (ADCCLMx) . . . . . . 12-18
12.3.14Pin Control 1 Register (APCTL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-20
12.3.15Pin Control 2 Register (APCTL2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-21
12.3.16Pin Control 3 Register (APCTL3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-22
12.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-22
12.4.1 Clock Select and Divide Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-23
12.4.2 Input Select and Pin Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-23
12.4.3 Hardware Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-23
12.4.4 Conversion Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-24
12.4.5 Automatic Compare Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-28
12.4.6 Calibration Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-28
12.4.7 User-Defined Offset Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-29
12.4.8 Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-30
12.4.9 MCU Wait Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-31
12.4.10MCU Stop3 Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-31
12.4.11MCU Stop2 Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-32
12.5 Initialization Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-32
12.5.1 ADC Module Initialization Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-32
12.6 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-34
12.6.1 External Pins and Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-34
12.6.2 Sources of Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-36
Chapter 13
Cyclic Redundancy Check (CRC)
13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1
13.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3
13.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3
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13.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
13.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
13.3 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
13.3.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
13.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5
13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7
13.4.1 ITU-T (CCITT) Recommendations and Expected CRC Results . . . . . . . . . . . 13-7
13.4.2 Programming model extension for CF1Core . . . . . . . . . . . . . . . . . . . . . . . . . 13-8
13.4.3 Transpose feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-9
13.5 Initialization Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10
Chapter 14
Carrier Modulator Timer (CMT)
14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1
14.2 Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1
14.3 IRO Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1
14.4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3
14.5 CMT Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3
14.6 External Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3
14.7 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4
14.7.1 Carrier Generator Data Registers (CMTCGH1, CMTCGL1, CMTCGH2, and
CMTCGL2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4
14.7.2 CMT Output Control Register (CMTOC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5
14.7.3 CMT Modulator Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . 14-6
14.7.4 CMT Modulator Data Registers (CMTCMD1, CMTCMD2, CMTCMD3 and
CMTCMD4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-8
14.8 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-8
14.8.1 Carrier Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-10
14.8.2 Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-12
14.8.3 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-16
14.8.4 CMT Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-16
14.8.5 Low-Power Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-17
Chapter 15
12-bit Digital to Analog Converter (DAC12LVLPv1)
15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1
15.1.1 DAC Clock Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1
15.1.2 DAC V
ext
and V
int
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1
15.1.3 DAC Hardware Trigger Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1
15.1.4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3
15.1.5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3
15.2 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4
15.2.1 DAC Data Register x (DACDATxH:DACDATxL) . . . . . . . . . . . . . . . . . . . . . . . 15-5
15.2.2 DAC Status Register (DACS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5
15.2.3 DAC Control Register (DACC0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6
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15.2.4 DAC Control Register1 (DACC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7
15.2.5 DAC Control Register 2 (DACC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8
15.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8
15.3.1 DAC Data Buffer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8
15.3.2 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9
15.3.3 Low Power Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9
15.3.4 Background Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9
Chapter 16
Inter-Integrated Circuit (S08IICV3)
16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1
16.1.1 Module Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1
16.1.2 IIC Clock Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1
16.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3
16.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3
16.1.5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4
16.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4
16.2.1 SCL — Serial Clock Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4
16.2.2 SDA — Serial Data Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4
16.3 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5
16.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5
16.3.2 IIC Address Register 1 (IICA1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5
16.3.3 IIC Frequency Divider Register (IICF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-6
16.3.4 IIC Control Register (IICC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-9
16.3.5 IIC Status Register (IICS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-10
16.3.6 IIC Data I/O Register (IICD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-11
16.3.7 IIC Control Register 2 (IICC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-13
16.3.8 IIC SMBus Control and Status Register (IICSMB) . . . . . . . . . . . . . . . . . . . . 16-14
16.3.9 IIC Address Register 2 (IICA2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-15
16.3.10IIC SCL Low Time Out Register High (IICSLTH) . . . . . . . . . . . . . . . . . . . . . 16-15
16.3.11IIC SCL LowTime Out register Low (IICSLTL) . . . . . . . . . . . . . . . . . . . . . . . 16-15
16.3.12IIC Programmable Input Glitch Filter (IICFLT) . . . . . . . . . . . . . . . . . . . . . . . 16-16
16.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-17
16.4.1 IIC Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-17
16.4.2 10-bit Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-21
16.4.3 Address Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-22
16.4.4 System Management Bus Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-22
16.5
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-24
16.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-24
16.6.1 Byte Transfer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-25
16.6.2 Address Detect Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-25
16.6.3 Arbitration Lost Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-25
16.6.4 Timeouts Interrupt in SMbus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-25
16.6.5 Programmable input glitch filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-26
16.7 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-27
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16.8 SMBALERT# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-30
Chapter 17
Multipurpose Clock Generator (S08MCGV3)
17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1
17.1.1 Clock Check & Select Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3
17.1.2 Clock Check & Select Control (CCSCTRL) . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3
17.1.3 CCS XOSC1 Timer Register (CCSTMR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4
17.1.4 CCS XOSC2 Timer Register (CCSTMR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5
17.1.5 CCS Internal Reference Clock Timer Register (CCSTMRIR) . . . . . . . . . . . . . 17-5
17.1.6 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5
17.1.7 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-6
17.1.8 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-8
17.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-8
17.3 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-8
17.3.1 MCG Control Register 1 (MCGC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-8
17.3.2 MCG Control Register 2 (MCGC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-10
17.3.3 MCG Trim Register (MCGTRM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-11
17.3.4 MCG Status and Control Register (MCGSC) . . . . . . . . . . . . . . . . . . . . . . . . 17-12
17.3.5 MCG Control Register 3 (MCGC3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-13
17.3.6 MCG Control Register 4 (MCGC4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-14
17.3.7 MCG Test Register (MCGT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-15
17.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-16
17.4.1 MCG Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-16
17.4.2 MCG Mode State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-18
17.4.3 Mode Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-18
17.4.4 Bus Frequency Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-19
17.4.5 Low Power Bit Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-19
17.4.6 Internal Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-19
17.4.7 External Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-19
17.4.8 Fixed Frequency Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-20
17.4.9 MCGPLLSCLK Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-20
17.5
Initialization / Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-21
17.5.1 MCG Module Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-21
17.5.2 Using a 32.768 kHz Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-23
17.5.3 MCG Mode Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-23
17.5.4 Calibrating the Internal Reference Clock (IRC) . . . . . . . . . . . . . . . . . . . . . . 17-32
Chapter 18
Mini-FlexBus
18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1
18.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1
18.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1
18.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2
18.1.4 Module Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2
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18.1.5 Mini-FlexBus Security Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2
18.1.6 Mini-FlexBus Clock Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2
18.2 External Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3
18.2.1 Address and Data Buses (FB_An, FB_Dn, FB_ADn) . . . . . . . . . . . . . . . . . . . 18-3
18.2.2 Chip Selects (FB_CS
[1:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3
18.2.3 Output Enable (FB_OE
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3
18.2.4 Read/Write (FB_R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3
18.2.5 Address Latch Enable (FB_ALE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-4
18.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-4
18.3.1 Chip-Select Address Registers (CSAR0 – CSAR1) . . . . . . . . . . . . . . . . . . . . 18-4
18.3.2 Chip-Select Mask Registers (CSMR0 – CSMR1) . . . . . . . . . . . . . . . . . . . . . . 18-5
18.3.3 Chip-Select Control Registers (CSCR0 – CSCR1) . . . . . . . . . . . . . . . . . . . . . 18-6
18.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-7
18.4.1 Chip-Select Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-7
18.4.2 Data Transfer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-8
18.4.3 Data Byte Alignment and Physical Connections . . . . . . . . . . . . . . . . . . . . . . . 18-9
18.4.4 Address/Data Bus Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-9
18.4.5 Bus Cycle Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-9
18.4.6 Mini-FlexBus Timing Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-11
18.4.7 Bus Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-21
Chapter 19
Programmable Delay Block (PDB)
19.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1
19.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1
19.1.2 PDB Trigger Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1
19.2 ADC Hardware Triggers and Selects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1
19.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3
19.2.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3
19.2.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-4
19.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-8
19.3.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-8
19.3.2 Registers Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-8
19.3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-14
19.4 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-15
19.5 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-15
19.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-15
Chapter 20
Serial Communication Interface (S08SCIV4)
20.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-17
20.1.1 SCIx Clock Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-17
20.1.2 Module Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-17
20.1.3 Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-18
20.1.4 Interfacing the SCIs to Off-Chip Opto-Isolators . . . . . . . . . . . . . . . . . . . . . . 20-19
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20.1.5 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-19
20.1.6 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-20
20.1.7 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-21
20.2 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-23
20.2.1 SCI Baud Rate Registers (SCIxBDH, SCIxBDL) . . . . . . . . . . . . . . . . . . . . . 20-23
20.2.2 SCI Control Register 1 (SCIxC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-24
20.2.3 SCI Control Register 2 (SCIxC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-25
20.2.4 SCI Status Register 1 (SCIxS1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-26
20.2.5 SCI Status Register 2 (SCIxS2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-28
20.2.6 SCI Control Register 3 (SCIxC3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-29
20.2.7 SCI Data Register (SCIxD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-30
20.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-30
20.3.1 Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-30
20.3.2 Transmitter Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-31
20.3.3 Receiver Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-32
20.3.4 Interrupts and Status Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-34
20.3.5 Additional SCI Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-35
Chapter 21
16-bit Serial Peripheral Interface (S08SPI16V5)
21.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1
21.1.1 SPI1 Clock Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1
21.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3
21.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3
21.1.4 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-4
21.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-6
21.2.1 SPSCK — SPI Serial Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-6
21.2.2 MOSI — Master Data Out, Slave Data In . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-6
21.2.3 MISO — Master Data In, Slave Data Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-6
21.2.4 SS — Slave Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-6
21.3 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-6
21.3.1 SPI Control Register 1 (SPIxC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-7
21.3.2 SPI Control Register 2 (SPIxC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-8
21.3.3 SPI Baud Rate Register (SPIxBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-10
21.3.4 SPI Status Register (SPIxS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-11
21.3.5 SPI Data Registers (SPIxDH:SPIxDL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-14
21.3.6 SPI Match Registers (SPIxMH:SPIxML) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-15
21.3.7 SPI Control Register 3 (SPIxC3) — enable FIFO feature . . . . . . . . . . . . . . . 21-15
21.3.8 SPI Clear Interrupt Register (SPIxCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-17
21.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-18
21.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-18
21.4.2 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-18
21.4.3 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-19
21.4.4 SPI FIFO MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-21
21.4.5 Data Transmission Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-22
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21.4.6 SPI Clock Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-22
21.4.7 SPI Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-24
21.4.8 Special Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-25
21.4.9 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-26
21.4.10Low-power Mode Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-27
21.4.11SPI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-28
21.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-30
21.5.1 SPI Module Initialization Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-30
Chapter 22
8-bit Serial Peripheral Interface (S08SPIV5)
22.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1
22.1.1 SPI2 Clock Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1
22.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-3
22.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-3
22.1.4 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-3
22.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-5
22.2.1 SPSCK — SPI Serial Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-5
22.2.2 MOSI — Master Data Out, Slave Data In . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6
22.2.3 MISO — Master Data In, Slave Data Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6
22.2.4 SS — Slave Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6
22.3 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6
22.3.1 SPI Control Register 1 (SPIxC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6
22.3.2 SPI Control Register 2 (SPIxC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-8
22.3.3 SPI Baud Rate Register (SPIxBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-9
22.3.4 SPI Status Register (SPIxS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-10
22.3.5 SPI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-11
22.3.6 SPI Match Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-11
22.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-12
22.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-12
22.4.2 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-12
22.4.3 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-13
22.4.4 SPI Clock Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-14
22.4.5 SPI Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-16
22.4.6 Special Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-17
22.4.7 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-18
22.4.8 Low-power Mode Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-19
22.4.9 SPI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-20
22.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-21
22.5.1 SPI Module Initialization Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-21
Chapter 23
Time Of Day Module (S08TODV1)
23.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-1
23.1.1 TOD Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-1
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23.1.2 TOD Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-1
23.1.3 TOD Status after Stop2 Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-1
23.1.4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-3
23.1.5 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-3
23.1.6 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-4
23.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-5
23.2.1 TOD Clock (TODCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-5
23.2.2 TOD Match Signal (TODMTCHS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-5
23.3 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-5
23.3.1 TOD Control Register (TODC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-5
23.3.2 TOD Status and Control Register (TODSC) . . . . . . . . . . . . . . . . . . . . . . . . . . 23-6
23.3.3 TOD Match Register (TODM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-8
23.3.4 TOD Counter Register (TODCNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-8
23.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-8
23.4.1 TOD Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-9
23.4.2 TOD Match Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-9
23.4.3 Match Write Complete . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-10
23.4.4 TOD Clock Select and Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-11
23.4.5 Quarter-Second, One-Second, and Match Interrupts . . . . . . . . . . . . . . . . . . 23-12
23.4.6 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-13
23.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-13
23.5 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-13
23.5.1 Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-13
23.5.2 Initialization Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-14
23.6 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-17
Chapter 24
Timer/Pulse-Width Modulator (S08TPMV3)
24.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-1
24.1.1 ACMP/TPM Configuration Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-1
24.1.2 TPM External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-1
24.1.3 TPM Clock Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-1
24.1.4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-3
24.1.5 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-3
24.1.6 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-4
24.2 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-6
24.2.1 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-6
24.3 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-9
24.3.1 TPM Status and Control Register (TPMxSC) . . . . . . . . . . . . . . . . . . . . . . . . . 24-9
24.3.2 TPM-Counter Registers (TPMxCNTH:TPMxCNTL) . . . . . . . . . . . . . . . . . . . 24-10
24.3.3 TPM Counter Modulo Registers (TPMxMODH:TPMxMODL) . . . . . . . . . . . . 24-11
24.3.4 TPM Channel n Status and Control Register (TPMxCnSC) . . . . . . . . . . . . . 24-12
24.3.5 TPM Channel Value Registers (TPMxCnVH:TPMxCnVL) . . . . . . . . . . . . . . 24-13
24.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-15
24.4.1 Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-15
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24.4.2 Channel Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-16
24.5 Reset Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-19
24.5.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-19
24.5.2 Description of Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-20
24.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-20
24.6.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-20
24.6.2 Description of Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-20
Chapter 25
USB On-the-GO (USBOTG)
25.0.1 Module Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-3
25.0.2 USB Clock Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-3
25.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-3
25.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-3
25.2.1 USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-3
25.2.2 USB On-The-Go . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-5
25.2.3 USB-FS Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-6
25.2.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-6
25.3 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-6
25.3.1 USB Pull-up/Pull-down Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-6
25.3.2 USB OTG Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-7
25.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-8
25.4.1 Data Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-8
25.5 Programmers Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-9
25.5.1 Buffer Descriptor Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-9
25.5.2 Rx vs. Tx as a USB Target Device or USB Host . . . . . . . . . . . . . . . . . . . . . 25-10
25.5.3 Addressing Buffer Descriptor Table Entries . . . . . . . . . . . . . . . . . . . . . . . . . 25-10
25.5.4 Buffer Descriptor Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-11
25.5.5 USB Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-12
25.6 Memory Map/Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-14
25.6.1 Capability Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-15
25.7 OTG and Host Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-40
25.7.1 Configuration of External Pull-up/Pull-down for USB . . . . . . . . . . . . . . . . . . 25-40
25.8 Host Mode Operation Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-42
25.9 On-The-Go Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-44
25.9.1 OTG Dual Role A Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-44
25.9.2 OTG Dual Role B Devi
ce Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-46
25.9.3 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-47
25.9.4 USB Suspend State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-47
Chapter 26
Voltage Reference Module (S08VREFV1)
26.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-1
26.1.1 VREF Configuration Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-3
26.1.2 VREF Clock Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-3
MCF51JE256 Reference Manual, Rev. 2
xviii Freescale Semiconductor
26.1.3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-3
26.1.4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-4
26.1.5 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-4
26.1.6 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-4
26.2 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-5
26.2.1 VREF Trim Register (VREFTRM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-5
26.2.2 VREF Status and Control Register (VREFSC) . . . . . . . . . . . . . . . . . . . . . . . . 26-6
26.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-6
26.3.1 Voltage Reference Disabled, VREFEN=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-7
26.3.2 Voltage Reference Enabled, VREFEN=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-7
26.4 Initialization Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-7
Chapter 27
Version 1 ColdFire Debug (CF1_DEBUG)
27.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-1
27.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-2
27.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-3
27.1.3 Modes of Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-3
27.2 External Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-5
27.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-6
27.3.1 Configuration/Status Register (CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-7
27.3.2 Extended Configuration/Status Register (XCSR) . . . . . . . . . . . . . . . . . . . . . 27-10
27.3.3 Configuration/Status Register 2 (CSR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-13
27.3.4 Configuration/Status Register 3 (CSR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-16
27.3.5 BDM Address Attribute Register (BAAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-17
27.3.6 Address Attribute Trigger Register (AATR) . . . . . . . . . . . . . . . . . . . . . . . . . . 27-18
27.3.7 Trigger Definition Register (TDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-19
27.3.8 Program Counter Breakpoint/Mask Registers (PBR0–3, PBMR) . . . . . . . . . 27-22
27.3.9 Address Breakpoint Registers (ABLR, ABHR) . . . . . . . . . . . . . . . . . . . . . . . 27-24
27.3.10Data Breakpoint and Mask Registers (DBR, DBMR) . . . . . . . . . . . . . . . . . 27-25
27.3.11PST Buffer (PSTB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-26
27.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-27
27.4.1 Background Debug Mode (BDM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-27
27.4.2 Real-Time Debug Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-56
27.4.3 Trace Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-56
27.4.4 Freescale-Recommended BDM Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-67
Appendix A
Revision History
A.1 Changes Between Rev. 0 and Rev. 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-1
A.2 Changes Between Rev. 1 and Rev. 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-2
MCF51JE256 Reference Manual, Rev. 2
Freescale Semiconductor xix
About This Book
The primary objective of this reference manual is to define the processor for software and hardware
developers. The information in this book is subject to change without notice, as described in the
disclaimers on the title page. As with any technical documentation, the reader must use the most recent
version of the documentation.
To locate any published errata or updates for this document, refer to the world-wide web at
http://www.freescale.com/coldfire.
Portions of Chapter 25, “USB On-the-GO (USBOTG) Chapter 23, “Universal Serial Bus Interface – Host
Module,” and Chapter 24, “Universal Serial Bus Interface – On-The-Go Module,”relating to the EHCI
specification are Copyright © Intel Corporation 1999-2001. The EHCI specification is provided “As Is”
with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for
any particular purpose, or any warranty otherwise arising out of any proposal, specification or sample.
Intel disclaims all liability, including liability for infringement of any proprietary rights, relating to use of
information in the EHCI specification. Intel may make changes to the EHCI specifications at any time,
without notice.
Audience
This manual is intended for system software and hardware developers and applications programmers who
want to develop products with this ColdFire processor. It is assumed that the reader understands operating
systems, microprocessor system design, basic principles of software and hardware, and basic details of the
ColdFire
®
architecture.
Suggested Reading
This section lists additional reading that provides background for the information in this manual as well as
general information about ColdFire architecture.
General Information
Useful information about the ColdFire architecture and computer architecture in general:
• ColdFire Programmers Reference Manual (MCF5200PRM/AD)
• Using Microprocessors and Microcomputers: The Motorola Family, William C. Wray, Ross
Bannatyne, Joseph D. Greenfield
• Computer Architecture: A Quantitative Approach, Second Edition, by John L. Hennessy and David
A. Patterson.
• Computer Organization and Design: The Hardware/Software Interface, Second Edition, David A.
Patterson and John L. Hennessy.
MCF51JE256 Reference Manual, Rev. 2
xx Freescale Semiconductor
ColdFire Documentation
ColdFire documentation is available from the sources listed on the back cover of this manual, as well as
our web site, http://www.freescale.com/coldfire.
• Reference manuals — These books provide details about individual ColdFire implementations and
are intended to be used in conjunction with the ColdFire Programmers Reference Manual.
• Data sheets — Data sheets provide specific data regarding pin-out diagrams, bus timing, signal
behavior, and AC, DC, and thermal characteristics, as well as other design considerations.
• Product briefs — Each device has a product brief that provides an overview of its features. This
document is roughly equivalent to the overview (Chapter 1) of an device’s reference manual.
• Application notes — These short documents address specific design issues useful to programmers
and engineers working with Freescale Semiconductor processors.
Additional literature is published as new processors become available. For a current list of ColdFire
documentation, refer to http://www.freescale.com/coldfire.
Conventions
This document uses the following notational conventions:
cleared/set When a bit takes the value zero, it is said to be cleared; when it takes a value of
one, it is said to be set.
MNEMONICS In text, instruction mnemonics are shown in uppercase.
mnemonics In code and tables, instruction mnemonics are shown in lowercase.
italics Italics indicate variable command parameters.
Book titles in text are set in italics.
0x0 Prefix to denote hexadecimal number
0b0 Prefix to denote binary number
REG[FIELD] Abbreviations for registers are shown in uppercase. Specific bits, fields, or ranges
appear in brackets. For example, RAMBAR[BA] identifies the base address field
in the RAM base address register.
nibble A 4-bit data unit
byte An 8-bit data unit
word A 16-bit data unit
1
longword A 32-bit data unit
x In some contexts, such as signal encodings, x indicates a don’t care.
n Used to express an undefined numerical value
~ NOT logical operator
& AND logical operator
| OR logical operator
1
The only exceptions to this appear in the discussion of serial communication modules that support variable-length data
transmission units. To simplify the discussion these units are referred to as words regardless of length.
MCF51JE256 Reference Manual, Rev. 2
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