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NXP MCF51Jx Reference guide

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MCF51JU128 Reference Manual
Supports the MCF51JU32, MCF51JU64, and MCF51JU128
Document Number: MCF51JU128RM
Rev. 3, 08/2012
MCF51JU128 Reference Manual, Rev. 3, 08/2012
2 Freescale Semiconductor, Inc.
Contents
Section number Title Page
Chapter 1
About This Document
1.1 Overview.......................................................................................................................................................................59
1.1.1 Purpose...........................................................................................................................................................59
1.1.2 Audience........................................................................................................................................................59
1.2 Conventions..................................................................................................................................................................59
1.2.1 Numbering systems........................................................................................................................................59
1.2.2 Typographic notation.....................................................................................................................................60
1.2.3 Special terms..................................................................................................................................................60
1.2.4 Register reset..................................................................................................................................................61
Chapter 2
Introduction
2.1 ColdFire+ Portfolio Introduction..................................................................................................................................63
2.2 MCF51JU128 Block Diagram......................................................................................................................................64
2.3 MCF51JU Feature Summary........................................................................................................................................65
2.4 MCF51JU Features by Package....................................................................................................................................69
Chapter 3
Chip Configuration
3.1 Introduction...................................................................................................................................................................71
3.2 Module to Module Interaction Summary......................................................................................................................71
3.3 Core modules................................................................................................................................................................73
3.3.1 Version 1 (V1) ColdFire Core Configuration................................................................................................73
3.3.2 Debug Configuration......................................................................................................................................73
3.3.2.1 USB VREG in BDM..................................................................................................................74
3.4 System modules............................................................................................................................................................74
3.4.1 Crossbar Switch Configuration......................................................................................................................74
3.4.1.1 Crossbar Switch Master Assignments........................................................................................75
3.4.1.2 Crossbar Switch Slave Assignments..........................................................................................76
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3.4.2 Peripheral Bridge Configuration....................................................................................................................76
3.4.2.1 Peripheral bridge interfaces.......................................................................................................76
3.4.2.2 Memory map and module register access..................................................................................77
3.4.3 DMA Controller Configuration.....................................................................................................................77
3.4.3.1 DMA Request Sources...............................................................................................................77
3.4.4 Interrupt Controller (INTC) Configuration....................................................................................................78
3.4.4.1 Interrupt priority levels..............................................................................................................79
3.4.4.2 Interrupt channel assignments....................................................................................................79
3.4.5 Low-Leakage Wakeup Unit (LLWU) Configuration....................................................................................81
3.4.5.1 LLWU wakeup sources..............................................................................................................82
3.4.5.2 Reset due to LLWU wakeup event............................................................................................83
3.4.5.3 LLWU register reset...................................................................................................................83
3.4.6 Computer Operating Properly (COP) Watchdog Configuration....................................................................84
3.4.6.1 COP clocks.................................................................................................................................84
3.4.6.2 COP watchdog operation...........................................................................................................84
3.4.7 System Mode Controller (SMC) Configuration.............................................................................................86
3.4.7.1 SMC register reset......................................................................................................................86
3.4.8 Power Management Controller (PMC) Configuration...................................................................................87
3.4.8.1 PMC register reset......................................................................................................................87
3.4.9 Reset Control Module (RCM) Configuration................................................................................................87
3.4.9.1 RCM register reset.....................................................................................................................88
3.4.10 System Integration Module (SIM) Configuration..........................................................................................88
3.4.10.1 SIM register reset.......................................................................................................................89
3.5 Clock Modules..............................................................................................................................................................89
3.5.1 Multipurpose Clock Generator (MCG) Configuration..................................................................................89
3.5.1.1 MCG oscillator-frequency trim settings: factory and custom....................................................90
3.5.2 Oscillator (OSC) Configuration.....................................................................................................................91
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3.6 Memories and Memory Interfaces................................................................................................................................92
3.6.1 RAM Configuration.......................................................................................................................................92
3.6.1.1 RAM overview...........................................................................................................................92
3.6.1.2 RAM sizes..................................................................................................................................92
3.6.1.3 RAM retention in low power modes..........................................................................................93
3.6.1.4 RAM accesses............................................................................................................................93
3.6.2 Flash Memory Controller (FMC) Configuration...........................................................................................93
3.6.3 Flash Memory Module (FTFL) Configuration..............................................................................................94
3.6.3.1 Flash Memory Types.................................................................................................................95
3.6.3.2 Flash Memory Sizes...................................................................................................................95
3.6.3.3 Flash Memory Map....................................................................................................................96
3.6.3.4 Flash Security.............................................................................................................................97
3.6.3.5 Flash Modes...............................................................................................................................97
3.6.3.6 Erase All Flash Contents............................................................................................................97
3.6.3.7 FTFL_FOPT Register................................................................................................................97
3.6.4 System Register File Configuration...............................................................................................................97
3.6.4.1 Register file details.....................................................................................................................98
3.6.5 EzPort Configuration.....................................................................................................................................98
3.6.5.1 EzPort and BDM........................................................................................................................99
3.6.5.2 Flash Option Register (FOPT)...................................................................................................99
3.6.5.3 EzPort Clocking.........................................................................................................................99
3.6.6 Mini-FlexBus Configuration..........................................................................................................................100
3.6.6.1 Mini-FlexBus instantiation information.....................................................................................100
3.6.6.2 Mini-FlexBus CSCR0 reset value..............................................................................................101
3.6.6.3 Mini-FlexBus security................................................................................................................101
3.7 Security.........................................................................................................................................................................101
3.7.1 Cyclic Redundancy Check (CRC) Configuration..........................................................................................101
3.7.1.1 Module register width and serialization of accesses..................................................................102
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3.8 Analog...........................................................................................................................................................................102
3.8.1 12-bit Analog-to-Digital Converter (ADC) Configuration............................................................................102
3.8.1.1 Module register width and serialization of accesses..................................................................103
3.8.1.2 ADC instantiation information...................................................................................................103
3.8.1.3 DMA support on ADC...............................................................................................................103
3.8.1.4 ADC0 Channel Assignments.....................................................................................................104
3.8.1.5 ADC Reference, Triggers, and Alternate Clock........................................................................105
3.8.1.6 Clock Gating..............................................................................................................................105
3.8.2 Comparator (CMP) Configuration.................................................................................................................106
3.8.2.1 CMP instantiation information...................................................................................................106
3.8.2.2 External window/sample input...................................................................................................107
3.8.3 12-bit Digital-to-Analog Converter (DAC) Configuration............................................................................108
3.8.3.1 12-bit DAC Overview................................................................................................................108
3.8.3.2 12-bit DAC Instantiation............................................................................................................108
3.8.3.3 12-bit DAC Reference...............................................................................................................108
3.8.3.4 DAC DMA request ...................................................................................................................109
3.8.4 Voltage Reference (VREF) Configuration....................................................................................................109
3.8.4.1 VREF Overview.........................................................................................................................109
3.9 Timers...........................................................................................................................................................................110
3.9.1 Programmable Delay Block (PDB) Configuration........................................................................................110
3.9.1.1 Module register width and serialization of accesses..................................................................110
3.9.1.2 PDB Overview...........................................................................................................................111
3.9.1.3 PDB instantiation.......................................................................................................................111
3.9.1.4 PDB Module Interconnections...................................................................................................111
3.9.1.5 PDB acknowledgement connections..........................................................................................112
3.9.1.6 PDB Interval Trigger Connection to DAC................................................................................112
3.9.1.7 DAC External Trigger Input Connection...................................................................................112
3.9.1.8 Pulse-Out Connection................................................................................................................112
3.9.1.9 Pulse-Out Enable Register Implementation...............................................................................112
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3.9.2 FlexTimer (FTM) Configuration...................................................................................................................113
3.9.2.1 FTM overview............................................................................................................................113
3.9.2.2 FTM instantiation information...................................................................................................113
3.9.2.3 FTM external clock options.......................................................................................................115
3.9.3 Modulo Timer (MTIM) Configuration..........................................................................................................115
3.9.3.1 MTIM overview.........................................................................................................................115
3.9.4 Low Power Timer (LPTMR) Configuration..................................................................................................116
3.9.4.1 LPTMR overview......................................................................................................................116
3.9.4.2 LPTMR pin connections............................................................................................................117
3.9.4.3 LPTMR clock options................................................................................................................117
3.9.4.4 LPTMR register reset.................................................................................................................117
3.9.5 Carrier Modulator Transmitter (CMT) Configuration...................................................................................118
3.9.5.1 CMT instantiation information..................................................................................................118
3.9.5.2 CMT IRO drive strength............................................................................................................118
3.10 Communication interfaces............................................................................................................................................119
3.10.1 Universal Serial Bus (USB) FS Subsystem...................................................................................................119
3.10.1.1 USB Wakeup..............................................................................................................................119
3.10.1.2 USB Power Distribution............................................................................................................119
3.10.1.3 USB power management...........................................................................................................121
3.10.1.4 USB Controller Configuration...................................................................................................122
3.10.1.5 USB Device Charger Detection (USBDCD) Configuration......................................................122
3.10.1.6 USB Voltage Regulator (VREG) Configuration.......................................................................123
3.10.2 Serial Peripheral Interface (SPI) Configuration.............................................................................................124
3.10.2.1 Number and instantiation of SPI modules.................................................................................125
3.10.2.2 SPI baud rate..............................................................................................................................125
3.10.3 Inter-Integrated Circuit (I2C) Configuration.................................................................................................126
3.10.3.1 Number of I2C modules.............................................................................................................126
3.10.4 Universal Asynchronous Receiver/Transmitter (UART) Configuration.......................................................126
3.10.4.1 UART instances.........................................................................................................................127
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3.10.4.2 UART wakeup...........................................................................................................................127
3.10.4.3 UART support for opto-isolated interface.................................................................................127
3.10.5 Integrated Interchip Sound (I2S)/Synchronous Audio Interface (SAI) Configuration..................................128
3.10.5.1 Instantiation Information............................................................................................................128
3.10.5.2 Module register width and serialization of accesses..................................................................128
3.10.5.3 I2S/SAI Clocking.......................................................................................................................129
3.11 Human-machine interfaces (HMI)................................................................................................................................129
3.11.1 Rapid GPIO (RGPIO) Configuration.............................................................................................................129
3.11.1.1 Number of available RGPIO pins..............................................................................................130
3.11.1.2 RGPIO clock gating...................................................................................................................130
3.11.2 Enhanced GPIO (EGPIO) Configuration.......................................................................................................130
3.11.2.1 Instantiation Information............................................................................................................131
3.11.2.2 EGPIO registers.........................................................................................................................131
3.11.3 Touch Sense Input (TSI) Configuration.........................................................................................................132
3.11.3.1 Module register width and serialization of accesses..................................................................132
3.11.3.2 Number and instantiation of inputs............................................................................................132
3.11.3.3 TSI clock names.........................................................................................................................132
3.11.3.4 TSI module functionality in MCU operation modes.................................................................133
3.11.3.5 TSI Interrupts.............................................................................................................................133
3.11.4 External Interrupt (IRQ) Module Configuration............................................................................................134
Chapter 4
Memory Map
4.1 System Memory Map....................................................................................................................................................135
4.2 Read-after-write sequence and required serialization of memory operations..............................................................140
Chapter 5
Clock Distribution
5.1 Introduction...................................................................................................................................................................141
5.2 Clock distribution.........................................................................................................................................................141
5.2.1 High-Level device clocking diagram.............................................................................................................141
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5.2.2 Device Clock Summary.................................................................................................................................142
5.2.3 Architecture....................................................................................................................................................144
5.2.4 Clock divider requirements............................................................................................................................144
5.2.5 Clock gating...................................................................................................................................................145
5.2.6 Module clocks................................................................................................................................................145
5.2.6.1 VLPR Mode Clocking...............................................................................................................147
5.2.6.2 I2S/SAI Clocking.......................................................................................................................147
5.2.6.3 USB Controller Clocking...........................................................................................................147
5.2.6.4 UART Clocking.........................................................................................................................148
5.2.6.5 PMC's LPO clock.......................................................................................................................148
Chapter 6
Reset and Boot
6.1 Reset..............................................................................................................................................................................149
6.1.1 MCU reset sources.........................................................................................................................................149
6.1.1.1 Power-on reset (POR)................................................................................................................150
6.1.1.2 External RESET pin (PIN).........................................................................................................150
6.1.1.3 COP watchdog (WDOG) timer..................................................................................................151
6.1.1.4 Illegal opcode detect (ILOP)......................................................................................................151
6.1.1.5 Illegal address detect (ILAD).....................................................................................................151
6.1.1.6 Multipurpose Clock Generator loss of clock (LOC)..................................................................152
6.1.1.7 Low voltage detect (LVD).........................................................................................................152
6.1.1.8 Low leakage wakeup (WAKEUP).............................................................................................152
6.1.1.9 Stop mode acknowledge error (SACKERR) ............................................................................153
6.1.1.10 Background debug forced reset (BDFR)...................................................................................153
6.1.2 Reset Pin .......................................................................................................................................................153
6.1.3 MCU Resets...................................................................................................................................................154
6.1.3.1 POR Only ..................................................................................................................................154
6.1.3.2 Chip POR not VLLS .................................................................................................................154
6.1.3.3 Chip POR ..................................................................................................................................154
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6.1.3.4 Chip Reset not VLLS ................................................................................................................154
6.1.3.5 Early Chip Reset .......................................................................................................................154
6.1.3.6 Chip Reset .................................................................................................................................155
6.2 Boot...............................................................................................................................................................................155
6.2.1 Boot sources...................................................................................................................................................155
6.2.2 Boot options...................................................................................................................................................155
6.2.3 FOPT boot options.........................................................................................................................................156
6.2.4 Boot sequence................................................................................................................................................157
Chapter 7
Power Management
7.1 Introduction...................................................................................................................................................................159
7.2 Power modes.................................................................................................................................................................159
7.3 Module Operation in Low Power Modes......................................................................................................................160
Chapter 8
Security
8.1 Introduction...................................................................................................................................................................165
8.2 Flash Security...............................................................................................................................................................165
8.3 Flash Security Options..................................................................................................................................................166
8.3.1 Backdoor Key Access....................................................................................................................................166
8.3.2 Freescale Factory Access...............................................................................................................................166
8.4 Enabling Flash Security................................................................................................................................................167
8.5 Unsecuring the MCU using Backdoor Key Access......................................................................................................167
8.6 Unsecuring the MCU using the Erase All Blocks command........................................................................................168
8.7 Security Interactions with other Modules.....................................................................................................................169
8.7.1 Security interactions with Mini-FlexBus.......................................................................................................169
8.7.2 Security interactions with EzPort...................................................................................................................169
8.7.3 Security interactions with Debug...................................................................................................................169
Chapter 9
Signal Multiplexing and Signal Descriptions
9.1 Introduction...................................................................................................................................................................171
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9.2 Signal Multiplexing Integration....................................................................................................................................171
9.3 Port Mux Control Features............................................................................................................................................172
9.4 Signal Multiplexing and Pin Assignments....................................................................................................................173
9.5 Pinout diagrams............................................................................................................................................................176
9.6 Module-by-module signals...........................................................................................................................................180
9.7 Module Signal Description Tables................................................................................................................................190
9.7.1 Core Modules.................................................................................................................................................190
9.7.2 System Modules.............................................................................................................................................190
9.7.3 Clock Modules...............................................................................................................................................190
9.7.4 Memories and Memory Interfaces.................................................................................................................191
9.7.5 Analog............................................................................................................................................................192
9.7.6 Timer Modules...............................................................................................................................................193
9.7.7 Communication Interfaces.............................................................................................................................194
9.7.8 Human-Machine Interfaces (HMI)................................................................................................................196
Chapter 10
Port Mux Control
10.1 Port Mux Control..........................................................................................................................................................199
10.2 Memory Map and Registers..........................................................................................................................................199
10.2.1 Port A Pin Function 1 Register (MXC_PTAPF1).........................................................................................200
10.2.2 Port A Pin Function 2 Register (MXC_PTAPF2).........................................................................................201
10.2.3 Port A Pin Function 3 Register (MXC_PTAPF3).........................................................................................202
10.2.4 Port A Pin Function 4 Register (MXC_PTAPF4).........................................................................................202
10.2.5 Port B Pin Function 1 Register (MXC_PTBPF1)..........................................................................................203
10.2.6 Port B Pin Function 2 Register (MXC_PTBPF2)..........................................................................................204
10.2.7 Port B Pin Function 3 Register (MXC_PTBPF3)..........................................................................................205
10.2.8 Port B Pin Function 4 Register (MXC_PTBPF4)..........................................................................................205
10.2.9 Port C Pin Function 1 Register (MXC_PTCPF1)..........................................................................................206
10.2.10 Port C Pin Function 2 Register (MXC_PTCPF2)..........................................................................................207
10.2.11 Port C Pin Function 3 Register (MXC_PTCPF3)..........................................................................................208
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10.2.12 Port C Pin Function 4 Register (MXC_PTCPF4)..........................................................................................208
10.2.13 Port D Pin Function 1 Register (MXC_PTDPF1).........................................................................................209
10.2.14 Port D Pin Function 2 Register (MXC_PTDPF2).........................................................................................210
10.2.15 Port D Pin Function 3 Register (MXC_PTDPF3).........................................................................................211
10.2.16 Port D Pin Function 4 Register (MXC_PTDPF4).........................................................................................211
10.2.17 Port E Pin Function 1 Register (MXC_PTEPF1)..........................................................................................212
10.2.18 Port E Pin Function 2 Register (MXC_PTEPF2)..........................................................................................213
10.2.19 Port E Pin Function 3 Register (MXC_PTEPF3)..........................................................................................214
10.2.20 Port E Pin Function 4 Register (MXC_PTEPF4)..........................................................................................214
10.2.21 Port F Pin Function 1 Register (MXC_PTFPF1)...........................................................................................215
10.2.22 Port F Pin Function 2 Register (MXC_PTFPF2)...........................................................................................216
10.2.23 Port F Pin Function 3 Register (MXC_PTFPF3)...........................................................................................217
10.2.24 Port F Pin Function 4 Register (MXC_PTFPF4)...........................................................................................217
Chapter 11
Core
11.1 Introduction...................................................................................................................................................................219
11.1.1 Overview........................................................................................................................................................219
11.2 Memory Map/Register Description..............................................................................................................................221
11.2.1 Data registers (D0–D7)..................................................................................................................................223
11.2.2 Address registers (A0–A6).............................................................................................................................224
11.2.3 Supervisor/user stack pointers (A7 and OTHER_A7)...................................................................................224
11.2.4 Condition code register (CCR)......................................................................................................................226
11.2.5 Program counter (PC)....................................................................................................................................227
11.2.6 Vector base register (VBR)............................................................................................................................227
11.2.7 CPU configuration register (CPUCR)............................................................................................................228
11.2.8 Status register (SR)........................................................................................................................................231
11.3 Functional Description..................................................................................................................................................232
11.3.1 Instruction Set Architecture...........................................................................................................................232
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11.3.2 Exception Processing Overview....................................................................................................................233
11.3.2.1 Exception Stack Frame Definition.............................................................................................236
11.3.2.2 S08 and ColdFire Exception Processing Comparison...............................................................237
11.3.3 Processor Exceptions.....................................................................................................................................238
11.3.3.1 Access Error Exception..............................................................................................................238
11.3.3.2 Address Error Exception............................................................................................................239
11.3.3.3 Illegal Instruction Exception......................................................................................................240
11.3.3.4 Divide-By-Zero..........................................................................................................................241
11.3.3.5 Privilege Violation.....................................................................................................................241
11.3.3.6 Trace Exception.........................................................................................................................242
11.3.3.7 Unimplemented Line-A Opcode................................................................................................242
11.3.3.8 Unimplemented Line-F Opcode.................................................................................................243
11.3.3.9 Debug Interrupt .........................................................................................................................243
11.3.3.10 RTE and Format Error Exception .............................................................................................243
11.3.3.11 TRAP Instruction Exception......................................................................................................244
11.3.3.12 Unsupported Instruction Exception...........................................................................................244
11.3.3.13 Interrupt Exception....................................................................................................................244
11.3.3.14 Fault-on-Fault Halt.....................................................................................................................244
11.3.3.15 Reset Exception..........................................................................................................................245
11.3.4 Instruction Execution Timing........................................................................................................................248
11.3.4.1 Timing Assumptions..................................................................................................................248
11.3.4.2 MOVE Instruction Execution Times.........................................................................................249
11.3.4.3 Standard One Operand Instruction Execution Times................................................................250
11.3.4.4 Standard Two Operand Instruction Execution Times................................................................251
11.3.4.5 Miscellaneous Instruction Execution Times..............................................................................252
11.3.4.6 EMAC Instruction Execution Times..........................................................................................253
11.3.4.7 Branch Instruction Execution Times..........................................................................................255
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Chapter 12
Enhanced Multiply-Accumulate Unit (EMAC)
12.1 Introduction...................................................................................................................................................................257
12.1.1 Overview........................................................................................................................................................257
12.1.1.1 Introduction to the MAC............................................................................................................258
12.2 Memory Map/Register Definition.................................................................................................................................259
12.2.1 MAC Status Register (MACSR)....................................................................................................................260
12.2.2 Mask Register (MASK).................................................................................................................................262
12.2.3 Accumulator Registers (ACC0-3)..................................................................................................................264
12.2.4 Accumulator Extension Registers (ACCext01, ACCext23)..........................................................................265
12.3 Functional Description..................................................................................................................................................266
12.3.1 Fractional Operation Mode............................................................................................................................268
12.3.1.1 Rounding....................................................................................................................................269
12.3.1.2 Saving and Restoring the EMAC Programming Model............................................................270
12.3.1.3 MULS/MULU............................................................................................................................271
12.3.1.4 Scale Factor in MAC or MSAC Instructions.............................................................................271
12.3.2 EMAC Instruction Set Summary...................................................................................................................271
12.3.3 EMAC Instruction Execution Times..............................................................................................................272
12.3.4 Data Representation.......................................................................................................................................273
12.3.5 MAC Opcodes................................................................................................................................................273
Chapter 13
System Integration Module (SIM)
13.1 Introduction...................................................................................................................................................................279
13.2 Memory Map and Registers..........................................................................................................................................279
13.2.1 System Options Register 1 (SIM_SOPT1)....................................................................................................281
13.2.2 System Options Register 2 (SIM_SOPT2)....................................................................................................282
13.2.3 System Options Register 3 (SIM_SOPT3)....................................................................................................283
13.2.4 System Options Register 4 (SIM_SOPT4)....................................................................................................284
13.2.5 System Options Register 5 (SIM_SOPT5)....................................................................................................285
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13.2.6 System Options Register 6 (SIM_SOPT6)....................................................................................................285
13.2.7 System Options Register 7 (SIM_SOPT7)....................................................................................................286
13.2.8 COP Control Register (SIM_COPC).............................................................................................................287
13.2.9 Service COP Register (SIM_SRVCOP)........................................................................................................288
13.2.10 Oscillator 1 Control Register (SIM_OSC1)...................................................................................................289
13.2.11 Device Identification High Register (SIM_SDIDH).....................................................................................290
13.2.12 Device Identification Low Register (SIM_SDIDL).......................................................................................290
13.2.13 Clock Gate Control Register 1 (SIM_SCGC1)..............................................................................................291
13.2.14 Clock Gate Control Register 2 (SIM_SCGC2)..............................................................................................292
13.2.15 Clock Gate Control Register 3 (SIM_SCGC3)..............................................................................................293
13.2.16 Clock Gate Control Register 4 (SIM_SCGC4)..............................................................................................294
13.2.17 Clock Gate Control Register 5 (SIM_SCGC5)..............................................................................................295
13.2.18 Clock Gate Control Register 6 (SIM_SCGC6)..............................................................................................296
13.2.19 Clockout Register (SIM_CLKOUT)..............................................................................................................298
13.2.20 Clock Divider 0 Register (SIM_CLKDIV0)..................................................................................................299
13.2.21 Clock Divider 1 Register (SIM_CLKDIV1)..................................................................................................300
13.2.22 Flash Configuration Register (SIM_SPCR)...................................................................................................301
13.2.23 Unique Identification Register (SIM_UIDH3)..............................................................................................302
13.2.24 Unique Identification Register (SIM_UIDH2)..............................................................................................302
13.2.25 Unique Identification Register (SIM_UIDH1)..............................................................................................303
13.2.26 Unique Identification Register (SIM_UIDH0)..............................................................................................304
13.2.27 Unique Identification Register (SIM_UIDMH3)...........................................................................................304
13.2.28 Unique Identification Register (SIM_UIDMH2)...........................................................................................305
13.2.29 Unique Identification Register (SIM_UIDMH1)...........................................................................................306
13.2.30 Unique Identification Register (SIM_UIDMH0)...........................................................................................306
13.2.31 Unique Identification Register (SIM_UIDML3)...........................................................................................307
13.2.32 Unique Identification Register (SIM_UIDML2)...........................................................................................308
13.2.33 Unique Identification Register (SIM_UIDML1)...........................................................................................308
13.2.34 Unique Identification Register (SIM_UIDML0)...........................................................................................309
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13.2.35 Unique Identification Register (SIM_UIDL3)...............................................................................................310
13.2.36 Unique Identification Register (SIM_UIDL2)...............................................................................................310
13.2.37 Unique Identification Register (SIM_UIDL1)...............................................................................................311
13.2.38 Unique Identification Register (SIM_UIDL0)...............................................................................................312
Chapter 14
Crossbar Switch
14.1 Introduction...................................................................................................................................................................313
14.1.1 Features..........................................................................................................................................................313
14.2 Memory Map / Register Definition...............................................................................................................................314
14.3 Functional Description..................................................................................................................................................314
14.3.1 General operation...........................................................................................................................................314
14.3.2 Arbitration......................................................................................................................................................315
14.3.2.1 Arbitration During Undefined Length Bursts............................................................................315
14.3.2.2 Fixed-priority operation.............................................................................................................315
14.3.2.3 Round-robin priority operation..................................................................................................316
14.3.2.4 Priority Elevation.......................................................................................................................316
14.4 Initialization/application information...........................................................................................................................317
Chapter 15
Interrupt Controller (INTC)
15.1 Introduction...................................................................................................................................................................319
15.1.1 Overview........................................................................................................................................................320
15.1.2 Features..........................................................................................................................................................323
15.1.3 Modes of Operation.......................................................................................................................................324
15.2 External Signal Description..........................................................................................................................................324
15.3 Interrupt Request Level and Priority Assignments.......................................................................................................324
15.4 Memory Map and Registers..........................................................................................................................................325
15.4.1 Interrupt Mask Register High (INTC_IMRH)...............................................................................................326
15.4.2 Interrupt Mask Register Low (INTC_IMRL)................................................................................................328
15.4.3 Force Interrupt Register (INTC_FRC)...........................................................................................................332
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15.4.4 INTC Programmable Level 6 Priority Registers (INTC_PL6Pn)..................................................................333
15.4.5 INTC Wakeup Control Register (INTC_WCR)............................................................................................334
15.4.6 Set Interrupt Mask Register (INTC_SIMR)...................................................................................................335
15.4.7 Clear Interrupt Mask Register (INTC_CIMR)...............................................................................................336
15.4.8 INTC Set Interrupt Force Register (INTC_SFRC)........................................................................................337
15.4.9 INTC Clear Interrupt Force Register (INTC_CFRC)....................................................................................338
15.4.10 INTC Software IACK Register (INTC_SWIACK).......................................................................................339
15.4.11 INTC Level-n IACK Registers (INTC_LVLnIACK)....................................................................................339
15.5 Functional Description..................................................................................................................................................340
15.5.1 Handling of Non-Maskable Level 7 Interrupt Requests................................................................................340
15.6 Initialization Information..............................................................................................................................................341
15.7 Application Information................................................................................................................................................341
15.7.1 Emulation of the HCS08's 1-Level IRQ Handling.........................................................................................341
15.7.2 Using INTC_PL6P{7,6} Registers................................................................................................................342
15.7.3 More on Software IACKs..............................................................................................................................343
Chapter 16
Low Leakage Wakeup Unit (LLWU)
16.1 Introduction...................................................................................................................................................................347
16.1.1 Features..........................................................................................................................................................347
16.1.2 Modes of operation........................................................................................................................................348
16.1.2.1 LLS mode...................................................................................................................................348
16.1.2.2 VLLS modes..............................................................................................................................348
16.1.2.3 Non-low leakage modes.............................................................................................................348
16.1.2.4 Debug mode...............................................................................................................................349
16.1.3 Block diagram................................................................................................................................................349
16.2 LLWU signal descriptions............................................................................................................................................350
16.3 Memory map/register definition...................................................................................................................................351
16.3.1 LLWU Pin Enable 1 register (LLWU_PE1)..................................................................................................352
16.3.2 LLWU Pin Enable 2 register (LLWU_PE2)..................................................................................................353
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16.3.3 LLWU Pin Enable 3 register (LLWU_PE3)..................................................................................................354
16.3.4 LLWU Pin Enable 4 register (LLWU_PE4)..................................................................................................355
16.3.5 LLWU Module Enable register (LLWU_ME)..............................................................................................356
16.3.6 LLWU Flag 1 register (LLWU_F1)...............................................................................................................358
16.3.7 LLWU Flag 2 register (LLWU_F2)...............................................................................................................359
16.3.8 LLWU Flag 3 register (LLWU_F3)...............................................................................................................361
16.3.9 LLWU Pin Filter 1 register (LLWU_FILT1)................................................................................................363
16.3.10 LLWU Pin Filter 2 register (LLWU_FILT2)................................................................................................364
16.3.11 LLWU Reset Enable register (LLWU_RST).................................................................................................365
16.4 Functional description...................................................................................................................................................366
16.4.1 LLS mode.......................................................................................................................................................366
16.4.2 VLLS modes..................................................................................................................................................366
16.4.3 Initialization...................................................................................................................................................367
Chapter 17
Reset Control Module (RCM)
17.1 Introduction...................................................................................................................................................................369
17.2 Reset memory map and register descriptions...............................................................................................................369
17.2.1 System Reset Status Register 0 (RCM_SRS0)..............................................................................................369
17.2.2 System Reset Status Register 1 (RCM_SRS1)..............................................................................................371
17.2.3 Reset Pin Filter Control register (RCM_RPFC)............................................................................................372
17.2.4 Reset Pin Filter Width register (RCM_RPFW).............................................................................................373
17.2.5 Mode Register (RCM_MR)...........................................................................................................................375
Chapter 18
System Mode Controller (SMC)
18.1 Introduction...................................................................................................................................................................377
18.2 Modes of operation.......................................................................................................................................................377
18.3 Memory map and register descriptions.........................................................................................................................379
18.3.1 Power Mode Protection register (SMC_PMPROT).......................................................................................379
18.3.2 Power Mode Control register (SMC_PMCTRL)...........................................................................................380
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18.3.3 VLLS Control register (SMC_VLLSCTRL).................................................................................................382
18.3.4 Power Mode Status register (SMC_PMSTAT).............................................................................................383
18.4 Functional description...................................................................................................................................................384
18.4.1 Power mode transitions..................................................................................................................................384
18.4.2 Power mode entry/exit sequencing................................................................................................................387
18.4.2.1 Stop mode entry sequence..........................................................................................................388
18.4.2.2 Stop mode exit sequence............................................................................................................389
18.4.2.3 Aborted stop mode entry............................................................................................................389
18.4.2.4 Transition to wait modes............................................................................................................389
18.4.2.5 Transition from stop modes to Debug mode..............................................................................389
18.4.3 Run modes......................................................................................................................................................389
18.4.3.1 RUN mode.................................................................................................................................390
18.4.3.2 Very-Low Power Run (VLPR) mode........................................................................................390
18.4.3.3 BDM in Run and VLPR Mode..................................................................................................391
18.4.4 Wait modes....................................................................................................................................................391
18.4.4.1 WAIT mode...............................................................................................................................391
18.4.4.2 Very-Low-Power Wait (VLPW) mode......................................................................................392
18.4.4.3 BDM in Wait and VLPW Mode................................................................................................392
18.4.5 Stop modes.....................................................................................................................................................393
18.4.5.1 STOP mode................................................................................................................................393
18.4.5.2 Very-Low-Power Stop (VLPS) mode........................................................................................394
18.4.5.3 BDM in Stop and VLPS Modes.................................................................................................394
18.4.5.4 Low-Leakage Stop (LLS) mode................................................................................................395
18.4.5.5 Very-Low-Leakage Stop (VLLSx) modes.................................................................................395
18.4.5.6 BDM in LLS and VLLSx Modes...............................................................................................396
Chapter 19
Power Management Controller (PMC)
19.1 Introduction...................................................................................................................................................................397
19.2 Features.........................................................................................................................................................................397
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19.3 Low-voltage detect (LVD) system................................................................................................................................397
19.3.1 LVD reset operation.......................................................................................................................................398
19.3.2 LVD interrupt operation.................................................................................................................................398
19.3.3 Low-voltage warning (LVW) interrupt operation.........................................................................................398
19.4 I/O retention..................................................................................................................................................................399
19.5 Memory map and register descriptions.........................................................................................................................399
19.5.1 Low Voltage Detect Status And Control 1 register (PMC_LVDSC1)..........................................................399
19.5.2 Low Voltage Detect Status And Control 2 register (PMC_LVDSC2)..........................................................401
19.5.3 Regulator Status And Control register (PMC_REGSC)................................................................................402
Chapter 20
DMA Controller
20.1 Introduction...................................................................................................................................................................405
20.1.1 Overview........................................................................................................................................................405
20.1.2 Features..........................................................................................................................................................406
20.2 DMA Transfer Overview..............................................................................................................................................407
20.3 Memory Map and Registers..........................................................................................................................................408
20.3.1 DMA Request Control Register (DMA_REQC)...........................................................................................409
20.3.2 Source Address Register (DMA_SARn).......................................................................................................413
20.3.3 Destination Address Register (DMA_DARn)...............................................................................................414
20.3.4 DMA Status Register / Byte Count Register (DMA_DSR_BCRn)...............................................................414
20.3.5 DMA Control Register (DMA_DCRn)..........................................................................................................417
20.4 Functional Description..................................................................................................................................................420
20.4.1 Transfer Requests (Cycle-Steal and Continuous Modes)..............................................................................421
20.4.2 Channel Initialization and Startup..................................................................................................................421
20.4.2.1 Channel Prioritization................................................................................................................421
20.4.2.2 Programming the DMA Controller Module...............................................................................422
20.4.3 Dual-Address Data Transfer Mode................................................................................................................423
20.4.4 Advanced Data Transfer Controls: Auto-Alignment.....................................................................................424
20.4.5 Termination....................................................................................................................................................425
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