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MCF51Qx

NXP MCF51Qx Reference guide

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MCF51QU128 Reference Manual
Supports the MCF51QU32, MCF51QU64, and MCF51QU128
Document Number: MCF51QU128RM
Rev. 3, 08/2012
MCF51QU128 Reference Manual, Rev. 3, 08/2012
2 Freescale Semiconductor, Inc.
Contents
Section number Title Page
Chapter 1
About This Document
1.1 Overview.......................................................................................................................................................................55
1.1.1 Purpose...........................................................................................................................................................55
1.1.2 Audience........................................................................................................................................................55
1.2 Conventions..................................................................................................................................................................55
1.2.1 Numbering systems........................................................................................................................................55
1.2.2 Typographic notation.....................................................................................................................................56
1.2.3 Special terms..................................................................................................................................................56
1.2.4 Register reset..................................................................................................................................................57
Chapter 2
Introduction
2.1 ColdFire+ Portfolio Introduction..................................................................................................................................59
2.2 MCF51QU128 Block Diagram.....................................................................................................................................60
2.3 MCF51QU Feature Summary.......................................................................................................................................61
2.4 MCF51QU Features by Package..................................................................................................................................65
Chapter 3
Chip Configuration
3.1 Introduction...................................................................................................................................................................67
3.2 Module to Module Interaction Summary......................................................................................................................67
3.3 Core modules................................................................................................................................................................69
3.3.1 Version 1 (V1) ColdFire Core Configuration................................................................................................69
3.3.2 Debug Configuration......................................................................................................................................69
3.3.2.1 VREG in BDM...........................................................................................................................70
3.4 System modules............................................................................................................................................................70
3.4.1 Crossbar Switch Configuration......................................................................................................................70
3.4.1.1 Crossbar Switch Master Assignments........................................................................................71
3.4.1.2 Crossbar Switch Slave Assignments..........................................................................................72
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3.4.2 Peripheral Bridge Configuration....................................................................................................................72
3.4.2.1 Peripheral bridge interfaces.......................................................................................................72
3.4.2.2 Memory map and module register access..................................................................................73
3.4.3 DMA Controller Configuration.....................................................................................................................73
3.4.3.1 DMA Request Sources...............................................................................................................73
3.4.4 Interrupt Controller (INTC) Configuration....................................................................................................74
3.4.4.1 Interrupt priority levels..............................................................................................................75
3.4.4.2 Interrupt channel assignments....................................................................................................75
3.4.5 Low-Leakage Wakeup Unit (LLWU) Configuration....................................................................................77
3.4.5.1 LLWU wakeup sources..............................................................................................................78
3.4.5.2 Reset due to LLWU wakeup event............................................................................................79
3.4.5.3 LLWU register reset...................................................................................................................79
3.4.6 Computer Operating Properly (COP) Watchdog Configuration....................................................................80
3.4.6.1 COP clocks.................................................................................................................................80
3.4.6.2 COP watchdog operation...........................................................................................................80
3.4.7 System Mode Controller (SMC) Configuration.............................................................................................82
3.4.7.1 SMC register reset......................................................................................................................82
3.4.8 Power Management Controller (PMC) Configuration...................................................................................83
3.4.8.1 PMC register reset......................................................................................................................83
3.4.9 Reset Control Module (RCM) Configuration................................................................................................83
3.4.9.1 RCM register reset.....................................................................................................................84
3.4.10 Voltage Regulator (VREG) Configuration....................................................................................................84
3.4.10.1 VREG operation controls...........................................................................................................85
3.4.10.2 VREG in BDM...........................................................................................................................85
3.4.11 System Integration Module (SIM) Configuration..........................................................................................85
3.4.11.1 SIM register reset.......................................................................................................................86
3.5 Clock Modules..............................................................................................................................................................86
3.5.1 Multipurpose Clock Generator (MCG) Configuration..................................................................................86
3.5.1.1 MCG oscillator-frequency trim settings: factory and custom....................................................87
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3.5.2 Oscillator (OSC) Configuration.....................................................................................................................88
3.6 Memories and Memory Interfaces................................................................................................................................89
3.6.1 RAM Configuration.......................................................................................................................................89
3.6.1.1 RAM overview...........................................................................................................................89
3.6.1.2 RAM sizes..................................................................................................................................89
3.6.1.3 RAM retention in low power modes..........................................................................................90
3.6.1.4 RAM accesses............................................................................................................................90
3.6.2 Flash Memory Controller (FMC) Configuration...........................................................................................90
3.6.3 Flash Memory Module (FTFL) Configuration..............................................................................................91
3.6.3.1 Flash Memory Types.................................................................................................................92
3.6.3.2 Flash Memory Sizes...................................................................................................................92
3.6.3.3 Flash Memory Map....................................................................................................................93
3.6.3.4 Flash Security.............................................................................................................................94
3.6.3.5 Flash Modes...............................................................................................................................94
3.6.3.6 Erase All Flash Contents............................................................................................................94
3.6.3.7 FTFL_FOPT Register................................................................................................................94
3.6.4 System Register File Configuration...............................................................................................................94
3.6.4.1 Register file details.....................................................................................................................95
3.6.5 EzPort Configuration.....................................................................................................................................95
3.6.5.1 EzPort and BDM........................................................................................................................96
3.6.5.2 Flash Option Register (FOPT)...................................................................................................96
3.6.5.3 EzPort Clocking.........................................................................................................................96
3.6.6 Mini-FlexBus Configuration..........................................................................................................................97
3.6.6.1 Mini-FlexBus instantiation information.....................................................................................97
3.6.6.2 Mini-FlexBus CSCR0 reset value..............................................................................................98
3.6.6.3 Mini-FlexBus security................................................................................................................98
3.7 Security.........................................................................................................................................................................98
3.7.1 Cyclic Redundancy Check (CRC) Configuration..........................................................................................98
3.7.1.1 Module register width and serialization of accesses..................................................................99
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3.8 Analog...........................................................................................................................................................................99
3.8.1 12-bit Analog-to-Digital Converter (ADC) Configuration............................................................................99
3.8.1.1 Module register width and serialization of accesses..................................................................100
3.8.1.2 ADC instantiation information...................................................................................................100
3.8.1.3 DMA support on ADC...............................................................................................................100
3.8.1.4 ADC0 Channel Assignments.....................................................................................................101
3.8.1.5 ADC Reference, Triggers, and Alternate Clock........................................................................102
3.8.1.6 Clock Gating..............................................................................................................................102
3.8.2 Comparator (CMP) Configuration.................................................................................................................103
3.8.2.1 CMP instantiation information...................................................................................................103
3.8.2.2 External window/sample input...................................................................................................104
3.8.3 12-bit Digital-to-Analog Converter (DAC) Configuration............................................................................105
3.8.3.1 12-bit DAC Overview................................................................................................................105
3.8.3.2 12-bit DAC Instantiation............................................................................................................105
3.8.3.3 12-bit DAC Reference...............................................................................................................105
3.8.3.4 DAC DMA request ...................................................................................................................106
3.8.4 Voltage Reference (VREF) Configuration....................................................................................................106
3.8.4.1 VREF Overview.........................................................................................................................106
3.9 Timers...........................................................................................................................................................................107
3.9.1 Programmable Delay Block (PDB) Configuration........................................................................................107
3.9.1.1 Module register width and serialization of accesses..................................................................107
3.9.1.2 PDB Overview...........................................................................................................................108
3.9.1.3 PDB instantiation.......................................................................................................................108
3.9.1.4 PDB Module Interconnections...................................................................................................108
3.9.1.5 PDB acknowledgement connections..........................................................................................109
3.9.1.6 PDB Interval Trigger Connection to DAC................................................................................109
3.9.1.7 DAC External Trigger Input Connection...................................................................................109
3.9.1.8 Pulse-Out Connection................................................................................................................109
3.9.1.9 Pulse-Out Enable Register Implementation...............................................................................109
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3.9.2 FlexTimer (FTM) Configuration...................................................................................................................110
3.9.2.1 FTM overview............................................................................................................................110
3.9.2.2 FTM instantiation information...................................................................................................110
3.9.2.3 FTM external clock options.......................................................................................................112
3.9.3 Modulo Timer (MTIM) Configuration..........................................................................................................112
3.9.3.1 MTIM overview.........................................................................................................................112
3.9.4 Low Power Timer (LPTMR) Configuration..................................................................................................113
3.9.4.1 LPTMR overview......................................................................................................................113
3.9.4.2 LPTMR pin connections............................................................................................................114
3.9.4.3 LPTMR clock options................................................................................................................114
3.9.4.4 LPTMR register reset.................................................................................................................114
3.9.5 Carrier Modulator Transmitter (CMT) Configuration...................................................................................115
3.9.5.1 CMT instantiation information..................................................................................................115
3.9.5.2 CMT IRO drive strength............................................................................................................115
3.10 Communication interfaces............................................................................................................................................116
3.10.1 Serial Peripheral Interface (SPI) Configuration.............................................................................................116
3.10.1.1 Number and instantiation of SPI modules.................................................................................116
3.10.1.2 SPI baud rate..............................................................................................................................116
3.10.2 Inter-Integrated Circuit (I2C) Configuration.................................................................................................117
3.10.2.1 Number of I2C modules.............................................................................................................117
3.10.3 Universal Asynchronous Receiver/Transmitter (UART) Configuration.......................................................118
3.10.3.1 UART instances.........................................................................................................................118
3.10.3.2 UART wakeup...........................................................................................................................118
3.10.3.3 UART support for opto-isolated interface.................................................................................118
3.11 Human-machine interfaces (HMI)................................................................................................................................119
3.11.1 Rapid GPIO (RGPIO) Configuration.............................................................................................................119
3.11.1.1 Number of available RGPIO pins..............................................................................................119
3.11.1.2 RGPIO clock gating...................................................................................................................120
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3.11.2 Enhanced GPIO (EGPIO) Configuration.......................................................................................................120
3.11.2.1 Instantiation Information............................................................................................................120
3.11.2.2 EGPIO registers.........................................................................................................................121
3.11.3 Touch Sense Input (TSI) Configuration.........................................................................................................121
3.11.3.1 Module register width and serialization of accesses..................................................................122
3.11.3.2 Number and instantiation of inputs............................................................................................122
3.11.3.3 TSI clock names.........................................................................................................................122
3.11.3.4 TSI module functionality in MCU operation modes.................................................................122
3.11.3.5 TSI Interrupts.............................................................................................................................123
3.11.4 External Interrupt (IRQ) Module Configuration............................................................................................123
Chapter 4
Memory Map
4.1 System Memory Map....................................................................................................................................................125
4.2 Read-after-write sequence and required serialization of memory operations..............................................................130
Chapter 5
Clock Distribution
5.1 Introduction...................................................................................................................................................................131
5.2 Clock distribution.........................................................................................................................................................131
5.2.1 High-Level device clocking diagram.............................................................................................................131
5.2.2 Device Clock Summary.................................................................................................................................132
5.2.3 Architecture....................................................................................................................................................134
5.2.4 Clock divider requirements............................................................................................................................134
5.2.5 Clock gating...................................................................................................................................................135
5.2.6 Module clocks................................................................................................................................................135
5.2.6.1 VLPR Mode Clocking...............................................................................................................136
5.2.6.2 UART Clocking.........................................................................................................................136
5.2.6.3 PMC's LPO clock.......................................................................................................................136
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Chapter 6
Reset and Boot
6.1 Reset..............................................................................................................................................................................139
6.1.1 MCU reset sources.........................................................................................................................................139
6.1.1.1 Power-on reset (POR)................................................................................................................140
6.1.1.2 External RESET pin (PIN).........................................................................................................140
6.1.1.3 COP watchdog (WDOG) timer..................................................................................................141
6.1.1.4 Illegal opcode detect (ILOP)......................................................................................................141
6.1.1.5 Illegal address detect (ILAD).....................................................................................................141
6.1.1.6 Multipurpose Clock Generator loss of clock (LOC)..................................................................142
6.1.1.7 Low voltage detect (LVD).........................................................................................................142
6.1.1.8 Low leakage wakeup (WAKEUP).............................................................................................142
6.1.1.9 Stop mode acknowledge error (SACKERR) ............................................................................143
6.1.1.10 Background debug forced reset (BDFR)...................................................................................143
6.1.2 Reset Pin .......................................................................................................................................................143
6.1.3 MCU Resets...................................................................................................................................................144
6.1.3.1 POR Only ..................................................................................................................................144
6.1.3.2 Chip POR not VLLS .................................................................................................................144
6.1.3.3 Chip POR ..................................................................................................................................144
6.1.3.4 Chip Reset not VLLS ................................................................................................................144
6.1.3.5 Early Chip Reset .......................................................................................................................144
6.1.3.6 Chip Reset .................................................................................................................................145
6.2 Boot...............................................................................................................................................................................145
6.2.1 Boot sources...................................................................................................................................................145
6.2.2 Boot options...................................................................................................................................................145
6.2.3 FOPT boot options.........................................................................................................................................146
6.2.4 Boot sequence................................................................................................................................................147
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Chapter 7
Power Management
7.1 Introduction...................................................................................................................................................................149
7.2 Power modes.................................................................................................................................................................149
7.3 Module Operation in Low Power Modes......................................................................................................................150
Chapter 8
Security
8.1 Introduction...................................................................................................................................................................155
8.2 Flash Security...............................................................................................................................................................155
8.3 Flash Security Options..................................................................................................................................................156
8.3.1 Backdoor Key Access....................................................................................................................................156
8.3.2 Freescale Factory Access...............................................................................................................................156
8.4 Enabling Flash Security................................................................................................................................................157
8.5 Unsecuring the MCU using Backdoor Key Access......................................................................................................157
8.6 Unsecuring the MCU using the Erase All Blocks command........................................................................................158
8.7 Security Interactions with other Modules.....................................................................................................................159
8.7.1 Security interactions with Mini-FlexBus.......................................................................................................159
8.7.2 Security interactions with EzPort...................................................................................................................159
8.7.3 Security interactions with Debug...................................................................................................................159
Chapter 9
Signal Multiplexing and Signal Descriptions
9.1 Introduction...................................................................................................................................................................161
9.2 Signal Multiplexing Integration....................................................................................................................................161
9.3 Port Mux Control Features............................................................................................................................................162
9.4 Signal Multiplexing and Pin Assignments....................................................................................................................163
9.5 Pinout diagrams............................................................................................................................................................166
9.6 Module-by-module signals...........................................................................................................................................169
9.7 Module Signal Description Tables................................................................................................................................178
9.7.1 Core Modules.................................................................................................................................................178
9.7.2 System Modules.............................................................................................................................................178
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9.7.3 Clock Modules...............................................................................................................................................179
9.7.4 Memories and Memory Interfaces.................................................................................................................179
9.7.5 Analog............................................................................................................................................................181
9.7.6 Timer Modules...............................................................................................................................................181
9.7.7 Communication Interfaces.............................................................................................................................183
9.7.8 Human-Machine Interfaces (HMI)................................................................................................................184
Chapter 10
Port Mux Control
10.1 Port Mux Control..........................................................................................................................................................187
10.2 Memory Map and Registers..........................................................................................................................................187
10.2.1 Port A Pin Function 1 Register (MXC_PTAPF1).........................................................................................188
10.2.2 Port A Pin Function 2 Register (MXC_PTAPF2).........................................................................................189
10.2.3 Port A Pin Function 3 Register (MXC_PTAPF3).........................................................................................190
10.2.4 Port A Pin Function 4 Register (MXC_PTAPF4).........................................................................................190
10.2.5 Port B Pin Function 1 Register (MXC_PTBPF1)..........................................................................................191
10.2.6 Port B Pin Function 2 Register (MXC_PTBPF2)..........................................................................................192
10.2.7 Port B Pin Function 3 Register (MXC_PTBPF3)..........................................................................................193
10.2.8 Port B Pin Function 4 Register (MXC_PTBPF4)..........................................................................................193
10.2.9 Port C Pin Function 1 Register (MXC_PTCPF1)..........................................................................................194
10.2.10 Port C Pin Function 2 Register (MXC_PTCPF2)..........................................................................................195
10.2.11 Port C Pin Function 3 Register (MXC_PTCPF3)..........................................................................................196
10.2.12 Port C Pin Function 4 Register (MXC_PTCPF4)..........................................................................................196
10.2.13 Port D Pin Function 1 Register (MXC_PTDPF1).........................................................................................197
10.2.14 Port D Pin Function 2 Register (MXC_PTDPF2).........................................................................................198
10.2.15 Port D Pin Function 3 Register (MXC_PTDPF3).........................................................................................199
10.2.16 Port D Pin Function 4 Register (MXC_PTDPF4).........................................................................................199
10.2.17 Port E Pin Function 1 Register (MXC_PTEPF1)..........................................................................................200
10.2.18 Port E Pin Function 2 Register (MXC_PTEPF2)..........................................................................................201
10.2.19 Port E Pin Function 3 Register (MXC_PTEPF3)..........................................................................................202
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10.2.20 Port E Pin Function 4 Register (MXC_PTEPF4)..........................................................................................202
10.2.21 Port F Pin Function 1 Register (MXC_PTFPF1)...........................................................................................203
10.2.22 Port F Pin Function 2 Register (MXC_PTFPF2)...........................................................................................204
10.2.23 Port F Pin Function 3 Register (MXC_PTFPF3)...........................................................................................205
10.2.24 Port F Pin Function 4 Register (MXC_PTFPF4)...........................................................................................205
Chapter 11
Core
11.1 Introduction...................................................................................................................................................................207
11.1.1 Overview........................................................................................................................................................207
11.2 Memory Map/Register Description..............................................................................................................................209
11.2.1 Data registers (D0–D7)..................................................................................................................................211
11.2.2 Address registers (A0–A6).............................................................................................................................212
11.2.3 Supervisor/user stack pointers (A7 and OTHER_A7)...................................................................................212
11.2.4 Condition code register (CCR)......................................................................................................................214
11.2.5 Program counter (PC)....................................................................................................................................215
11.2.6 Vector base register (VBR)............................................................................................................................215
11.2.7 CPU configuration register (CPUCR)............................................................................................................216
11.2.8 Status register (SR)........................................................................................................................................219
11.3 Functional Description..................................................................................................................................................220
11.3.1 Instruction Set Architecture...........................................................................................................................220
11.3.2 Exception Processing Overview....................................................................................................................221
11.3.2.1 Exception Stack Frame Definition.............................................................................................224
11.3.2.2 S08 and ColdFire Exception Processing Comparison...............................................................225
11.3.3 Processor Exceptions.....................................................................................................................................226
11.3.3.1 Access Error Exception..............................................................................................................226
11.3.3.2 Address Error Exception............................................................................................................227
11.3.3.3 Illegal Instruction Exception......................................................................................................228
11.3.3.4 Divide-By-Zero..........................................................................................................................229
11.3.3.5 Privilege Violation.....................................................................................................................229
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11.3.3.6 Trace Exception.........................................................................................................................230
11.3.3.7 Unimplemented Line-A Opcode................................................................................................230
11.3.3.8 Unimplemented Line-F Opcode.................................................................................................231
11.3.3.9 Debug Interrupt .........................................................................................................................231
11.3.3.10 RTE and Format Error Exception .............................................................................................231
11.3.3.11 TRAP Instruction Exception......................................................................................................232
11.3.3.12 Unsupported Instruction Exception...........................................................................................232
11.3.3.13 Interrupt Exception....................................................................................................................232
11.3.3.14 Fault-on-Fault Halt.....................................................................................................................232
11.3.3.15 Reset Exception..........................................................................................................................233
11.3.4 Instruction Execution Timing........................................................................................................................236
11.3.4.1 Timing Assumptions..................................................................................................................236
11.3.4.2 MOVE Instruction Execution Times.........................................................................................237
11.3.4.3 Standard One Operand Instruction Execution Times................................................................238
11.3.4.4 Standard Two Operand Instruction Execution Times................................................................239
11.3.4.5 Miscellaneous Instruction Execution Times..............................................................................240
11.3.4.6 EMAC Instruction Execution Times..........................................................................................241
11.3.4.7 Branch Instruction Execution Times..........................................................................................243
Chapter 12
Enhanced Multiply-Accumulate Unit (EMAC)
12.1 Introduction...................................................................................................................................................................245
12.1.1 Overview........................................................................................................................................................245
12.1.1.1 Introduction to the MAC............................................................................................................246
12.2 Memory Map/Register Definition.................................................................................................................................247
12.2.1 MAC Status Register (MACSR)....................................................................................................................248
12.2.2 Mask Register (MASK).................................................................................................................................250
12.2.3 Accumulator Registers (ACC0-3)..................................................................................................................252
12.2.4 Accumulator Extension Registers (ACCext01, ACCext23)..........................................................................253
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12.3 Functional Description..................................................................................................................................................254
12.3.1 Fractional Operation Mode............................................................................................................................256
12.3.1.1 Rounding....................................................................................................................................257
12.3.1.2 Saving and Restoring the EMAC Programming Model............................................................258
12.3.1.3 MULS/MULU............................................................................................................................259
12.3.1.4 Scale Factor in MAC or MSAC Instructions.............................................................................259
12.3.2 EMAC Instruction Set Summary...................................................................................................................259
12.3.3 EMAC Instruction Execution Times..............................................................................................................260
12.3.4 Data Representation.......................................................................................................................................261
12.3.5 MAC Opcodes................................................................................................................................................261
Chapter 13
System Integration Module (SIM)
13.1 Introduction...................................................................................................................................................................267
13.2 Memory Map and Registers..........................................................................................................................................267
13.2.1 System Options Register 1 (SIM_SOPT1)....................................................................................................269
13.2.2 System Options Register 2 (SIM_SOPT2)....................................................................................................270
13.2.3 System Options Register 3 (SIM_SOPT3)....................................................................................................271
13.2.4 System Options Register 4 (SIM_SOPT4)....................................................................................................272
13.2.5 System Options Register 5 (SIM_SOPT5)....................................................................................................273
13.2.6 System Options Register 6 (SIM_SOPT6)....................................................................................................273
13.2.7 System Options Register 7 (SIM_SOPT7)....................................................................................................274
13.2.8 COP Control Register (SIM_COPC).............................................................................................................275
13.2.9 Service COP Register (SIM_SRVCOP)........................................................................................................276
13.2.10 Oscillator 1 Control Register (SIM_OSC1)...................................................................................................277
13.2.11 Device Identification High Register (SIM_SDIDH).....................................................................................278
13.2.12 Device Identification Low Register (SIM_SDIDL).......................................................................................278
13.2.13 Clock Gate Control Register 1 (SIM_SCGC1)..............................................................................................279
13.2.14 Clock Gate Control Register 2 (SIM_SCGC2)..............................................................................................280
13.2.15 Clock Gate Control Register 3 (SIM_SCGC3)..............................................................................................281
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13.2.16 Clock Gate Control Register 4 (SIM_SCGC4)..............................................................................................282
13.2.17 Clock Gate Control Register 5 (SIM_SCGC5)..............................................................................................283
13.2.18 Clock Gate Control Register 6 (SIM_SCGC6)..............................................................................................284
13.2.19 Clockout Register (SIM_CLKOUT)..............................................................................................................285
13.2.20 Clock Divider 0 Register (SIM_CLKDIV0)..................................................................................................286
13.2.21 Flash Configuration Register (SIM_SPCR)...................................................................................................287
13.2.22 Unique Identification Register (SIM_UIDH3)..............................................................................................288
13.2.23 Unique Identification Register (SIM_UIDH2)..............................................................................................289
13.2.24 Unique Identification Register (SIM_UIDH1)..............................................................................................290
13.2.25 Unique Identification Register (SIM_UIDH0)..............................................................................................290
13.2.26 Unique Identification Register (SIM_UIDMH3)...........................................................................................291
13.2.27 Unique Identification Register (SIM_UIDMH2)...........................................................................................292
13.2.28 Unique Identification Register (SIM_UIDMH1)...........................................................................................292
13.2.29 Unique Identification Register (SIM_UIDMH0)...........................................................................................293
13.2.30 Unique Identification Register (SIM_UIDML3)...........................................................................................294
13.2.31 Unique Identification Register (SIM_UIDML2)...........................................................................................294
13.2.32 Unique Identification Register (SIM_UIDML1)...........................................................................................295
13.2.33 Unique Identification Register (SIM_UIDML0)...........................................................................................296
13.2.34 Unique Identification Register (SIM_UIDL3)...............................................................................................296
13.2.35 Unique Identification Register (SIM_UIDL2)...............................................................................................297
13.2.36 Unique Identification Register (SIM_UIDL1)...............................................................................................298
13.2.37 Unique Identification Register (SIM_UIDL0)...............................................................................................298
Chapter 14
Crossbar Switch
14.1 Introduction...................................................................................................................................................................301
14.1.1 Features..........................................................................................................................................................301
14.2 Memory Map / Register Definition...............................................................................................................................302
14.3 Functional Description..................................................................................................................................................302
14.3.1 General operation...........................................................................................................................................302
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14.3.2 Arbitration......................................................................................................................................................303
14.3.2.1 Arbitration During Undefined Length Bursts............................................................................303
14.3.2.2 Fixed-priority operation.............................................................................................................303
14.3.2.3 Round-robin priority operation..................................................................................................304
14.3.2.4 Priority Elevation.......................................................................................................................304
14.4 Initialization/application information...........................................................................................................................305
Chapter 15
Interrupt Controller (INTC)
15.1 Introduction...................................................................................................................................................................307
15.1.1 Overview........................................................................................................................................................308
15.1.2 Features..........................................................................................................................................................311
15.1.3 Modes of Operation.......................................................................................................................................312
15.2 External Signal Description..........................................................................................................................................312
15.3 Interrupt Request Level and Priority Assignments.......................................................................................................312
15.4 Memory Map and Registers..........................................................................................................................................313
15.4.1 Interrupt Mask Register High (INTC_IMRH)...............................................................................................314
15.4.2 Interrupt Mask Register Low (INTC_IMRL)................................................................................................316
15.4.3 Force Interrupt Register (INTC_FRC)...........................................................................................................320
15.4.4 INTC Programmable Level 6 Priority Registers (INTC_PL6Pn)..................................................................321
15.4.5 INTC Wakeup Control Register (INTC_WCR)............................................................................................322
15.4.6 Set Interrupt Mask Register (INTC_SIMR)...................................................................................................323
15.4.7 Clear Interrupt Mask Register (INTC_CIMR)...............................................................................................324
15.4.8 INTC Set Interrupt Force Register (INTC_SFRC)........................................................................................325
15.4.9 INTC Clear Interrupt Force Register (INTC_CFRC)....................................................................................326
15.4.10 INTC Software IACK Register (INTC_SWIACK).......................................................................................327
15.4.11 INTC Level-n IACK Registers (INTC_LVLnIACK)....................................................................................327
15.5 Functional Description..................................................................................................................................................328
15.5.1 Handling of Non-Maskable Level 7 Interrupt Requests................................................................................328
15.6 Initialization Information..............................................................................................................................................329
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15.7 Application Information................................................................................................................................................329
15.7.1 Emulation of the HCS08's 1-Level IRQ Handling.........................................................................................329
15.7.2 Using INTC_PL6P{7,6} Registers................................................................................................................330
15.7.3 More on Software IACKs..............................................................................................................................331
Chapter 16
Low Leakage Wakeup Unit (LLWU)
16.1 Introduction...................................................................................................................................................................335
16.1.1 Features..........................................................................................................................................................335
16.1.2 Modes of operation........................................................................................................................................336
16.1.2.1 LLS mode...................................................................................................................................336
16.1.2.2 VLLS modes..............................................................................................................................336
16.1.2.3 Non-low leakage modes.............................................................................................................336
16.1.2.4 Debug mode...............................................................................................................................337
16.1.3 Block diagram................................................................................................................................................337
16.2 LLWU signal descriptions............................................................................................................................................338
16.3 Memory map/register definition...................................................................................................................................339
16.3.1 LLWU Pin Enable 1 register (LLWU_PE1)..................................................................................................340
16.3.2 LLWU Pin Enable 2 register (LLWU_PE2)..................................................................................................341
16.3.3 LLWU Pin Enable 3 register (LLWU_PE3)..................................................................................................342
16.3.4 LLWU Pin Enable 4 register (LLWU_PE4)..................................................................................................343
16.3.5 LLWU Module Enable register (LLWU_ME)..............................................................................................344
16.3.6 LLWU Flag 1 register (LLWU_F1)...............................................................................................................346
16.3.7 LLWU Flag 2 register (LLWU_F2)...............................................................................................................347
16.3.8 LLWU Flag 3 register (LLWU_F3)...............................................................................................................349
16.3.9 LLWU Pin Filter 1 register (LLWU_FILT1)................................................................................................351
16.3.10 LLWU Pin Filter 2 register (LLWU_FILT2)................................................................................................352
16.3.11 LLWU Reset Enable register (LLWU_RST).................................................................................................353
16.4 Functional description...................................................................................................................................................354
16.4.1 LLS mode.......................................................................................................................................................354
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16.4.2 VLLS modes..................................................................................................................................................354
16.4.3 Initialization...................................................................................................................................................355
Chapter 17
Reset Control Module (RCM)
17.1 Introduction...................................................................................................................................................................357
17.2 Reset memory map and register descriptions...............................................................................................................357
17.2.1 System Reset Status Register 0 (RCM_SRS0)..............................................................................................357
17.2.2 System Reset Status Register 1 (RCM_SRS1)..............................................................................................359
17.2.3 Reset Pin Filter Control register (RCM_RPFC)............................................................................................360
17.2.4 Reset Pin Filter Width register (RCM_RPFW).............................................................................................361
17.2.5 Mode Register (RCM_MR)...........................................................................................................................363
Chapter 18
System Mode Controller (SMC)
18.1 Introduction...................................................................................................................................................................365
18.2 Modes of operation.......................................................................................................................................................365
18.3 Memory map and register descriptions.........................................................................................................................367
18.3.1 Power Mode Protection register (SMC_PMPROT).......................................................................................367
18.3.2 Power Mode Control register (SMC_PMCTRL)...........................................................................................368
18.3.3 VLLS Control register (SMC_VLLSCTRL).................................................................................................370
18.3.4 Power Mode Status register (SMC_PMSTAT).............................................................................................371
18.4 Functional description...................................................................................................................................................372
18.4.1 Power mode transitions..................................................................................................................................372
18.4.2 Power mode entry/exit sequencing................................................................................................................375
18.4.2.1 Stop mode entry sequence..........................................................................................................376
18.4.2.2 Stop mode exit sequence............................................................................................................377
18.4.2.3 Aborted stop mode entry............................................................................................................377
18.4.2.4 Transition to wait modes............................................................................................................377
18.4.2.5 Transition from stop modes to Debug mode..............................................................................377
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18.4.3 Run modes......................................................................................................................................................377
18.4.3.1 RUN mode.................................................................................................................................378
18.4.3.2 Very-Low Power Run (VLPR) mode........................................................................................378
18.4.3.3 BDM in Run and VLPR Mode..................................................................................................379
18.4.4 Wait modes....................................................................................................................................................379
18.4.4.1 WAIT mode...............................................................................................................................379
18.4.4.2 Very-Low-Power Wait (VLPW) mode......................................................................................380
18.4.4.3 BDM in Wait and VLPW Mode................................................................................................380
18.4.5 Stop modes.....................................................................................................................................................381
18.4.5.1 STOP mode................................................................................................................................381
18.4.5.2 Very-Low-Power Stop (VLPS) mode........................................................................................382
18.4.5.3 BDM in Stop and VLPS Modes.................................................................................................382
18.4.5.4 Low-Leakage Stop (LLS) mode................................................................................................383
18.4.5.5 Very-Low-Leakage Stop (VLLSx) modes.................................................................................383
18.4.5.6 BDM in LLS and VLLSx Modes...............................................................................................384
Chapter 19
Power Management Controller (PMC)
19.1 Introduction...................................................................................................................................................................385
19.2 Features.........................................................................................................................................................................385
19.3 Low-voltage detect (LVD) system................................................................................................................................385
19.3.1 LVD reset operation.......................................................................................................................................386
19.3.2 LVD interrupt operation.................................................................................................................................386
19.3.3 Low-voltage warning (LVW) interrupt operation.........................................................................................386
19.4 I/O retention..................................................................................................................................................................387
19.5 Memory map and register descriptions.........................................................................................................................387
19.5.1 Low Voltage Detect Status And Control 1 register (PMC_LVDSC1)..........................................................387
19.5.2 Low Voltage Detect Status And Control 2 register (PMC_LVDSC2)..........................................................389
19.5.3 Regulator Status And Control register (PMC_REGSC)................................................................................390
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Chapter 20
Voltage Regulator (VREG)
20.1 Introduction...................................................................................................................................................................393
20.1.1 Overview........................................................................................................................................................393
20.1.2 Features..........................................................................................................................................................394
20.1.3 Modes of Operation.......................................................................................................................................395
20.2 Voltage Regulator Module Signal Descriptions...........................................................................................................395
Chapter 21
DMA Controller
21.1 Introduction...................................................................................................................................................................397
21.1.1 Overview........................................................................................................................................................397
21.1.2 Features..........................................................................................................................................................398
21.2 DMA Transfer Overview..............................................................................................................................................399
21.3 Memory Map and Registers..........................................................................................................................................400
21.3.1 DMA Request Control Register (DMA_REQC)...........................................................................................401
21.3.2 Source Address Register (DMA_SARn).......................................................................................................405
21.3.3 Destination Address Register (DMA_DARn)...............................................................................................406
21.3.4 DMA Status Register / Byte Count Register (DMA_DSR_BCRn)...............................................................406
21.3.5 DMA Control Register (DMA_DCRn)..........................................................................................................409
21.4 Functional Description..................................................................................................................................................412
21.4.1 Transfer Requests (Cycle-Steal and Continuous Modes)..............................................................................413
21.4.2 Channel Initialization and Startup..................................................................................................................413
21.4.2.1 Channel Prioritization................................................................................................................413
21.4.2.2 Programming the DMA Controller Module...............................................................................414
21.4.3 Dual-Address Data Transfer Mode................................................................................................................415
21.4.4 Advanced Data Transfer Controls: Auto-Alignment.....................................................................................416
21.4.5 Termination....................................................................................................................................................417
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