Table of Contents
iv
SPG 422 Service Manual (B034000 and above)
Figure 1–31: Modulated pulse and bar for CR 1–35. . . . . . . . . . . . . . . . . .
Figure 1–32: Convergence (horizontal) — Y channel 1–36. . . . . . . . . . . . .
Figure 1–33: Convergence (horizontal) — CB and CR channels 1–36. . . .
Figure 1–34: Convergence (vertical) — Y channel 1–37. . . . . . . . . . . . . . .
Figure 1–35: Convergence (vertical) — CB and CR channels 1–37. . . . . .
Figure 1–36: Active picture markers (part of active picture
timing test signal) — Y channel 1–38. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 1–37: Active picture markers (part of active picture
timing test signal) — CB 1–38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 1–38: Active picture markers (part of active picture
timing test signal) — CR 1–39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 1–39: White bar (part of active picture timing test signal) —
Y channel 1–39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 1–40: White bar (part of active picture timing test signal) —
CB and CR channels 1–40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 1–41: Bowtie sweep — Y channel 1–40. . . . . . . . . . . . . . . . . . . . . . .
Figure 1–42: Bowtie — CB and CR channels 1–41. . . . . . . . . . . . . . . . . . . .
Figure 1–43: Bowtie markers — Y channel 1–41. . . . . . . . . . . . . . . . . . . . .
Figure 1–44: Ramp — Y channel 1–42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 1–45: Ramp — CB channel 1–42. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 1–46: Ramp — CR channel 1–43. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 1–47: Pluge — Y channel 1–43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 1–48: Pluge — CB and CR channels 1–44. . . . . . . . . . . . . . . . . . . . .
Figure 2–1: SPG 422 front panel 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2–2: Various ways genlock input can be configured 2–2. . . . . . . .
Figure 2–3: Illustration of SPG 422 timing 2–4. . . . . . . . . . . . . . . . . . . . . .
Figure 3–1: SPG 422 block diagram 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 3–2: Block diagram of genlock Input <1> 3–11. . . . . . . . . . . . . . . . .
Figure 3–3: Block diagram of burst and sync locks <2> 3–12. . . . . . . . . .
Figure 3–4: Power inductor circuit 3–17. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 3–5: Pulse width modulator and error amplifier circuit 3–19. . . . .
Figure 4–1: Setup to check serial digital video signals 4–11. . . . . . . . . . . . .
Figure 4–2: Various parts of the serial data stream 4–13. . . . . . . . . . . . . . .
Figure 4–3: Setup required to check for an embedded audio signal 4–14.
Figure 4–4: Setup to check accuracy of serial audio signals 4–16. . . . . . . .
Figure 4–5: Setup to check serial audio signal 4–17. . . . . . . . . . . . . . . . . . .
Figure 4–6: Setup to check NTSC analog black outputs 4–20. . . . . . . . . . .