Cadence INCISIVE VERIFICATION IP PORTFOLIO Overview

Brand: Cadence

Model: INCISIVE VERIFICATION IP PORTFOLIO

Type: Overview

OVERVIEW

The Cadence

Incisive

Veriﬁcation IP (VIP) Portfolio is a family

of Universal Veriﬁcation Components (UVCs) and Assertion-

Based VIP that enables metric-driven veriﬁcation of standard

SoC interfaces.

MIPI SLIMbus

MIPI UniPro

OCP

OCP 3.0

PCI

PCI Express

PCI Express Gen3

SAS

SAS 6Gb/s

SATA

SATA 6Gb/s

SDIO

SDXC

Serial RapidIO

SPI-4

USB

USB 3.0

INCISIVE VERIFICATION IP

PORTFOLIO

INCISIVE VIP PORTFOLIO

SINGLE LICENSE INCLUDES:

AMBA

AHB

AMBA APB

AMBA AXI

ATAPI

CAN

DDR2/DDR3

Ethernet

Ethernet 40/100G

FibreChannel

HDMI

JTAG

LIN

MIPI

CSI-2

MIPI DigRF

MIPI D-PHY

MIPI DSI

HIGHLIGHTS

• Proveninmorethan2,000projects

• Conformstoindustry-standardOpenVerication

Methodology (OVM)

• SupportsSystemVerilog(IEEE-1800)ande(IEEE-1647)

languages

• Includesprotocol-specicComplianceManagement

System (CMS)

DEPTH

Constrained-random architecture

Metric-driven environment

Compliance Management System

STANDARD

OVM compliant

Multi-language support:

SystemVerilog and

BREADTH

Support for 30+ protocols

Single portfolio license

CONVENIENCE

One common interface

One common license

One common architecture

QUALITY & PRODUCTIVITY

Superior bug detection

Schedule predictability

Embedded protocol expertise

COMPATIBILITY

Collaboration across projects

Open, multi-vendor standard

www.c ad en ce .c om

INCISIV E VIP POR T FOLIO

VERIFYING HOST MODULES

Incisive Universal Veriﬁcation Components (UVCs) assist in the

vericationofDUThosts(masters,transmitters,etc.)byprovid-

ing active device components to receive data. Monitors are also

provided to perform coverage collection.

HDL Top

Active

Host/Master/

Transmitter

UVC

Monitor

Device/Slave/

Receiver DUT

VERIFYING DEVICE MODULES

IncisiveUVCsperformthevericationofDUTdevices(slaves,

receivers,etc.)byprovidingactivehostcomponentstogener-

ateconstrained-randomstimulusanddrivetheDUT.Monitors

are also provided to perform coverage collection that feeds into

user-denedscoreboards.

HDL Top

Active

Host/Master/

Transmitter

UVC

Data

Scoreboard

Interrupt

Scoreboard

Internal

Signal

Monitor

Device/Slave/

Receiver DUT

ASSERTION-BASED VIP

Assertionsuitesareprovidedforselectedprotocols.Typically

consistingof100to200protocolchecks,thesesuitesprovidea

convenient mechanism for design engineers to participate in the

vericationoftheirmodules.Usingformalanalysistoolssuch

asIncisiveFormalVerier,modulesmaybeveriedwhilethe

designisstillinprocesswithoutrequiringtestbenchcreation.

Incisive Assertion-Based VIP

Interface Constraints

Interface Assertions

DUT

I/F I/F

Whitebox

Assertions

Functional

Assertions

FOCUS ON VERIFICATION

IncisiveVericationIPisindependentlycreatedandtestedagainstexternaldesignIPsourcesto

providefullyobjectivevalidation.ThisfocuspreventsthebugtransferthatcanoccurwhendesignIP

and veriﬁcation IP are co-developed.

“Using Assertion-Based VIP and Incisive Formal

Veriﬁer, we can start veriﬁcation earlier and ﬁnd

bugs much more efﬁciently. Obviously, when

we improve our productivity we accelerate our

schedule.”

Sang Tran

Manager VLSI Technology,

Newport Media

www.c ad en ce .c om

INCISIV E VIP POR T FOLIO

COMPLIANCE MANAGEMENT

SYSTEM (CMS)

The CMS provides a protocol-speciﬁc metric-driven veriﬁcation

environmentthatincludes:

• Executablevericationplanmappedtotheprotocol

speciﬁcation

• LibraryofconstrainedrandomteststoisolateDUT

corner cases

• Integratedcoveragemodeltogradeverication

completeness

• CompliancechecksandmetricstoidentifyDUT

veriﬁcation gaps

Compliance

vPlan

Compliance

Test Suite

Compliance

Coverage Model

Compliance

Checks and Metrics

COMPLIANCE

MANAGEMENT

SYSTEM

PROTOCOL COMPLIANCE AND THE

VERIFICATION PLAN

ProtocolcompliancestartswiththeVericationPlan(vPlan).All

vericationobjectivesarecapturedinthevPlanandcorrelated

to the protocol speciﬁcation on a paragraph by paragraph basis.

Alibraryofconstrained-randomtestsequencesthenstimulates

thedesign-under-testwithmultipleparametercombinationsfor

eachcoveragepointofinterest.Thisresultsinmoreexhaustive

vericationthanrunningalargesetofnon-randomizedvalida-

tion tests.

VERIFICATION PLAN EXAMPLE

Coverage vs. Plan

Correlation to Protocol Speciﬁcation

Resultsfrommultiplesimulationrunsareintegratedand

graphicallydisplayedinthevPlanwindow.Cumulativecoverage

vs. plan is displayed and any coverage gaps are clearly identi-

ed.Thevericationengineerthenadjuststhetestgeneration

constraintstofocusadditionaltestsequencesonthecoverage

points of interest.

Projectmanagementisfacilitatedthroughvariousreportsand

chartswhichmeasureprogressvs.plan.Earlywarningisthus

providedforscheduledeviationsandresourcelimitations.

GAP ANALYSIS EXAMPLE

Coverage Holes Identiﬁed

“We brought up the CMS compliance test suite in

our veriﬁcation environment in just a day. Our team

was impressed with the rapid results. We identi-

ﬁed a number of failures right away and we’re now

working to dramatically expand our regression runs

to take full advantage of the CMS.”

Mike Bartley

Manager, Test and Veriﬁcation

ClearSpeed

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PORTFOLIO LICENSING

Incisive UVCs are licensed collectively as the Incisive VIP

Portfolio.Consequently,asinglelicenseenablesanyoneof

theprotocolsinasinglesimulationrun.ThispreservesyourVIP

investmentasprojectneedschange.Also,newprotocolsare

addedtotheportfolioastheybecomeavailable,furtherincreas-

ingtheportfolio’svalue.

ACCELERATION AND EMULATION

Cadence provides additional VIP for protocol veriﬁcation in

hardwareaccelerationandemulationenvironments,suchas

theIncisivePalladium

and Xtreme

Systems. Transaction-Based

VIPisofferedtosupporttheSystemC

testbenches associated

withhardwareacceleration.High-leveltransactionsefciently

communicatewiththeDUTrunningintheaccelerator.Inthis

environment,youcanachievesimulationspeedsof100xthe

performanceofsoftwaresimulators.

Cadence SpeedBridge

Adaptorsareusedforprotocolverica-

tionduringhardwareemulation.Thesecircuitcardsprovide

thehigh-speedstimulusrequiredtounleashtheperformance

ofemulation.UsingSpeedBridgeAdaptorsandthePalladium

System,youcanachievesimulationspeeds10,000xfasterthan

softwaresimulation.

LEARN MORE

• Aresourcelibraryplussupportandtraininginformationare

availableat:http://www.cadence.com/products/fv/

veriﬁcation_ip

• Hands-ondemosofIncisiveVIPareavailableattheXuropa

onlinecommunity:www.xuropa.com/cadence

• Call1.800.746.6223tospeakwitharepresentative

“We’ve determined that 90% of the risk is in the

chip’s interfaces. If we design the interfaces

incorrectly, it doesn’t matter if we get the rest

of the chip right. This is especially true with PCI

Express since it’s such a complex protocol. The bot-

tom line for us is that the choice we made to go

with proven IP that’s easy to get up and running is

just good, solid common sense.”

Jim O’Connor,

VP of Engineering

iVivity

Cadence INCISIVE VERIFICATION IP PORTFOLIO Overview

Cadence INCISIVE VERIFICATION IP PORTFOLIO Overview

Cadence INCISIVE VERIFICATION IP PORTFOLIO Overview

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