ADV7850
Fast Switching 4:1 HDMI 1.4 Receiver
With 3D-Comb Decoder and Digitizer
HARDWARE
MANUAL
Rev. A
May 2012
ADV7850
Rev. A May 2012
2
TABLE OF CONTENTS
1 INTRODUCTION TO ADV7850 HARDWARE MANUAL ................................................................................................ 11
1.1 DESCRIPTION OF THE HARDWARE MANUAL ...................................................................................................................................... 11
1.2 COPYRIGHT INFORMATION .................................................................................................................................................................. 11
1.3 DISCLAIMER ........................................................................................................................................................................................... 11
1.4 TRADEMARK AND SERVICE MARK NOTICE......................................................................................................................................... 11
1.5 NUMBER NOTATIONS ........................................................................................................................................................................... 11
1.6 REGISTER ACCESS CONVENTIONS ....................................................................................................................................................... 11
1.7 ACRONYMS AND ABBREVIATIONS ....................................................................................................................................................... 11
1.8 CONTROL DESCRIPTION ....................................................................................................................................................................... 13
1.9 REFERENCES ........................................................................................................................................................................................... 14
2 INTRODUCTION ................................................................................................................................................................. 15
2.1 ANALOG FRONT END ............................................................................................................................................................................ 15
2.2 STANDARD DEFINITION PROCESSOR ................................................................................................................................................... 16
2.3 HDMI RECEIVER .................................................................................................................................................................................. 16
2.4 COMPONENT PROCESSOR ..................................................................................................................................................................... 16
2.5 AUDIO CODEC .................................................................................................................................................................................... 17
2.6 MAIN FEATURES OF ADV7850 ............................................................................................................................................................ 17
2.6.1 Analog Front End .............................................................................................................................................................. 17
2.6.2 HDMI Receiver .................................................................................................................................................................. 17
2.6.3 Composite and S-Video Processing ................................................................................................................................... 17
2.6.4 Component Video Processing ............................................................................................................................................ 18
2.6.5 RGB Graphics Processing .................................................................................................................................................. 18
2.6.6 Audio CODEC ................................................................................................................................................................... 18
2.6.7 Additional Features ........................................................................................................................................................... 18
2.7 FUNCTIONAL BLOCK DIAGRAM ........................................................................................................................................................... 19
2.8 PIN DESCRIPTION .................................................................................................................................................................................. 20
3 GLOBAL CONTROL REGISTERS........................................................................................................................................ 29
3.1 ADV7850 REVISION IDENTIFICATION ................................................................................................................................................ 29
3.2 POWER-DOWN CONTROLS ................................................................................................................................................................... 29
3.2.1 Primary Power-down Controls ......................................................................................................................................... 29
3.2.2 Secondary Power-down Controls ...................................................................................................................................... 29
3.2.3 Power-down Mode ............................................................................................................................................................ 30
3.2.4 EDID Support in Power-off Mode.................................................................................................................................... 31
3.2.5 ADC Power-down Control ................................................................................................................................................ 32
3.2.6 DDC and VGA Pins Power Down .................................................................................................................................... 33
3.3 RESET CONTROLS AND GLOBAL PIN CONTROLS ................................................................................................................................. 33
3.3.1 Reset Pin ............................................................................................................................................................................ 33
3.3.2 Reset Controls .................................................................................................................................................................... 33
3.3.3 Tristate Pins ....................................................................................................................................................................... 34
3.3.4 ADC Phase Control ........................................................................................................................................................... 34
3.4 ADC-HDMI SIMULTANEOUS MODE .................................................................................................................................................. 34
4 PRIMARY MODE AND VIDEO STANDARD .................................................................................................................... 36
4.1 PRIMARY MODE AND VIDEO STANDARD CONTROLS ........................................................................................................................ 36
4.1.1 Setting the Vertical Frequency .......................................................................................................................................... 40
4.2 STANDARD CONFIGURATION FOR SDP-HDMI AUDIO SIMULTANEOUS MODE ............................................................................. 40
4.3 PRIMARY MODE AND VIDEO STANDARD CONFIGURATION FOR HDMI FREE RUN ....................................................................... 41
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5 ANALOG FRONT END ......................................................................................................................................................... 42
5.1 ADC SAMPLING CLOCK ....................................................................................................................................................................... 42
5.2 ADCS AND VOLTAGE CLAMPS ............................................................................................................................................................ 42
5.2.1 Analog Input Hardware Configuration ............................................................................................................................ 42
5.2.2 Clamp Operation ............................................................................................................................................................... 43
5.2.3 SDP Clamp Operation ....................................................................................................................................................... 43
5.3 ANALOG INPUT MUXING ..................................................................................................................................................................... 45
5.3.1 Analog Input Routing Recommendation .......................................................................................................................... 45
5.4 AUTOMATIC INPUT MUXING SELECTION ........................................................................................................................................... 46
5.5 MANUAL INPUT MUXING OVERVIEW ................................................................................................................................................. 47
5.5.1 Manual Input Muxing ...................................................................................................................................................... 47
5.6 VIDEO OUTPUT MUX ........................................................................................................................................................................... 49
5.7 SYNC1-3 INPUT CONTROL .................................................................................................................................................................. 50
5.7.1 Automatic Synchronization Configuration ...................................................................................................................... 51
5.7.2 Manual Synchronization Configuration .......................................................................................................................... 51
5.8 SYNCHRONIZATION SLICERS ................................................................................................................................................................ 52
5.8.1 Synchronization Filter Stage ............................................................................................................................................. 52
5.8.2 Sync Stripper Slice Level .................................................................................................................................................... 53
5.8.3 D-Terminal Connector ...................................................................................................................................................... 53
5.8.4 TRI 1-8 Input Resistor Selection ....................................................................................................................................... 53
5.8.5 Trilevel Input Controls ...................................................................................................................................................... 54
5.8.6 Trilevel Slicer Operation ................................................................................................................................................... 54
5.8.7 Bilevel/Trilevel Selection ................................................................................................................................................... 56
5.8.8 Trilevel Slicer Readbacks ................................................................................................................................................... 57
5.8.9 Programming Trilevel Slicers ............................................................................................................................................ 59
5.8.9.1 Upper Slice Levels ................................................................................................................................................................... 59
5.8.9.2 Lower Slice Levels .................................................................................................................................................................. 62
5.8.10 Fast Blanking Configuration ........................................................................................................................................ 64
5.8.11 SCART Source Selection Control ................................................................................................................................. 65
5.8.12 SCART Fast Blank Timing ........................................................................................................................................... 65
5.9 ANTI ALIASING FILTERS ....................................................................................................................................................................... 66
5.9.1 Description ......................................................................................................................................................................... 66
6 STANDARD DEFINITION PROCESSOR ........................................................................................................................... 69
6.1 SDP BLOCK ............................................................................................................................................................................................ 69
6.2 SDP SYNCHRONIZATION PROCESSING ................................................................................................................................................ 69
6.3 SDP GENERAL SETUP ............................................................................................................................................................................ 70
6.3.1 Autodetection of SDP Modes ............................................................................................................................................ 70
6.3.2 Pedestal Configuration in SDP Modes .............................................................................................................................. 72
6.4 SDP STATUS REGISTERS ....................................................................................................................................................................... 73
6.4.1 SDP Autodetection Result ................................................................................................................................................. 73
6.4.2 SDP Video Detection ......................................................................................................................................................... 73
6.4.3 Input Status ....................................................................................................................................................................... 74
6.4.4 Macrovision Status ............................................................................................................................................................ 77
6.4.5 Synctip Noise Measurement, Noisy and Very Noisy Signal Detection ............................................................................ 78
6.4.6 Additional SDP Status Registers ....................................................................................................................................... 79
6.5 SDP COLOR CONTROLS ........................................................................................................................................................................ 80
6.5.1 Contrast ............................................................................................................................................................................. 81
6.5.2 Brightness ........................................................................................................................................................................... 81
6.5.3 Saturation .......................................................................................................................................................................... 81
6.5.4 Hue..................................................................................................................................................................................... 81
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6.6 SDP GAIN OPERATION ......................................................................................................................................................................... 81
6.6.1 SDP Luma Gain ................................................................................................................................................................ 82
6.6.2 Chroma Gain ..................................................................................................................................................................... 84
6.6.3 Peak White Feature ........................................................................................................................................................... 85
6.6.4 Peak Chroma ..................................................................................................................................................................... 86
6.6.5 Color Kill............................................................................................................................................................................ 86
6.7 3D COMB ............................................................................................................................................................................................... 87
6.7.1 3D Comb Activation ......................................................................................................................................................... 87
6.7.2 3D Comb Sensitivity .......................................................................................................................................................... 92
6.8 Y SHAPING FILTER ................................................................................................................................................................................ 92
6.8.1 Input Shaping Filter Enables ........................................................................................................................................... 101
6.9 CHROMA SHAPING FILTER ................................................................................................................................................................. 103
6.10 SPLIT FILTER SELECTION ............................................................................................................................................................... 107
6.11 IF FILTER COMPENSATION ............................................................................................................................................................ 108
6.12 LUMA TRANSIENT IMPROVEMENT AND CHROMA TRANSIENT IMPROVEMENT ....................................................................... 109
6.13 RINGING REDUCTION .................................................................................................................................................................... 114
6.14 HORIZONTAL AND VERTICAL PEAKING ....................................................................................................................................... 115
6.14.1 Horizontal Peaking..................................................................................................................................................... 115
6.14.2 Vertical Peaking ......................................................................................................................................................... 118
6.15 FRAME SYNCHRONIZATION (FRAME TIME BASE CORRECTION) ............................................................................................... 121
6.16 FREE RUN MODE ............................................................................................................................................................................ 122
6.17 LETTERBOX DETECTION ................................................................................................................................................................ 123
6.17.1 Detection at Start of Field .......................................................................................................................................... 124
6.17.2 Detection at End of Field ............................................................................................................................................ 124
6.17.3 Detection at Mid Range.............................................................................................................................................. 124
6.18 SDP SYNCHRONIZATION OUTPUT SIGNALS ................................................................................................................................ 125
6.18.1 HSync Timing Configuration ..................................................................................................................................... 125
6.18.2 VSync and FIELD Configuration............................................................................................................................... 126
6.18.3 DE Configuration ....................................................................................................................................................... 129
6.18.4 CSync Signal Configuration ....................................................................................................................................... 131
6.18.5 Manual Color Space Conversion Matrix ................................................................................................................... 132
6.18.5.1 CSC Manual Programming ............................................................................................................................................... 135
7 HDMI RECEIVER ................................................................................................................................................................ 136
7.1 MODES OF OPERATION ....................................................................................................................................................................... 136
7.1.1 HDMI Mux Mode ........................................................................................................................................................... 136
7.1.2 HDMI Non-Mux Mode ................................................................................................................................................... 136
7.2 +5 V CABLE DETECT ........................................................................................................................................................................... 137
7.3 HOT PLUG ASSERT .............................................................................................................................................................................. 138
7.4 E-EDID/REPEATER CONTROLLER ..................................................................................................................................................... 141
7.5 E-EDID DATA CONFIGURATION ...................................................................................................................................................... 142
7.5.1 E-EDID Support for Cable Supply Mode ........................................................................................................................ 144
7.6 5 V SUPPLY .......................................................................................................................................................................................... 144
7.7 TRANSITIONING FROM CABLE SUPPLY MODE ................................................................................................................................. 144
7.8 SPI INTERFACE .................................................................................................................................................................................... 145
7.8.1 SPI EEPROM Data Structure ......................................................................................................................................... 146
7.9 STRUCTURE OF INTERNAL E-EDID FOR PORT A ............................................................................................................................. 147
7.10 STRUCTURE OF INTERNAL E-EDID OF PORTS B, C, AND D ....................................................................................................... 147
7.11 SPA CONFIGURATION ................................................................................................................................................................... 150
7.12 EXTERNAL E-EDID ....................................................................................................................................................................... 150
7.13 TMDS EQUALIZATION .................................................................................................................................................................. 150
7.13.1 Equalizer Read back ................................................................................................................................................... 150
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7.13.2 Manual Operation ...................................................................................................................................................... 150
7.14 PORT SELECTION ............................................................................................................................................................................ 151
7.15 FAST SWITCHING AND BACKGROUND PORT SELECTION ........................................................................................................... 151
7.16 TMDS CLOCK ACTIVITY DETECTION ......................................................................................................................................... 153
7.16.1 Clock and Data Termination Control ....................................................................................................................... 154
7.17 TMDS MEASUREMENT ................................................................................................................................................................. 155
7.17.1 TMDS Measurement After TMDS PLL ..................................................................................................................... 155
7.18 DEEP COLOR MODE SUPPORT ...................................................................................................................................................... 158
7.19 VIDEO FIFO ................................................................................................................................................................................... 160
7.20 PIXEL REPETITION ......................................................................................................................................................................... 161
7.21 ARC SUPPORT ................................................................................................................................................................................ 163
7.22 3D VIDEO SUPPORT ................................................................................................................................................................ 165
7.23 HDCP SUPPORT ............................................................................................................................................................................ 165
7.23.1 HDCP Decryption Engine .......................................................................................................................................... 165
7.23.2 Internal HDCP Key OTP ROM ................................................................................................................................. 167
7.23.3 HDCP Keys Access Flags ............................................................................................................................................ 167
7.24 HDMI SYNCHRONIZATION PARAMETERS ................................................................................................................................... 169
7.24.1 Horizontal Filter and Measurements ........................................................................................................................ 169
7.24.2 Primary Port Horizontal Filter Measurements ......................................................................................................... 169
7.24.3 Background Port Horizontal Filter Measurements ................................................................................................... 171
7.24.4 Horizontal Filter Locking Mechanism ....................................................................................................................... 172
7.24.5 Vertical Filters and Measurements ............................................................................................................................ 172
7.24.6 Primary Port Vertical Filter Measurements .............................................................................................................. 172
7.24.7 Background Port Vertical Filter Measurements ........................................................................................................ 176
7.24.8 Vertical Filter Locking Mechanism ............................................................................................................................ 177
7.25 AUDIO CONTROL AND CONFIGURATION .................................................................................................................................... 177
7.25.1 Audio DPLL ................................................................................................................................................................ 178
7.25.2 Locking Mechanism .................................................................................................................................................... 178
7.25.3 ACR Parameters Loading Method ............................................................................................................................. 178
7.25.4 Audio DPLL Coast Feature ........................................................................................................................................ 179
7.26 AUDIO FIFO .................................................................................................................................................................................. 179
7.27 AUDIO PACKET TYPE FLAGS ......................................................................................................................................................... 181
7.28 AUDIO OUTPUT INTERFACE ......................................................................................................................................................... 183
7.28.1 I2S/SPDIF Audio Interface and Output Controls ..................................................................................................... 184
7.28.2 DSD Audio Interface and Output Controls ............................................................................................................... 187
7.28.3 DST Audio Interface and Output Controls ............................................................................................................... 189
7.28.4 HBR Interface and Output Controls .......................................................................................................................... 190
7.29 MCLKOUT SETTING .................................................................................................................................................................... 191
7.30 AUDIO CHANNEL MODE ............................................................................................................................................................... 191
7.31 AUDIO MUTING ............................................................................................................................................................................. 192
7.31.1 Audio Mute Configuration ........................................................................................................................................ 192
7.31.2 Internal Mute Status .................................................................................................................................................. 194
7.31.3 AV Mute Status .......................................................................................................................................................... 194
7.31.4 Audio Stream with Incorrect Parity Error ................................................................................................................. 194
7.32 AUDIO CLOCK REGENERATION PARAMETERS............................................................................................................................. 195
7.32.1 ACR Parameters Readbacks ....................................................................................................................................... 195
7.32.2 Monitoring ACR Parameters ..................................................................................................................................... 195
7.33 CHANNEL STATUS .......................................................................................................................................................................... 196
7.33.1 Validity Status Flag .................................................................................................................................................... 196
7.33.2 General Control and Mode Information ................................................................................................................... 197
7.33.3 Category Code ............................................................................................................................................................ 198
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7.33.4 Source Number and Channel Number ...................................................................................................................... 198
7.33.5 Sampling and Frequency Accuracy ............................................................................................................................ 198
7.33.6 Word Length ............................................................................................................................................................... 199
7.33.7 Channel Status Copyright Value Assertion ............................................................................................................... 199
7.33.8 Monitoring Change of Audio Sampling Frequency ................................................................................................... 200
7.34 PACKETS AND INFOFRAMES REGISTERS ....................................................................................................................................... 200
7.34.1 InfoFrames Registers .................................................................................................................................................. 201
7.34.2 InfoFrame Collection Mode ....................................................................................................................................... 201
7.34.3 InfoFrame Checksum Error Flags .............................................................................................................................. 201
7.34.4 AVI InfoFrame Registers ............................................................................................................................................ 202
7.34.5 Audio InfoFrame Registers ......................................................................................................................................... 203
7.34.6 SPD InfoFrame Registers ............................................................................................................................................ 204
7.34.7 MPEG Source InfoFrame Registers ............................................................................................................................ 204
7.34.8 Vendor Specific InfoFrame Registers ......................................................................................................................... 205
7.34.9 Multiple InfoFrames Support ( THX Media Directorâ„¢) ............................................................................................ 206
7.35 PACKET REGISTERS ........................................................................................................................................................................ 207
7.35.1 ACP Packet Registers .................................................................................................................................................. 207
7.35.2 ISRC Packet Registers ................................................................................................................................................. 208
7.35.3 Gamut Metadata Packets ........................................................................................................................................... 210
7.36 CUSTOMIZING PACKET/INFOFRAME STORAGE REGISTERS ........................................................................................................ 211
7.37 BACKGROUND PORT INFOFRAME AND PACKET SUPPORT ........................................................................................................... 213
7.38 REPEATER SUPPORT ....................................................................................................................................................................... 214
7.38.1 Repeater Routines Performed by the E-EDID/Repeater Controller .......................................................................... 214
7.38.2 Repeater Actions Required by External Controller ................................................................................................... 215
7.38.3 HDCP Registers Available in Repeater Map ............................................................................................................. 216
7.39 INTERFACE TO DCM SECTION ..................................................................................................................................................... 221
7.40 COLOR SPACE INFORMATION SENT TO THE CP SECTION .......................................................................................................... 222
7.41 STATUS REGISTERS ......................................................................................................................................................................... 222
7.42 HDMI RECEIVER SECTION RESET STRATEGY .............................................................................................................................. 225
7.43 HDMI PACKET DETECTION FLAG RESET .................................................................................................................................... 225
8 DECIMATION CONTROLS, COLOR SPACE CONVERSION, AND COLOR CONTROLS ......................................... 226
8.1 DCM CONFIGURATION ..................................................................................................................................................................... 226
8.2 MANUAL FILTER COEFFICIENT PROGRAMMING ............................................................................................................................... 227
8.2.1 DCM Channel Power Down Control ............................................................................................................................. 229
8.3 COLOR SPACE CONVERSION MATRIX ............................................................................................................................................... 230
8.3.1 CP CSC Selection ............................................................................................................................................................. 230
8.3.2 Selecting Automatic or Manual CP CSC Conversion Mode .......................................................................................... 231
8.3.3 Automatic Color Space Conversion Matrix.................................................................................................................... 231
8.3.4 Manual Color Space Conversion Matrix ........................................................................................................................ 233
8.3.4.1 CSC Manual Programming .................................................................................................................................................... 236
8.3.4.2 CSC Example ......................................................................................................................................................................... 237
8.3.5 CSC in Pass-through Mode ............................................................................................................................................. 238
8.4 COLOR CONTROLS .............................................................................................................................................................................. 238
9 COMPONENT PROCESSOR .............................................................................................................................................. 241
9.1 INTRODUCTION TO COMPONENT PROCESSOR ................................................................................................................................. 241
9.2 CLAMP OPERATION ............................................................................................................................................................................ 242
9.3 CP GAIN OPERATION ........................................................................................................................................................................... 244
9.3.1 Features of Manual Gain Control ................................................................................................................................... 244
9.3.2 Features of Automatic Gain Control .............................................................................................................................. 244
9.3.3 Manual Gain and Automatic Gain Control Selection ................................................................................................... 244
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9.3.4 Manual Gain Control ...................................................................................................................................................... 245
9.3.5 Manual Gain Filter Mode ............................................................................................................................................... 247
9.3.6 Automatic Gain Control ................................................................................................................................................. 247
9.3.6.1 Readback Signals from AGC Block ....................................................................................................................................... 249
9.4 CP OFFSET BLOCK .............................................................................................................................................................................. 252
9.5 CP DATA PATH FOR ANALOG MODE ................................................................................................................................................ 253
9.5.1 Pregain Block ................................................................................................................................................................... 253
9.6 SYNC PROCESSED BY CP SECTION ..................................................................................................................................................... 258
9.6.1 Sync Extracted by Sync Slicer Section ............................................................................................................................. 258
9.6.2 External Sync and Sync from HDMI Section ................................................................................................................. 259
9.6.2.1 Signals Routing to Synchronization Channels ....................................................................................................................... 259
9.6.2.2 XTAL Clock Registering and Glitch Rejection Filter ............................................................................................................ 260
9.6.2.3 Signal Routed to SSPD Blocks .............................................................................................................................................. 261
9.6.3 Final Sync Muxing Stage ................................................................................................................................................. 262
9.7 SYNCHRONIZATION PROCESSING CHANNEL MUX ........................................................................................................................... 262
9.7.1 Synchronization Source Polarity Detector ...................................................................................................................... 263
9.7.1.1 SSPD Readback Signals ......................................................................................................................................................... 267
9.7.2 Standard Detection and Identification ........................................................................................................................... 271
9.7.3 Detailed Mechanism of STDI Block Horizontal/Vertical Lock Mechanism .................................................................. 274
9.7.3.1 STDI Horizontal Locking Operation ...................................................................................................................................... 274
9.7.3.2 STDI Vertical Locking........................................................................................................................................................... 274
9.7.3.3 STDI Usage............................................................................................................................................................................ 277
9.7.3.4 STDI Readback Values for SD, PR, and HD ......................................................................................................................... 277
9.7.3.5 STDI Readback Values for Graphics Standards .................................................................................................................... 278
9.8 CP OUTPUT SYNCHRONIZATION SIGNAL POSITIONING ................................................................................................................. 278
9.8.1 CP Primary Synchronization Signals .............................................................................................................................. 279
9.8.2 HSync Timing Controls ................................................................................................................................................... 280
9.8.3 VSync Timing Controls ................................................................................................................................................... 283
9.8.4 DE Timing Controls ........................................................................................................................................................ 285
9.8.5 FIELD Timing Controls .................................................................................................................................................. 287
9.8.6 HCOUNT Timing Control .............................................................................................................................................. 296
9.9 CP DATA PROCESSING DELAY CONTROLS ....................................................................................................................................... 296
9.10 CP HORIZONTAL LOCK STATUS ................................................................................................................................................... 296
9.11 NOISE AND CALIBRATION ............................................................................................................................................................. 298
9.11.1 Measurement Window ............................................................................................................................................... 298
9.11.2 Noise Measurement .................................................................................................................................................... 298
9.11.3 Calibration Measurement .......................................................................................................................................... 299
9.12 FREE RUN MODE ............................................................................................................................................................................ 299
9.12.1 Free Run Mode Thresholds ........................................................................................................................................ 299
9.12.1.1 Horizontal Free Run Conditions ....................................................................................................................................... 299
9.12.2 Vertical Run Conditions............................................................................................................................................. 301
9.12.3 Free Run Default Color Output ................................................................................................................................. 303
9.13 CP STATUS ..................................................................................................................................................................................... 304
9.14 AUTO GRAPHICS MODE ................................................................................................................................................................ 305
9.14.1 Primary Auto Graphics Controls ............................................................................................................................... 305
9.14.2 Graphics Controls ....................................................................................................................................................... 308
10 VBI DATA PROCESSOR .................................................................................................................................................... 310
10.1 VDP CONFIGURATION .................................................................................................................................................................. 310
10.1.1 VDP Default Configuration ....................................................................................................................................... 310
10.1.2 VDP Manual Configuration ...................................................................................................................................... 312
10.2 TELETEXT SYSTEM IDENTIFICATION ............................................................................................................................................ 313
10.3 VDP DECODED DATA READBACK REGISTERS ............................................................................................................................ 314
10.3.1 Teletext Readback Registers ....................................................................................................................................... 314
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10.3.2 CGMS and WSS Readback Registers ......................................................................................................................... 314
10.3.3 Closed Captioning Readback Registers ...................................................................................................................... 315
10.3.4 VITC Readback Registers ........................................................................................................................................... 316
10.3.5 VPS, PDC, UTC, Gemstar and CGMS Type B Readback Registers .......................................................................... 317
10.4 READBACK REGISTERS ................................................................................................................................................................... 320
10.5 USER INTERFACE FOR I
2
C READBACK REGISTERS ....................................................................................................................... 320
10.5.1 VDP Register Readback Protocols .............................................................................................................................. 320
10.5.1.1 Data Available Updates .................................................................................................................................................... 320
10.5.2 Content Based Data Update ...................................................................................................................................... 321
10.6 INTERRUPT BASED READING OF VDP READBACK REGISTERS ................................................................................................... 321
10.7 SPI READBACK REGISTERS ........................................................................................................................................................... 322
10.7.1 SPI Data Formats – Slave Mode ............................................................................................................................... 322
10.7.2 SPI Data Formats – Master Mode ........................................................................................................................... 324
10.7.3 Configuring Master Mode on the SPI Port ................................................................................................................ 326
10.7.4 SPI VDP Controls and Readbacks ............................................................................................................................ 328
10.7.5 ADV7850 VDP Interrupt Generation ....................................................................................................................... 330
11 AUDIO CODEC ................................................................................................................................................................... 333
11.1 AUDIO CODEC OVERVIEW ............................................................................................................................................................. 333
11.2 ANALOG AUDIO MUX FUNCTIONALITY ..................................................................................................................................... 333
11.2.1 Analog Audio ADC Input Selection ........................................................................................................................... 334
11.2.2 Analog Audio Mux Output Selection ........................................................................................................................ 334
11.2.3 Analog Audio Mux Input/Mux Output Configuration Overview ............................................................................ 335
11.3 AUDIO CODEC FUNCTIONALITY ................................................................................................................................................... 336
11.3.1 Audio PLL ................................................................................................................................................................... 336
11.3.2 VREF_AUDIO, FILTA and FILTD (Location) ......................................................................................................... 337
11.3.3 DAC and Headphone Outputs ................................................................................................................................... 338
11.3.3.1 Audio Codec DAC Output ................................................................................................................................................ 338
11.3.3.2 Audio Codec Headphone Output ...................................................................................................................................... 338
11.3.4 Volume Controls ......................................................................................................................................................... 340
11.4 AUDIO POWER UP/DOWN CONTROLS ........................................................................................................................................ 341
12 MEMORY CONTROLLER .................................................................................................................................................. 344
12.1 MEMORY REQUIREMENTS ............................................................................................................................................................. 344
12.2 GENERAL CONTROLS ..................................................................................................................................................................... 344
12.2.1 Reset ............................................................................................................................................................................ 344
12.2.2 Output Enables ........................................................................................................................................................... 344
12.3 DRIVE STRENGTH CONTROLS ....................................................................................................................................................... 345
12.4 DDR2 BIST TEST ............................................................................................................................................................................. 345
12.5 EXTERNAL MEMORY LAYOUT GUIDELINES .................................................................................................................................. 347
13 HDMI TRANSMITTER ....................................................................................................................................................... 349
13.1 GENERAL OPERATION ................................................................................................................................................................... 349
13.2 GENERAL CONTROLS ..................................................................................................................................................................... 349
13.3 HDMI DVI SELECTION ................................................................................................................................................................ 350
13.4 AV MUTE ....................................................................................................................................................................................... 351
13.5 TX SQUELCH FEATURE .................................................................................................................................................................. 351
13.6 SOURCE PRODUCT DESCRIPTION INFOFRAME ............................................................................................................................ 352
13.7 SPARE PACKETS .............................................................................................................................................................................. 353
13.8 SYSTEM MONITORING ................................................................................................................................................................... 354
13.8.1 General Status and Interrupts .................................................................................................................................... 354
13.9 EDID/HDCP CONTROLLER STATUS ........................................................................................................................................... 355
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13.10 EDID/HDCP CONTROLLER ERROR CODES ................................................................................................................................ 355
13.11 VIDEO SETUP .................................................................................................................................................................................. 356
13.11.1 Input Format .............................................................................................................................................................. 356
13.11.2 Video Mode Detection ................................................................................................................................................ 356
13.11.3 Pixel Repetition ........................................................................................................................................................... 357
13.11.4 Video Related Packets and InfoFrames ..................................................................................................................... 358
13.11.5 AVI InfoFrame ........................................................................................................................................................... 358
13.11.6 MPEG InfoFrame ....................................................................................................................................................... 359
13.11.7 Gamut Metadata ........................................................................................................................................................ 360
13.12 AUDIO SETUP ................................................................................................................................................................................. 362
13.12.1 Input Format .............................................................................................................................................................. 362
13.12.2 I2S Audio .................................................................................................................................................................... 363
13.12.3 SPDIF Audio ............................................................................................................................................................... 368
13.12.4 DSD Audio.................................................................................................................................................................. 369
13.12.5 HBR Audio ................................................................................................................................................................. 369
13.12.6 N and CTS Parameters............................................................................................................................................... 370
13.12.7 N Parameter ............................................................................................................................................................... 371
13.12.8 CTS Parameter ........................................................................................................................................................... 371
13.12.9 Recommended N and Expected CTS Values ............................................................................................................. 371
13.12.10 Audio Sample Packets ................................................................................................................................................ 373
13.12.11 Audio InfoFrame ........................................................................................................................................................ 377
13.12.12 Audio Content Protection Packet .............................................................................................................................. 378
13.12.13 ISRC Packet ................................................................................................................................................................ 379
13.13 EDID HANDLING .......................................................................................................................................................................... 380
13.13.1 Reading the EDID ...................................................................................................................................................... 380
13.13.2 EDID Definitions ........................................................................................................................................................ 381
13.13.3 Additional Segments................................................................................................................................................... 381
13.13.4 EDID_TRIES Control ................................................................................................................................................. 382
13.13.5 EDID_REREAD Control ............................................................................................................................................ 382
13.14 HDCP HANDLING ......................................................................................................................................................................... 382
13.14.1 One Sink And No Upstream Devices ......................................................................................................................... 382
13.14.2 Multiple Sinks and No Upstream Devices ................................................................................................................. 384
13.14.3 Software Implementation ........................................................................................................................................... 385
13.14.4 AV Mute ..................................................................................................................................................................... 386
14 REGISTER ACCESS AND SERIAL PORTS DESCRIPTION ............................................................................................ 388
14.1 MAIN I
2
C PORT .............................................................................................................................................................................. 388
14.1.1 Register Access ............................................................................................................................................................ 388
14.1.2 Protocol for Main I
2
C Port ......................................................................................................................................... 389
14.2 DDC PORTS ................................................................................................................................................................................... 389
14.2.1 I
2
C Protocols for Access to the Internal E-EDID ....................................................................................................... 389
14.2.2 I
2
C Protocols for Access to HDCP Registers ............................................................................................................... 390
14.2.3 DDC Port A ................................................................................................................................................................ 390
14.2.4 DDC Port B ................................................................................................................................................................. 390
14.2.5 DDC Port C ................................................................................................................................................................ 391
14.2.6 DDC Port D ................................................................................................................................................................ 391
15 INTERRUPTS ...................................................................................................................................................................... 392
15.1 INTERRUPT ARCHITECTURE OVERVIEW ...................................................................................................................................... 392
15.2 INTERRUPT PINS ............................................................................................................................................................................. 392
15.2.1 Interrupt Duration ..................................................................................................................................................... 392
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15.2.2 Interrupt Drive Level .................................................................................................................................................. 392
15.2.3 Interrupt Manual Assertion ....................................................................................................................................... 393
15.2.4 Multiple Interrupt Events ........................................................................................................................................... 394
15.3 RX SECTION .................................................................................................................................................................................... 394
15.4 DESCRIPTION OF RX INTERRUPT BITS .......................................................................................................................................... 398
15.4.1 General Operation ...................................................................................................................................................... 398
15.4.2 Analog/HDMI Video Mode ....................................................................................................................................... 398
15.4.3 Macrovision Detection ............................................................................................................................................... 398
15.4.4 VDP Operation ........................................................................................................................................................... 398
15.4.5 HDMI Only Mode ...................................................................................................................................................... 398
15.5 ADDITIONAL EXPLANATIONS ....................................................................................................................................................... 400
15.5.1 afe_interrupt_raw ...................................................................................................................................................... 400
15.5.2 stdi_data_valid_raw .................................................................................................................................................. 402
15.5.3 cp_lock, cp_unlock ...................................................................................................................................................... 402
15.5.4 Video 3D Detection .................................................................................................................................................... 403
15.5.5 HDMI Interrupts Validity Checking Process ............................................................................................................. 403
15.5.5.1 Group 1 HDMI Interrupts ................................................................................................................................................. 403
15.5.5.2 Group 2 HDMI Interrupts ................................................................................................................................................. 403
15.5.5.3 Group 3 HDMI Interrupts ................................................................................................................................................. 403
15.5.6 Storing Masked Interrupts ......................................................................................................................................... 404
15.5.6.1 Interrupt Status Registers .................................................................................................................................................. 404
15.5.7 Processing Analog Front End Interrupts .................................................................................................................... 425
15.6 TX CORE .......................................................................................................................................................................................... 426
15.6.1 Interrupt Architecture Overview ................................................................................................................................ 426
15.6.1.1 Interrupt Bits ..................................................................................................................................................................... 427
15.6.1.2 Interrupt Mask Bits ........................................................................................................................................................... 428
16 APPENDIX A ....................................................................................................................................................................... 429
16.1 PCB LAYOUT RECOMMENDATIONS ............................................................................................................................................. 429
16.2 ANALOGUE INTERFACE INPUTS .................................................................................................................................................... 429
16.3 POWER SUPPLY BYPASSING ........................................................................................................................................................... 429
16.3.1 Power Supply Sequencing ........................................................................................................................................... 430
16.3.1.1 Power Up Sequence .......................................................................................................................................................... 430
16.3.1.2 Power Down Sequence ..................................................................................................................................................... 430
16.4 DIGITAL OUTPUTS (DATA AND CLOCKS) .................................................................................................................................... 431
16.5 DIGITAL INPUTS ............................................................................................................................................................................. 431
16.6 XTAL AND LOAD CAP VALUE SELECTION .................................................................................................................................. 431
17 APPENDIX B ....................................................................................................................................................................... 433
17.1 ADV7850 TYPICAL CONNECTION DIAGRAMS ........................................................................................................................... 433
18 APPENDIX C ....................................................................................................................................................................... 440
18.1 PACKAGE OUTLINE DRAWING ..................................................................................................................................................... 440
18.2 ORDERING GUIDE .......................................................................................................................................................................... 440
19 APPENDIX D ....................................................................................................................................................................... 441
19.1 RECOMMENDED UNUSED PIN CONFIGURATIONS....................................................................................................................... 441
LIST OF FIGURES ......................................................................................................................................................................... 450
LIST OF TABLES ........................................................................................................................................................................... 454
LIST OF EQUATIONS .................................................................................................................................................................. 457
REVISION HISTORY ................................................................................................................................................................... 458
ADV7850
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1 INTRODUCTION TO ADV7850 HARDWARE MANUAL
1.1 DESCRIPTION OF THE HARDWARE MANUAL
This manual provides a detailed description of the functionality and features supported by the ADV7850.
1.2 COPYRIGHT INFORMATION
© 2012 Analog Devices, Inc., ALL RIGHTS RESERVED. This document may not be reproduced in any form without prior, express
written consent from Analog Devices, Inc.
1.3 DISCLAIMER
Analog Devices, Inc. (ADI) reserves the right to change this product without prior notice. Information furnished by Analog Devices is
believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringement of
patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under the patent
rights of Analog Devices, Inc.
The information contained in this document is proprietary of ADI. This document must not be made available to anybody other than the
intended recipient without the written permission of ADI.
The content of this document is believed to be correct. If any errors are found within this document or if clarification is needed, contact
the authors at DVP_V[email protected]om.
1.4 TRADEMARK AND SERVICE MARK NOTICE
The Analog Devices logo is a registered trademark of Analog Devices, Inc. All other brand and product names are trademarks or service
marks of their respective owners.
1.5 NUMBER NOTATIONS
Notation
Description
bit N
Bits are numbered in little endian format, that is, the least
significant bit of a number is referred to as bit 0
V[X:Y]
Bit field representation covering bit X to Y of a value or a field V
0xNN
Hexadecimal (base-16) numbers are preceded by the prefix ‘0x’
0bNN
Binary (base-2) numbers are preceded by the prefix ‘0b’
NN
Decimal (base-10) are represented using no additional prefixes
or suffixes
1.6 REGISTER ACCESS CONVENTIONS
Mode
Description
R/W
Memory location has read and write access.
R
Memory location is read access only. A read always returns 0
unless specified otherwise.
W
Memory location is write access only.
1.7 ACRONYMS AND ABBREVIATIONS
Acronym/Abbreviation
Description
ACP
Audio Content Protection
ADC
Analog to Digital Converter
ADI
Analog Devices Inc.
ADV7850
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Acronym/Abbreviation
Description
AFE
Analog Front End
AGC
Automatic Gain Control
Ainfo
HDCP register. Refer to HDCP documentation.
AKSV
HDCP Transmitter Key Selection Vector. Refer to HDCP documentation.
An
64-bit pseudo-random value generated by HDCP Cipher function of Device A
AP
Audio Output Pin
AVI
Auxiliary Video Information
Aux
Auxiliary
Bcaps
HDCP register. Refer to HDCP documentation.
BGA
Ball Grid Array
BKSV
HDCP Receiver Key Selection Vector. Refer to HDCP documentation.
CP
Component Processor
CSC
Color Space Converter/Conversion
CSync
Composite Synchronization
CTI
Chroma Transient Improvement
DCM
Decimation
DDR
Double Data Rate
DDFS
Direct Digital Frequency Synthesizer
DE
Data Enable
DID
Data Identification Word
DLL
Delay Locked Loop
DNR
Digital Noise Reduction
DPP
Data Preprocessor
DUT
Device Under Test (designate the ADV7850 unless stated otherwise)
DVI
Digital Visual Interface
EAV
End of Active Video
ED
Enhanced Definition
EMC
Electromagnetic Compatibility
EQ
Equalizer
HD
High Definition
HDCP
High Bandwidth Digital Content Protection
HDMI
High Bandwidth Multimedia Interface
HDTV
High Definition Television
HPA
Hot Plug Assert
HPD
Hot Plug Detect
HQI
High Quality Input
HSync
Horizontal Synchronization
IC
Integrated Circuit
ISRC
International Standard Recording Code
I
2
S
Inter IC Sound
I
2
C
Inter Integrated Circuit
KSV
Key Selection Vector
LLC
Line Locked Clock
LSB
Least Significant Bit
L-PCM
Linear Pulse Coded Modulated
Mbps
Megabit per Second
MPEG
Moving Picture Expert Group
Ms
Millisecond
MSB
Most Significant Bit
NC
No Connect
OTP
One Time Programmable
PAR
Parallel
Pj’
HDCP Enhanced Link Verification Response. Refer to HDCP documentation.
Ri’
HDCP Link verification response. Refer to HDCP documentation.
Rx
Receiver
SA
Slave Address
SAV
Start of Active Video
SD
Standard Definition
SDP
Standard Definition Processor
ADV7850
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Acronym/Abbreviation
Description
SDR
Single Data Rate
SHA-1
Refer to HDCP documentation.
SMPTE
Society of Motion Picture and Television Engineers
SNR
Signal to Noise Ratio
SOG
Sync on Green
SOY
Sync on Y
SPA
Source Physical Address
SPD
Source Production Descriptor
SSPD
Synchronization Source Polarity Detector
STDI
Standard Identification
TBC
Timebase Correction
TMDS
Transition Minimized Differential Signaling
Tx
Transmitter
US
Up Sampling
VBI
Video Blanking Interval
VDP
VBI Data Processor
VSync
Vertical Synchronization
XTAL
Crystal Oscillator
1.8 CONTROL DESCRIPTION
The function of a control is described in a table preceded by the name, a short function description, the I
2
C map, the register location
within the I
2
C map, and a detailed description of the control.
prim_mode[3:0], VFE Map, Address 0x01[3:0]
This control is used to select the primary mode of operation of the decoder. It is to be used with vid_std[5:0].
Function
prim_mode[3:0]
Description
0000
SDP mode
0001 <<
Component mode
0010
Graphics mode
0011
Reserved
0100
Reserved
0101
HDMI-Comp
0110
HDMI-GR
0111 - 1111
Reserved
Figure 1: Field Description Format
Default value
indicated by 
The name of the field. In this example the field is called
prim_mode and is 4 bit long.
I2C location of the field
in big endian format
(MSB first, LSB last)
Detailed
description
of the field
Function of the field for each value
the field can take or be set to.
Values are in binary format.
Values the field can be set to or
take. These values are in binary
format if not preceded by ‘0x’ and in
hexadecimal format if preceded by
‘0x’.
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1.9 REFERENCES
• HDMI Licensing and LLC, High-Definition Multimedia Interface, Revision 1.4, June 5, 2009
• Digital Content Protection (DCP) LLC, High-bandwidth Digital Content Protection System, Revision 1.3, December 21, 2006
• CEA, CEA-861-D, A DTV Profile for Uncompressed High Speed Digital Interfaces, Revision D, July 18, 2006
• ITU, ITU-R BT.656-4, Interface for Digital Component Video Signals in 525-Line and 625-Line Television Systems Operating at
the 4:2:2 Level of Recommendation ITU-R BT.601, February 1998
• ITU, ITU-R BT.601-5 Studio encoding parameters of digital television for standard 4:3 and widescreen 16:9 aspect ratios,
December 1995
• ITU, ITU-R BT.709-5 Parameter values for the HDTV standards for production and international programme exchange, April
2002
• CENELEC, EN 50157, Part 1, Domestic and similar electronic equipment interconnection requirements: AV.link
• CENELEC, EN 50157, Part 2-1, Domestic and similar electronic equipment interconnection requirements: AV.link
• CENELEC, EN 50157, Part 2-2, Domestic and similar electronic equipment interconnection requirements: AV.link
• CENELEC, EN 50157, Part 2-3, Domestic and similar electronic equipment interconnection requirements: AV.link
ADV7850
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2 INTRODUCTION
The ADV7850 is a high quality, single chip, multiformat video decoder graphics digitizer with an integrated 4:1 multiplexed High-
Definition Multimedia Interface (HDMIâ„¢) receiver. The multiformat 3D comb filter decoder supports the conversion of PAL, NTSC, and
SECAM standards in the form of a composite or an S-Video input signal into a digital ITU-R BT.656 format. SCART and overlay functionality are
enabled by the ability of the ADV7850 to process simultaneously CVBS and standard definition RGB signals.
The ADV7850 contains one main component processor (CP), which processes YPrPb and RGB component formats, including RGB
graphics. The ADV7850 can operate in quad HDMI and analog input mode, thus allowing for fast switching between the ADCs and the
HDMI.
The ADV7850 supports the decoding of a component RGB/YPrPb video signal into a digital Transition Minimized Differential Signaling
(TMDS) output stream. The support for component video includes 525i, 625i, 525p, 625p, 720p, 1080i, 1080p, and 1250i standards, as well
as many other SMPTE and HD standards. The ADV7850 supports graphics digitization. The ADV7850 is capable of digitizing RGB
graphics signals from VGA to UXGA rates and converting them into a digital TMDS output stream. Internal EDID is available for one
graphics port.
The ADV7850 incorporates a quad input HDMI receiver that supports all HDTV formats up to 1080p and display resolutions up to UXGA
(1600 × 1200 at 60 Hz). The HDMI ARC feature is fully supported on all ports where audio is supplied via the SPDIF in interface.
The ADV7850 supports full HDCP de-encryption with internal key storage. The ADV7850 features HDCP authentification, sync
measurement and status monitoring for all non selected HDMI ports. These features allow for extremely fast switching between ports.
Each HDMI input port has a dedicated +5V Detect and Hot Plug Assert pin. The HDMI receiver also includes an integrated equalizer that
ensures the robust operation of the interface. The HDMI receiver has advanced audio functionality, such as a mute controller, that
prevents audible extraneous noise in the audio output. In addition, the HDMI receiver incorporates an internal EDID, which can be
available in power saving modes.
Fabricated in an advanced CMOS process, the ADV7850 is provided in a 19 mm × 19 mm, 425-ball, CSP_BGA, surface-mount, RoHS-
compliant package and is specified over the 0°C to +70°C temperature range.
2.1 ANALOG FRONT END
The ADV7850 analog front end comprises of four 170 MHz, 12-bit ADCs that digitize the analog video signal before applying it to the
SDP or CP. The analog front end uses differential channels to each ADC to ensure high performance in a mixed-signal application.
The front end also includes a 13-channel input mux that enables multiple video signals to be applied to the ADV7850 without the
requirement of an external mux. Current and voltage clamp control loops ensure that any DC offsets are removed from the video signal.
The clamps are positioned in front of each ADC to ensure that the video signal remains within the range of the converter. The ADV7850
can support two composite outputs for full SCART support. These two outputs can be connected to a selection of composite inputs
The ADCs are configured to run up to 4× oversampling mode when decoding composite or S-Video inputs. For component 525i, 625i,
525p, and 625p sources, 2× oversampling is performed. All other video standards are 1× oversampled. Oversampling the video signals
reduces the cost and complexity of external anti aliasing filters with the benefit of an increased signal to noise ratio (SNR).
Optional internal anti aliasing filters with programmable bandwidth are positioned in front of each ADC. These filters can be used to
band limit video signals, removing spurious and out-of-band noise.
The ADV7850 can support the simultaneous processing of CVBS and RGB standard definition signals to enable SCART compatibility and
overlay functionality. A combination of CVBS and RGB inputs can be mixed and the output is under the control of I
2
C registers and the
fast blank pin.
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2.2 STANDARD DEFINITION PROCESSOR
The standard definition processor (SDP) is capable of decoding a large selection of baseband video signals in composite and S-Video formats.
The video standards supported by the SDP include PAL, PAL 60, PAL M, PAL N, PAL Nc, NTSC M/J, NTSC 4.43, and SECAM. The
ADV7850 can automatically detect the video standard and process it accordingly.
The SDP has a 3D temporal comb filter and a 5-line adaptive 2D comb filter that gives superior chrominance and luminance separation
when decoding a composite video signal. This highly adaptive filter automatically adjusts its processing mode according to the video
standard and signal quality, with no user intervention required. A 1D notch filter can be used for poor quality inputs. The SDP has an IF
filter block that compensates for attenuation in the high frequency chroma spectrum due to a tuner saw filter. The SDP has specific lumi-
nance and chrominance parameter controls for brightness, contrast, saturation, and hue.
The ADV7850 implements a patented adaptive digital line length tracking (ADLLT) algorithm to track varying video line lengths from
sources such as a VCR. ADLLT enables the ADV7850 to track and decode poor quality video sources (such as VCRs) and noisy sources
(such as tuner outputs). Frame-based Timebase Correction (Frame TBC) ensures stable clock synchronization between the decoder and
the downstream devices.
The SDP also contains both a luma transient improvement (LTI) and a chroma transient improvement (CTI) processor. This processor
increases the edge rate on the luma and chroma transitions, resulting in a sharper video image. The SDP has a Rovi® detection circuit,
which allows Type I, Type II, and Type III Rovi protection levels. The decoder is also fully robust to all Rovi signal inputs.
2.3 HDMI RECEIVER
The HDMI receiver on the ADV7850 incorporates a fast switching feature that allows inactive ports to be authenticated for seamless
switching between encrypted HDMI sources. The ADV7850 incorporates XpressViewâ„¢ fast switching on all HDMI input ports. Using the
ADI hardware-based HDCP engine that minimizes software overheads, XpressView technology allows fast switching between any HDMI
input ports in less than one second. The ADV7850 HDMI receiver provides active equalization of the HDMI data signals. This
equalization compensates for the high frequency losses inherent in HDMI and DVI cabling, especially at longer lengths and higher
frequencies. The equalizer is capable of equalizing for cable lengths up to 30 meters to achieve robust receiver performance at even high
HDMI data rates.
With the inclusion of HDCP, displays can receive encrypted video content. The HDMI interface of the ADV7850 allows for authentication
of a video receiver, decryption of encoded data at the receiver, and renewability of that authentication during transmission, as specified by
the HDCP v1.3 protocol for active and background HDMI ports.
Audio Return Channel is supported via the SPDIF interface. The four ports each contain a single-ended ARC transmitter. The ADV7850
also supports 3D Video, such as packing for all 3D formats up to a 3 GHz TMDS clock. The ADV7850 supports full colorimetry
including SYCC601, Adobe RGB, and Adobe YCC601.
The HDMI receiver offers advanced audio functionality. The receiver contains an audio mute controller, which can detect a variety of
conditions that could result in audible extraneous noise in the audio output. Upon detection of these conditions, the audio data can be
muted to prevent audio clicks or pops.
2.4 COMPONENT PROCESSOR
The CP section is capable of decoding a wide range of component video formats in any color space. Component video standards
supported by the CP are 525i, 625i, 525p, 625p, 720p, 1080i, 1080p, 1250i, VGA up to UXGA at 60 Hz, and many other standards.
The output section of the CP is connected to a TMDS output bus which can interface easily to a TMDS input or HDMI processor IC.
The CP section contains circuitry to enable the detection of Rovi encoded YPrPb signals for 525i, 625i, 525p, and 625p. It is designed to be
fully robust when decoding these types of signals.
VBI extraction of CGMS data is performed by the VDP section of the ADV7850 for interlaced, progressive, and high definition scanning
ADV7850
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rates. The data extracted can be read back over the I
2
C interface or ancillary data stream.
2.5 AUDIO CODEC
The ADV7850 contains a 24-bit, 48 kHz stereo CODEC. The stereo audio ADC converts analog audio inputs and provides the data to the
back end via the HDMI interface. The stereo audio DAC receives I
2
S data from the back end and converts it to an analog audio output.
The audio output is available as both high impedance and driver output which is suitable for direct headphone connection.
2.6 MAIN FEATURES OF ADV7850
2.6.1 Analog Front End
The analog front-end functionality includes:
• 170 MHz 12-bit ADCs enabling true 12-bit video decoding
• 13 analog input channel mux enabling multisource connection without the requirement of an external mux
• Two analog output options for SCART connectivity
• Voltage clamp control loops ensuring any DC offsets are removed from the video signal
• Digital PLL design delivering ultra low sampling jitter for the digitizer
2.6.2 HDMI Receiver
• HDMI 1.4 compatible receiver
 ARC support
 3D video support including Frame packing for all 3D formats up to a 225 MHz TMDS clock and/or up a pixel clock of
148.5 MHz
 Full colorimetry support including SYCC601, Adobe RGB, and Adobe YCC601
 Advanced audio features
• HDCP v1.3 compliant receiver
• Fast switching between HDMI ports (XpressView support)
• Supports deep color
• Supports all display resolutions up to UXGA (1600 x 1200 at 60 Hz)
• HBR, DSD, and PCM formats are supported with a sampling frequency up to 192 kHz
• Programmable front end equalization for HDMI operation over cable lengths up to 30 meters
• Audio mute for removing extraneous noises
• Programmable interrupt generator to detect HDMI packets
• Internal EDID support
2.6.3 Composite and S-Video Processing
• Advanced adaptive 3D comb with concurrent Frame TBC using external DDR2 SDRAM memory
• Adaptive 2D 5-line comb filters for NTSC and PAL that give superior chrominance and luminance separation for composite
video
• Full automatic detection and autoswitching of all worldwide standards (PAL, NTSC, and SECAM)
• Automatic gain control with white peak mode that ensures the video is always processed without loss of the video processing
range
• Proprietary architecture for locking to weak, noisy, and unstable sources from VCRs and tuners
• IF filter block that compensates for high frequency luma attenuation due to the tuner saw filter
• LTI and CTI for PAL, NTSC and SECAM
• Simultaneous CVBS and HDMI audio processing
• Vertical and horizontal programmable luma peaking filters
• 4× oversampling for CVBS, and S-Video modes
• Line-locked clock output (LLC)
• Free run output mode that provides stable timing when no video input is present
• Internal color bar test pattern
• Advanced TBC with frame synchronization, which ensures nominal clock and data for nonstandard input
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• Color controls that include hue, brightness, saturation, and contrast
2.6.4 Component Video Processing
• Formats supported include 525i, 625i, 525p, 625p, 720p, 1080i, and 1080p
• Automatic adjustments for gain (contrast) and offset (brightness); manual adjustment controls are also supported
• Support for analog component YPrPb/RGB video formats with embedded synchronization or with separate HSync, VSync, or
CSync
• Any-to-any 3 × 3 CSC matrix supports YCrCb to RGB and RGB to YCrCb.
• Provides color controls such as saturation, brightness, hue, and contrast
• Two standard identification (STDI) blocks that enable dual system component format detection
• Two synchronization source polarity detectors (SSPD) determine the source and polarity of the synchronization signals that
accompany video inputs
• Certified Rovi copy protection detection on component formats (525i, 625i, 525p, and 625p)
• Free run output mode provides stable timing when no video input is present
• Arbitrary pixel sampling support for nonstandard video sources
• Autographic mode allows support for an extended selection of standards
2.6.5 RGB Graphics Processing
• 170 MHz conversion rate supports RGB input resolutions up to 1600 × 1200 at 60 Hz (UXGA)
• Automatic gain controls for graphics modes
• Contrast, brightness, saturation, and hue controls
• 64-phase Delay Locked Loop (DLL) allows optimum pixel clock sampling
• Automatic detection of synchronization source and polarity by the SSPD block
• Standard identification is enabled by either of the available STDI blocks
• RGB can be color space converted to YCrCb and decimated to a 4:2:2 format for video centric back-end IC interfacing
• Arbitrary pixel sampling support for nonstandard video sources
• Autographic mode allows support for an extended selection of standards
2.6.6 Audio CODEC
• 24-bit, 48 kHz stereo CODEC
• 5-channel stereo analog input mux with one stereo analog output
• Stereo headphones output
2.6.7 Additional Features
• Three interrupt request output pins, INT1, INT2 and INT3
• Temperature range : 0°C to +70°C
• 19 mm x 19 mm, Pb-free BGA package
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2.7 FUNCTIONAL BLOCK DIAGRAM
Figure 2: Functional Block Diagram
ADC0
CLAMP
12
ADC1
CLAMP
12
ADC2
CLAMP
12
ADC3
CLAMP
12
(A)
(B)
(C)
(D)
(A)
(B)
(C)
EDID/
REPEATER
CONTROLLER
HDCP
EEPROM
PLL
EQUAL-
IZER
EQUAL-
IZER
HDCP
BLOCK
SAMPLER
SAMPLER
FASTSWITCHING
BLOCK + HDMI DECODE
+ MUX
HS/CS, VS/FIELD
CONTROL AND DATA
PARAMETER
EXTRACTION
PACKET
PROCESSOR
HDMI
PROCESSOR
PACKET/
INFOFRAME
MEMORY
VBI
DECODER
I
2
C
READBACK
VBI DATA
FORMATTER
SPI
INTERFACE
VIDEO DATA PROCESSOR
INTERRUPT
CONTROLLER
AUDIO
PROCESSOR
VIDEO OUTPUT FORMATTER
TTX_SPI
INT1
INT2
ACTIVE PEAK
AND HSYNC DEPTH
NOISEAND
CALIBRATION
OFFSET
ADDER
MACROVISIONAND
CGMS DETECTION
COLOR SPACE
CONVERSION
STANDARD
IDENTIFICATION
SYNC SOURCE
AND POLARITY
DETECT
COMPONENT PROCESSOR (CP)
STANDARD DEFINITION PROCESSOR (SDP)
2D COMB
3D COMB
DDR2/mDDR
SDRAM 
INTERFACE
TBC
VERTICAL
PEAKING
HORIZONTAL
PEAKING
CTI AND LTI
STANDARD
AUTODECTION
MACROVISION
DETECTION
COLOR
CONTROL
FASTBLANK
OVERLAY
CONTROL
VIDEO_OUT_2
CVBS
YC
SCART RGB
YPrPb
RGB
SYNC1
HS_IN
VS_IN
TRI1 TO TRI8
SCL
SDA
RXA_5V/HPAA
RXB_5V/HPAB
DDCA_SDA/DDCA_SC
L
DDCB_SDA/DDCB_SC
L
RXA_C±
RXB_C±
RXA_0±
RXA_1±
RXA_2±
EQUAL-
IZER
SAMPLER
RXC_0±
RXC_1±
RXC_2±
EQUAL-
IZER
SAMPLER
RXD_0±
RXD_1±
RXD_2±
RXB_0±
RXB_1±
RXB_2±
13-CHANNEL
INPUT
MATRIX
ANALOG FRONT END
SYNC PROCESSING
AND
CLOCK GENERATION
TRI-LEVEL
SLICER
I
2
C CONTROL INTERFACE
MUX
GAIN
CONTROL
DIGITAL
FINE CLAMP
PROGRAM-
MABLE
DELAY
RXC_5V/HPAC
RXD_5V/HPAD
DDCC_SDA/DDCC_SC
L
DDCD_SDA/DDCD_SC
L
TX_C±
TX_0±
TX_1±
TX_2±
RXC_C±
RXD_C±
SYNC2
HDMI TX
PLL
SERIALIZER
TMDS DRIVERS
HDMI
ENCODER
5-CHANNEL
STEREO
INPUT
MATRIX
AUDIO_L/R_1
AUDIO_L/R_2
AUDIO_L/R_3
AUDIO_L/R_4
AUDIO_L/R_5
AUDIO_L/R_OUT
ADC
DAC
DAC_L/R_OUT
HP_L/R_OUT
AC_SCLK
AC_LRCLK
AC_SDI
VIDEO_OUT_1
SYNC3
AUDIO RETURN CHANNEL
(SINGLE MODE ONLY)
ARC_1
ARC_2
SPDIF_IN
ARC_3
ARC_4
AC_MCLK
AUDIO OUTPUT FORMATTER
HA_P0
HA_P1
HA_P2
HA_P3
HA_P4
HA_P5
HA_SCLK
HA_MCLK
SPI_EPROM
PROGRAMMABLE DECIMATION FILTERS
(A)
(B)
(C)
(D)
+3.3V_EPROM
5V DETECT, HPA
CONTROLLERAND
5V REGULATOR
HPD
DDC_SDA
DDC_SCL
I
2
S
AUDIO
PLL
HDCP
EEPROM
HDCP
BLOCK
VGA_SDA/VGA_SCL
INT3
ADV7850
Rev. A May 2012
20
2.8 PIN DESCRIPTION
Figure 3: ADV7850 Pin Configuration
Table 1: Function Descriptions
Pin No.
Mnemonic
Description
A1
GND
Ground
A2
GND
Ground
A3
GND
Ground
A4
RXB_2+
Digital Input Channel 2 true of Port B in the HDMI interface.
A5
RXB_1+
Digital Input Channel 1 true of Port B in the HDMI interface.
A6
RXB_0+
Digital Input Channel 0 true of Port B in the HDMI interface.
A7
RXB_C+
Digital input clock true of Port B in the HDMI interface.
A8
ARC_B
Single ended Audio Return Channel of Port B in the HDMI interface.
A9
TVDD
HDMI termination supply (3.3V)
A10
RXC_2+
Digital Input Channel 2 true of Port C in the HDMI interface.
A11
RXC_1+
Digital Input Channel 1 true of Port C in the HDMI interface.
A12
RXC_0+
Digital Input Channel 0 true of Port C in the HDMI interface.
A13
RXC_C+
Digital input clock true of Port C in the HDMI interface.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
A
GND GND GND RXB_2+ RXB_1+ RXB_0+ RXB_C+ ARC_B TVDD RXC_2+ RXC_1+ RXC_0+ RXC_C+ ARC_C GND RXD_2+ RXD_1+ RXD_0+ RXD_C+ ARC_D GND GND GND
A
B
ARC_A HPA_A GND RXB_2- RXB_1- RXB_0- RXB_C- HPA_B TVDD RXC_2- RXC_1- RXC_0- RXC_C- HPA_C GND RXD_2- RXD_1- RXD_0- RXD_C- HPA_D GND
ACMUXO
UT_R
ACMUXO
UT_L
B
C
RXA_C+ RXA_C- CVDD GND GND GND GND
VDD_EEP
ROM
TVDD TVDD TVDD TVDD TVDD TVDD GND TVDD TVDD TVDD TVDD GND GND
ACMUXIN
_1R
ACMUXIN
_1L
C
D
RXA_0+ RXA_0- CVDD RXD_5V VGA_5V
DDCA_SC
L
DDCA_SD
A
DDCB_SC
L
DDCB_SD
A
DDCC_SC
L
DDCC_SD
A
DDCD_SC
L
DDCD_SD
A
VREG GND VGA_SCL VGA_SDA TVDD AC_AVDD AC_AVDD AC_AVDD
ACMUXIN
_2R
ACMUXIN
_2L
D
E
RXA_1+ RXA_1- CVDD RXC_5V GND GND
ACMUXIN
_3R
ACMUXIN
_3L
E
F
RXA_2+ RXA_2- CVDD RXB_5V PLL_LF GND
ACMUXIN
_4R
ACMUXIN
_4L
F
G
TVDD TVDD TVDD TVDD GND TEST1 CVDD CVDD CVDD CVDD CVDD CVDD CVDD GND GND AC_AVDD GND
ACMUXIN
_5R
ACMUXIN
_5L
G
H
EP_MISO EP_MOSI SPDIF_IN RXA_5V GND GND GND GND GND GND GND GND GND GND GND GND GND FILTA
VREF_AU
DIO
H
J
EP_CSB EP_SCK
SHARED_
EDID
RESET GND GND GND GND GND GND GND GND GND GND GND AC_AVDD GND ISET FILTD
J
K
GND GND DVDDIO DVDDIO VDD GND GND GND GND GND GND GND GND GND GND AC_AVDD AC_AVDD
AC_DACO
ut_R
AC_DACO
ut_L
K
L
HA_AP5 HA_SCLK INT1 SDA VDD GND GND GND GND GND GND GND GND GND GND AC_AVDD AC_AVDD HPOUT_R HPOUT_L
L
M
HA_AP4
HA_AP3/
INT3
INT2 SCL VDD GND GND GND GND GND GND GND GND GND GND AC_AVDD GND GND GND
M
N
HA_AP2 HA_AP1 AC_MCLK
AC_LRCL
K
VDD GND GND GND GND GND GND GND GND GND GND PVDD PVDD XTALN XTALP
N
P
HA_AP0
HA_MCLK
OUT
AC_SDI AC_SCLK VDD GND GND GND GND GND GND GND GND GND GND GND GND GND GND
P
R
TTX_SCLK TTX_MOSI TTX_MISO TTX_CSB VDD GND GND GND GND GND GND GND GND GND GND GND GND REFN REFP
R
T
DVDDIO DVDDIO GND GND VDD GND GND GND GND GND GND GND GND GND GND AVDD AVDD AVDD AVDD
T
U
TX_AVDD TX_AVDD GND
TX_DDC_
SCL
VDD VDD VDD VDD VDD VDD VDD TEST2 GND GND GND AVIN13 AVIN12 AVIN11 AVIN10
U
V
TX_2+ TX_2- GND
TX_DDC_
SDA
AVDD AVDD AVDD AVDD
V
W
TX_1+ TX_1- GND TX_HPD GND AVOUT2 AVIN9 AVIN8
W
Y
TX_0+ TX_0- GND GND A7 A3 A10 BA0 CKE GND DQ6 DQ7 DQ0 DQ8 UDQS SDVDD SAVDD TRI1 TRI2 GND AVOUT1 SYNC3 AVIN7
Y
AA
TX_C+ TX_C- TX_AVDD GND A9 A5 A1 BA1 WE GND DQ4 DQ5 DQ2 DQ11 UDQSN SDVDD GND
HS_IN1/T
RI7
VS_IN1/T
RI8
GND TRI3
HS_IN2/T
RI5
VS_IN2/T
RI6
AA
AB
TX_PLGND TX_PVDD TX_PLVDD
SDVDD A11 A6 A2 CAS RAS VREF SDVDD LDQSN DQ3 DQ10 DQ12 DQ14 GND SYNC1 AVIN3 GND SYNC2 AVIN6 TRI4
AB
AC
GND
TX_RTER
M
TX_VDD33
SDVDD A8 A4 A0 CS CKN CK SDVDD LDQS DQ1 DQ9 DQ15 DQ13 GND AVIN1 AVIN2 GND AVIN4 AVIN5 GND
AC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
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