Polaroid TLA-01901C - 19" LCD TV User manual

1

TLA-01901C Service Manual

2

Content

Chapter 1 - Specifications and Composition………………………………2

Chapter 2 - Brief introduction of the main

integrated circuit function……………………………………5

Chapter 3 - Analysis of the Signal process

Flowchart and Key Point Measure Data

Chapter 4 - Spare part list …………………………………………………38

Chapter 5 - The factory mode setting

and noticeable proceeding ……………………………………39

Chapter 6 - The flow of software update

Annex ： 1、 TLA-01901C Circuit diagram

2、 TLA-01901C exploded mechanical diagram

*Annex parts hasn’t been attached in this file. They will be provided

in separated files.

*The chassises of this LCD TV are called LS16 or L16W in this file.

LS16 and LS16W use the same TV resolution. The difference is the

connectors arrangement between these two chasises.

………………………25

and noticeable proceedin g……………………………………41

3

Chapter 1 - Specifications and Composition

1、Models of the chassis

LS16：TBD

LS16W： TLA-01901C

2、Main Feature

RF Input ， including CATV Function(capable of compatible receiving

NTSC/ATSC/CLEAR-QAM ).

Capable of receiving the program of ATSC/NTSC within 54MHZ – 803MHz.

● AV Input

● HDMI Digital Signal Input

● VGA Input

● YPbPr Input

● Headphone Output

● SPDIF Digital Audio Output (Optional)

● 191 sets of programs presetting

In ATV mode, the TV can save 191 sets of program which fully prepared for the

richness programs in the future .

● Timer Function

Automatically on/off in certain preset time.

● Blue Background with Noise Silence (Optional)

The soft blue background will be displayed if there is no signal input in TV、

AV modes

● Automatic off if no signal input

LCD TV will go to the standby mode 15 or 5 minutes after there is no signal

input in TV mode.

● English / French/Spanish OSD menu

Simple graphic OSD menu makes the operation more convenient and more direct

viewing

● Power Energy Saving Function(power management mode)(only for LS16)

In PC mode, the LCD TV will automatically power off within 30 seconds and

enter into the Power Energy Saving Mode if there is no VGA signal input. It will

automatically exit from the Power Energy Saving Mode and work again when it

received a valid VGA signal or press any button on the panel/remote control.

● Plug and Play

It is no need to equip any installation software when the product is used as

computer terminal display equipment.

(In order to obtain a good image quality, perhaps,some minor adjustment should

be done with the PC display setting or TV pc set up. )

● Legerity , Convenience and Low power consumption

3、Unit circuit modules：

LS16 and LS16W chassis LCD TV is mainly composed of regulator IC,RF IC, video

processor IC ,power amplify IC, analog video IC, system control IC and key control

4

IC. See the IC frame as below:

4、PCB assembly introduction：

LS16 and LS16W LCD TV is mainly composed of AV Board , Remote Receiver Board,

Local Key Board and Main Board. The under sheet is the function introduction of every

Main Board

MSD116

MSD809

Power Board

LCD Panel

K Panel

IR Panel

Speake

r

MST3383

TL062

TDA1517

S-FLASH

TUNER

AV

HDMI PCYPbPr

+5V

+12V

+5V

+12V

IF-D

CVBS

L V D S

TS

[

0…7

]

HD

[

0…7

]

SIF

AUDIO

5

PCD Assembly:

NO. Parts Function Description

1

Main Board

module

Main Board module is the core of LCD TV signal processing.

Under the control of the System Control Circuit, It undertakes the

task of converting the external input signal into the unified digital

signal that the LCD screen could identify 。 After RF signal

processed by tuner, It was sent to the main chip (analog signal was

sent to MSD116 for processing ,and digital signal was sent to

MSD809 for decoding first and then to MSD116 for processing ),

then the main chip(MSD116 ) produce LVDS signal displayed on

the screen .In addition, signals input from VGA、AV、SVIDEO and

YPbPr would directly enter into MSD116 for processing, format

transformation and on screen display. HDMI signal was sent to

MST3383 for processing first and then transmitted to MSD116 for

processing, format transformation and on screen display. And there

is a headphone output interface near the tuner. For LS16 only, it

has a digital audio output interface(SPDIF).

3

Remote

Control

Receiver

Assembly

It is composite of one light indicator and one remote control

receiver, which enable users operate the TV conveniently and

know its current working status simply with a remote control.

4

Built-in

Power Board

Assembly

It can transform AC power into DC for ICs including+12V，+5V and

ADJ for switching the backlight of LCD on or off and adjusting the

brightness.

5

Key Board

Assembly

It consists of 7 function buttons by which users can operate the TV

freely.

6

Panel

Assembly

The LCD screen is used to display the image after the image signal

has been processed by the main board.

6

Chapter 2 - Brief introduction of the main integrated circuit

function

1、LS16 and LS16W Chassis Main ICs and function：

Main Board

Number Position Part Number Main function

1 U12,U6 24LC02 EEPROM

2 U23 24LC512 EEPROM

3 U7 MSD809 Demodulator

4 U9 MST3383AMCK-LF-170 HDMI Decoder

5 U8 DTVS205CH201A Tuner

6 U22 MSD116L Video and audio processor.

7 U24 M25P16-VMN6P/

S25FL016A0LMFI013

Flash for code storage

8 U28,U29,U30 IS42S16400D-6TL/

W9864G6GH-6/

K4S641632K-UC60

SDRAM

9 U31 TDA1517P Audio amplifier

10 U32 TL062CD Integration amplifier

2、LS16 and LS16W Chassis IC function.

2.1 TUNER(DTVS205CH201A)

GENERAL DESCRIPTION:

Receiving System: ATSC/NTSC system

Intermediate Frequency: Digital(center): 44MHz

Analog(P-carrier):45.75MHz

Input Impedance: 75Ω,Unbalanced

IF Output Impedance: 10Ω,Balanced

Band Change-Over System: PLL system

Tuning System: PLL system

Internal RF AGC function:

Built in wideband AGC detector with 6 programmable take-over points

Narrow band output to be filtering by a 5.6MHz SAW filter

Built in the additional IF amplifier with AGC circuit

Reference Frequency The X-tal the RF block’s PLL:4MHz

Control Data Bus: I²C (BUS VOLTAGE:3.3V)

Control Data Format: Refer to 6 Section

DTVS205CH201A BLOCK DIAGRAM：

7

PIN FUNCTION DESCRIPTION：

PIN PIN NAME DESCRIPTION

1 NC not connected

2 NC not connected

3 NC not connected

4 NC not connected

5 NC not connected

6 NC not connected

7 RF AGC TP

8 NC not connected

9 VT 30V

10 IF OUT (+) digital IF

11 IF OUT (-) digital IF

12 IF AGC

EXTERNAL

13 TP(IF)

14 CLOCK

15 DATA

16 GND

17 5V

18 NC

19 AFT analog demod

20 SIF analog demod

21 CVBS analog demod

8

2.2 MSD116L

GENERAL DESCRIPTION:

The MSD116L is a highly integrated SOC for LCD/PDP DTV applications with

resolutions up to SXGA/WXGA+.It is configured with an integrated triple-ADC/PLL,

a multi-standard TV video and audio decoder, a DTV video and audio decoder, a

video de-interlacer, a scaling engine, the MStarACE-3 color engine, a graphics engine,

an 8-bit MCU and a built-in output panel interface. The built-in DTV decoder

including transport stream de-multiplexer and MPEG-2 AV decoder are designed to

support ATSC HD/SDTV program while handling ATSC CC and EPG. For analog TV,

the MSD116L receives NTSC/PAL/SECAM CVBS/S-Video and component video

signals from various analog graphic & video sources. To further reduce system costs,

the MSD116L also integrates intelligent power management control capability for

green-mode requirements and spread-spectrum support for EMI management.

FEATURES

●Twin-turbo 8051 Micro-controller

●Transport Stream De-multiplexer

●MPEG-2 A/V Decoder

●NTSC/PAL/SECAM Video Decoder

●

Multi-Standard TV Sound Processor

●Digital Audio Interface

I

2

S digital audio input & output

S/PDIF digital audio input & output

●Analog RGB Compliant Input Ports

●Auto-Configuration/Auto-Detection

Two analog ports support up to 135MHz

Supports PC RGB input up to SXGA@75Hz

Supports HDTV RGB/YPbPr/YCbCr

Supports Composite Sync and SOG (Sync-on-Green) separator

Automatic color calibration

●High-Performance Scaling Engine

●

Video Processing & Conversion

●

Output Interface

Supports up to 8-bit dual LVDS SXGA/WXGA+ panel interface

Supports 2 data output formats: Thine & TI data mappings

Compatible with TIA/EIA

With 6/8 bits options

Spread spectrum output frequency for EMI suppression

Supports flexible spread spectrum frequency

●2D Graphics Engine

●Digital PWM Controller

●Miscellaneous

9

SDRAM controller to support up to 48-bit data bus

Supports serial flash with up to 2M address

Two I2C interfaces in master/slave mode

One IR receiver input with power-down wakeup

256-LQFP package

Operating at 1.8V (core) and 3.3V (I/O and analog)

PIN FUNCTION DESCRIPTION：

Analog Interface

Pin Name Pin Type Function Pin

VCLAMP CVBS/YC Mode Clamp Voltage Bypass 20

REFM Internal ADC Bottom De-coupling Pin 18

REFP Internal ADC Top De-coupling Pin 19

SOGIN1 Analog Input Sync-on-Green slicer input from

channel 1

2

BINP Analog Input Analog B Input of VGA 1

GINP Analog Input Analog G Input of VGA 3

RINP Analog Input Analog R Input of VGA 4

PBINP Analog Input Analog Pb Input 11

VCOMB Analog Input Common Negative Input for

B-component ADC

12

SOGIN0 Analog Input Sync-on-Green slicer input from

channel 0

13

VCOMG Analog Input Common Negative Input for

G-component ADC

15

YINP Analog Input Analog Y Input 14

VCOMR Analog Input Common Negative Input for

R-component ADC

17

PRINP Analog Input Analog Pr Input 16

C0INP Analog Input Analog Chroma Input for TV S-Video0 23

YS0INP Analog Input Analog Luma Input of TV S-Video0 24

C1INP Analog Input Analog Chroma Input for TV S-Video1

/ Analog Composite Input of TV CVBS4

25

YS1INP Analog Input Analog Luma Input of TV S-Video0 /

Analog Composite Input of TV CVBS3

26

VCOMY Analog Input Common Negative Input for

Y-component ADC

27

CVBSOUT Analog

Output

CVBS Output buffered from CVBS input 32

CVBS0 Analog Input Analog Composite Input for TV CVBS0 31

CVBS1 Analog Input Analog Composite Input for TV CVBS1 30

CVBS2 Analog Input Analog Composite Input for TV CVBS2 29

CVBS3 Analog Input Analog Composite Input for TV CVBS3 28

DREXT Analog Input Reference Current Generator, 820 170

10

ohm to Ground

HSYNC0 Schmitt

Trigger

Input w/

5V-tolerant

HSYNC / Composite Sync for VGA Input

from channel 0

9

VSYNC0 Schmitt

Trigger

Input w/

5V-tolerant

VSYNC for VGA Input from channel 1 10

HSYNC1 Schmitt

Trigger

Input w/

5V-tolerant

HSYNC / Composite Sync for VGA Input

from channel 1

8

VSYNC1

Schmitt Trigger

Input

w/ 5V-tolerant

VSYNC for VGA Input from channel 1

7

Digital Panel Output Interface

LVA0M Output

LVDS A-Link Channel 0 Negative Data

Output

186

LVA0P Output

LVDS A-Link Channel 0 Positive Data

Output

185

LVA1M Output

LVDS A-Link Channel 1 Negative Data

Output

184

LVA1P Output

LVDS A-Link Channel 1 Positive Data

Output

183

LVA2M Output

LVDS A-Link Channel 2 Negative Data

Output

182

LVA2P Output

LVDS A-Link Channel 2 Positive Data

Output

181

LVACKM Output LVDS A-Link Negative Clock Output 180

LVACKP Output LVDS A-Link Positive Clock Output 179

LVA3M Output

LVDS A-Link Channel 3 Negative Data

Output

178

LVA3P Output

LVDS A-Link Channel 3 Positive Data

Output

177

LVB0M Output

LVDS B-Link Channel 0 Negative Data

Output

199

LVB0P Output

LVDS B-Link Channel 0 Positive Data

Output

198

LVB1M Output

LVDS B-Link Channel 1 Negative Data

Output

197

LVB1P Output

LVDS B-Link Channel 1 Positive Data

Output

196

11

LVB2M Output

LVDS B-Link Channel 2 Negative Data

Output

195

LVB2P Output

LVDS B-Link Channel 2 Positive Data

Output

194

LVBCKM Output LVDS B-Link Negative Clock Output 190

LVBCKP Output LVDS B-Link Positive Clock Output 189

LVB3M Output

LVDS B-Link Channel 3 Negative Data

Output

188

LVB3P Output

LVDS B-Link Channel 3 Positive Data

Output

187

Internal MCU Interface with Serial Flash Memory

SAR3 Analog Input SAR Low Speed ADC Input 3 204

SAR2 Analog Input SAR Low Speed ADC Input 2 203

SAR1 Analog Input SAR Low Speed ADC Input 1 202

SAR0 Analog Input SAR Low Speed ADC Input 0 201

SCK Output SPI Interface Sampling Clock 171

SDI Output SPI Interface Data-In 172

SDO

Input w/

5V-tolerant

SPI Interface Data-Out 173

CSZ Output SPI Interface Chip Select 174

GPIO_P10-GPI

O_P17

I/O w/

5V-tolerant

General Purpose Input/Output; 4mA

driving strength

41-4

8

UART_TX

I/O w/

5V-tolerant

Universal Asynchronous Transmitter 55

UART_RX

I/O w/

5V-tolerant

Universal Asynchronous Receiver 56

IRIN

Input

w/5V-toleran

t

IR Receiver Input 57

INT Input

MCU Bus Interrupt; 4mA driving

strength

58

SCLM Output I2C Master Clock 59

SDAM

I/O w/

5V-tolerant

I2C Master Data 60

DDC_SCL I/O DDC Clock for D-SUB Input 33

DDC_SDA I/O DDC Data for D-SUB Input 34

DDC_ROMSCL I/O DDC ROM Clock for D-SUB Input 35

DDC_ROMSDA I/O DDC ROM Data for D-SUB Input 36

SDRAM Interface

SDR_CSZ Output SDRAM Chip Select; active low 134

SDR_CKE Output SDRAM Clock Enable 126

SDR_AD[11:0] Output SDRAM Address Bus

148-

137

12

SDR_BA[1:0] Output SDRAM Bank Select

129,

130

SDR_DQ[31:0] I/O SDRAM Data Bus

168-

161,

157-

150,

124-

117,

114-

107

SDR_RASZ Output SDRAM Row Address Strobe; active low 131

SDR_CASZ Output

SDRAM Column Address Strobe; active

low

132

SDR_WEZ Output SDRAM Write Enable 133

SDR_DQM[3:0] Output

SDRAM Data Mask for Low Byte; active

high

169,

149,

125,

106

SDR_MCLKO Output Master Clock Output to SDRAM 128

SDR1_CKE Output SDRAM1 Clock Enable 225

SDR1_AD[11:0

]

Output SDRAM1 Address Bus

224-

213

SDR1_BA[1:0] Output SDRAM1 Bank Select

233,

232

SDR1_DQ[15:0

]

I/O SDRAM1 Data Bus

251-

245,

243,

242,

240-

234

SDR1_RASZ Output

SDRAM1 Row Address Strobe; active

low

231

SDR1_CASZ Output

SDRAM1 Column Address Strobe;

active low

230

SDR1_WEZ Output SDRAM1 Write Enable 227

SDR1_DQM[1:0

]

Output

SDRAM1 Data Mask for Low Byte;

active high

229,

228

SDR1_MCLKO Output Master Clock Output to SDRAM1 226

TS Input Interface

TSCLK Input TS Clock 95

TSDATA[7:0] Input

TS Data in Parallel; LSB (bit 0) is

for serial TS data

96-1

03

TSVALID Input TS Data Valid 104

TSSYNC Input TS Sync-Byte Indicator 105

13

Audio Input/Output Interface

SIF0M Analog Input

Reference Ground for SIF Audio Input

Channel 0

50

SIF0P Analog Input SIF Audio Input Channel 0 51

SIF1P Analog Input SIF Audio Input Channel 1 53

SIF1M Analog Input

Reference Ground for SIF Audio Input

Channel 1

54

I2S_OUT_MCK Output Audio Master Clock Output 85

I2S_OUT_BCK Output Audio Bit Clock Output 86

I2S_OUT_WS Output

Word Select Output; 4mA driving

strength

87

I2S_OUT_SD Output

Audio Serial Data Output; 4mA

driving strength

88

SPDIFO Output

S/PDIF Audio Output; 4mA driving

strength

90

I2S_OUT_MUTE Output Audio Output Mute Control 89

I2S_IN_BCK Input Audio Bit Clock Input 81

I2S_IN_WS Input Word Select Input 82

I2S_IN_SD Input Audio Serial Data Input 83

SPDIFI Input S/PDIF Audio Input 84

AUVRM

Analog

Output

Negative Reference Voltage for

Audio ADC

64

AUVRP

Analog

Output

Positive Reference Voltage for

Audio ADC

65

AUVAG

Analog

Output

Reference Voltage for Audio Common

Mode

66

AUL0 Analog Input Audio Line Input Left Channel 0 68

AUR0 Analog Input Audio Line Input Right Channel 0 69

AUL1 Analog Input Audio Line Input Left Channel 1 70

AUR1 Analog Input Audio Line Input Right Channel 1 71

AUCOM Analog Input

Reference Ground for Audio Line

Input

72

AUL2 Analog Input Audio Line Input Left Channel 2 73

AUR2 Analog Input Audio Line Input Right Channel 2 74

AUL3 Analog Input Audio Line Input Left Channel 3 75

AUR3 Analog Input Audio Line Input Right Channel 3 76

AUOUTL1

Analog

Output

Main Audio Output Left Channel 0 77

AUOUTR1

Analog

Output

Main Audio Output Right Channel 0 78

AUOUTL0

Analog

Output

Main Audio Output Left Channel 0 79

AUOUTR0 Analog Main Audio Output Right Channel 0 80

14

Output

Power Pins

AVDD_ADC 3.3V Power ADC Power

6,

22

AVDD_SIF 3.3V Power SIF Power 52

AVDD_AU 3.3V Power Audio Power 67

AVDD_SDRPLL 3.3V Power SDRPLL Power 127

AVDD_LPLL 3.3V Power LPLL Power 193

AVDD_XTAL 3.3V Power XTAL Power 254

VDDC 1.8V Power Digital Core Power

94,

160,

200,

253

VDDP 3.3V Power Digital Input/Output Power

91,

115,

135,

158,

176,

192,

211,

244

GND Ground Ground

5,

21,

49,

62,

63,

92,

93,

116,

136,

159,

175,

191,

212,

241,

252,

2.3 MST3383 Description：

GENERAL DESCRIPTION:

15

The MST3383AMCK integrates the HDMI compliant receiver for enabling

advanced digital display devices such as digital TVs, plasma displays, LCD TVs and

projectors to receive and display. Compatible with the HDMI 1.2 specification, the

MST3383AMCK enables consumer electronic devices to receive uncompressed, high

quality, digital audio and video HD content over a single, low-cost HDMI cable. The

MST3383AMCK is available in a 128-pin PQFP package.

FEATURES：

●Highly integrated HDMI interface for 25~170 MHz pixel rates

●Compatible with VGA through UXGA RGB graphics signals, and component TV,

DTV and HDTV

●One DVI/HDMI single link input

●HDMI 1.2 compliant

●Smart sync detection with HSYNC, VSYNC and DE period report

●Serial port programming interface

●Integrated HDCP keys

●HDMI Interface

25 MHz ~ 170 MHz operation

Supports HDMI (High Definition Multimedia Interface) 1.2

Supports High bandwidth Digital Content Protection (HDCP) 1.1

Backward compatible to DVI 1.0

Supports up to 25m cable

Supports encrypted video contents

Supports authentication of video receiver with decryption of encoded data at the

receiver

Supports pin-swap to DVI/HDMI connector for low EMI

●Digital Audio Output Interface

Supports 2-channel serial audio output

Supports S/PDIF digital audio output

Supports audio sample rates of 32~192kHz, with a sample size of 16~24 bits

Pop sound suppression with auto fading

Volume control, 0 to -138 dB, -0.75 dB/step

Supports DSD audio stream with external DSD DAC

●Digital Video Output Interface

Supports color space conversion and sRGB

Supports 24-bit 4:4:4 YCbCr/RGB output formats

Supports 16-bit 4:2:2 YCbCr output formats (ITU-R BT.601)

Supports 8-bit 4:2:2 YCbCr output formats (ITU-R BT.656)

MST3383BLOCK DIAGRAM：

16

PIN FUNCTION DESCRIPTION：

CPU Interface

Pin Name Pin Type Function Pin

HWRESET

Schmitt

Trigger

Input w/

5V-tolerant

Hardware Reset; Active High 35

A0

Input w/

5V-tolerant

Serial Interface Address Input 36

SCL

Input w/

5V-tolerant

2-Wire Serial Bus Clock Input 37

SDA

I/O w/

5V-tolerant

2-Wire Serial Bus Data I/O 38

INT

Output

w/Pull-Down

Resistor

CPU Interrupt Programmable By User 40

DVI/HDMI Interface

RX0N

DVI/HDMI

Input

Negative DVI/HDMI Input for Data

Channel 0

108

RX0P

DVI/HDMI

Input

Positive DVI/HDMI Input for Data

Channel 0

109

RX1N

DVI/HDMI

Input

Negative DVI/HDMI Input for Data

Channel 1

111

RX1P

DVI/HDMI

Input

Positive DVI/HDMI Input for Data

Channel 1

112

RX2N DVI/HDMI Negative DVI/HDMI Input for Data 114

17

Input Channel 2

RX2P

DVI/HDMI

Input

Positive DVI/HDMI Input for Data

Channel 2

115

RXCKN

DVI/HDMI

Input

Negative DVI/HDMI Input for Clock

Channel

117

RXCKP

DVI/HDMI

Input

Positive DVI/HDMI Input for Clock

Channel

118

Misc. Interface

XOUT Crystal Oscillator Output 33

XIN Crystal Oscillator Input 34

REXT

External Resistor 390 Ohm connected

to AVDD_DVI

120

DDCSCL

Input w/

5V-tolerant

HDCP Slave Serial Bus Clock Input for

DVI

124

DDCSDA

I/O w/

5V-Tolerant

HDCP Slave Serial Bus Data I/O for DVI 125

Output Interface

DATA[23:0]

Output

w/Pull-Down

Resistor

Data Output Bit [23:0]; 4~12 mA

Driving Strength Programmable by User

43-50,

55-62,

76-83

DATACK

Output

w/Pull-Down

Resistor

Clock Output A; 4~12 mA Driving

Strength Programmable by User

68

SOGOUT/DE

Output

w/Pull-Down

Sync-on-Green Output for Analog 69

HSOUT

Output

w/Pull-Down

Resistor

HSYNC Output; 4~12 mA Driving

Strength Programmable by User

70

VSOUT

Output

w/Pull-Down

Resistor

VSYNC Output; 4~12 mA Driving

Strength Programmable by User

71

FIELD/GPO

Output

w/Pull-Down

Resistor

Frame Indication Output During

Interlace Input / General Purpose

Output Programmable by User

72

AUSD

Output

w/Pull-Down

Resistor

Audio Serial Data Output Bit; 4~12 mA

Driving Strength Programmable by User

96

AUSCK

Output

w/Pull-Down

Resistor

Audio Serial Clock Output; 4~12 mA

Driving Strength Programmable by User

97

AUWS

Output

w/Pull-Down

Resistor

Audio Serial Word Select Output; 4~12

mA Driving Strength Programmable by

User

98

AUMUTE Output Audio Output Mute Control 99

18

w/Pull-Down

Resistor

MCKO

Output w/

pull-Down

Resistor

Audio Master Clock Output 100

SPDIFO

Output

w/Pull-Down

Resistor

Audio SPDIF Output; 4~12 mA Driving

Strength Programmable by User

101

Power Pins

AVDD_DVI 3.3V Power DVI Power Supply

4, 29, 113,

119, 126

AVDD_MPLL 3.3V Power Master PLL Power Supply 32

AVDD_AUPLL 2.5V Power Audio PLL Power Supply 106

AVDD_PLL 3.3V Power PLL Power Supply 123

VDDP 3.3V Power Digital Output Power Supply

39, 53, 65, 73,

86, 88, 90, 102

VDDC 2.5V Power Digital Core Power Supply 67, 75, 92

GND Ground System Ground

5, 30, 31, 54,

66, 74, 87,89,

91, 103-105,

107, 110,

116, 122, 127

2.4 MSD809 Description：

GENERAL DESCRIPTION:

The MSD809 is a DTV receiver, which contains a digital receiver compatible with

ATSC 8-VSB mode for terrestrial broadcasting and ITU-J.83B which is in compliant

with 64-QAM and 256-QAM modes for digital cable appliances. It achieves

extremely high performance employing direct IF sampling architecture, robust

synchronization, and robust channel equalization. It contains a 12-bit A/D converter

and a PWM generator for automatic gain control. A host interface with an I2C bus is

also included to control the behavior of the MSD809.

FEATURES：

●Integrated 8-VSB and 64/256QAM Receiver

Direct 44MHz IF sampling scheme from tuner

Internal digital SAW filter for reduction external IF circuitry

12-bit A/D converter for sampling

MPEG-2 transport output with parallel/serial mode

GPIO control for tuner bypass mode

Enhanced FEC architecture with efficient high performance

Segment error rate measurement from the output of RS decoder

19

External ADC @24.69MHz

Optional dual AGC

49.38111MHz oscillator or crystal is used for reference clock

100-pin TQFP package

Low power consumption

Sleep mode and auto recovery mode

3.3V/1.2V operation

●8-VSB ATSC Receiver

Integrated de-interleaver RAM for VSB FEC

Symbol timing recovery range up to ± 200ppm

Carrier recovery range up to ± 250kHz

De-ghosting range up to –37usec to +47usec

Improvement of all delay echo cancellation

Full digital carrier/timing recovery and matched filtering

Phase tracking loop for compensating phase error

●64/256QAM ITU-T J.83B Receiver

ITU-T J.83B compliant 64/256 QAM demodulator and FEC

Symbol timing recovery range up to ±200ppm

Carrier recovery range up to ±400kHz

De-ghosting range up to ±12usec

Improvement of all delay echo cancellation

Full digital carrier/timing recovery and matched filtering

Phase tracking loop for compensating phase error

Digital HD/SDTV

Digital set-top box

Digital TV PC card

PIN FUNCTION DESCRIPTION：

Pin Name

Type

Function Pin

GPIO_IN0 I/O TUNER_SDA 1

GPIO_IN1 I GPIO 2

VDD12IH Power Internal Power (1.2V nominal)

3, 9, 21,

31, 35,

45, 50,

63, 69,

86, 91, 93

VSSIPH Power Internal Ground

4, 10, 22,

30, 34,

44, 49,

20

61, 68,

85, 92, 94

PK_DATA[7:0] O MPEG Transport Stream Data 5-8, 11-14

VDD33OPH Power Pad Power (3.3V nominal)

15, 27,

41, 60,

75, 99

VSSOH Power Pad Ground

16, 74,

100

RESET_N I System Reset 17

TEST_BIRA I Connected to GND 18

TEST_SIG[3:0] I Connected to GND

24, 23,

20, 19

PK_CLK O MPEG Clock Signal 25

VSSOH Power Pad Ground 26, 40, 57

PK_SYNC O MPEG Sync Signal 28

PK_ERR O MPEG Error Signal 29

PK_VAL O MPEG Valid Signal 32

EXT_PLL_SEL I Internal/External PLL Selection 33

SDA I/O Serial Bus Data Signal 36

SCL I Serial Clock Signal 37

I2CADDR[1:0] I Device ID Selection 39, 38

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Polaroid TLA-01901C - 19" LCD TV User manual

Polaroid TLA-01901C - 19" LCD TV User manual

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