Freescale Semiconductor, Inc.
Reference Manual
© 2016 Freescale Semiconductor, Inc. All rights reserved.
Rev. 2.0 of the MC56F8458x Reference Manual has two parts:
• The addendum to the reference manual, immediately following this cover page.
• Revision 2.0 of the reference manual, following the addendum. The change described in the
addendum has not been implemented in the specified page of the reference manual.
MC56F8458x Reference Manual with
Addendum
Supports 56F84587, 56F84585, 56F84567, 56F84565
Document Number: MC56F8458XRM
Rev. 2.0, 03/2016
Freescale Semiconductor, Inc.
Reference Manual Addendum
© 2016 Freescale Semiconductor, Inc. All rights reserved.
This addendum identifies a change to Rev. 2.0 of the MC56F8458x Reference Manual. The change
described in this addendum has not been implemented in the specified page of the reference manual.
1 Add paragraph to ADC Scan Control Register
(ADCx_SCTRL) section
In section, 25.3.23 ADC Scan Control Register (ADCx_SCTRL), on page 574, the following paragraph
is added as the last paragraph before the ADCx_SCTRL register illustration:
Use of the SCTRL register values for ADCB is not allowed when the scan is set
to one of the parallel modes and SIMULT is set to zero (independent, parallel
scanning). Therefore, in the parallel mode with SIMULT equal to zero, do not use
the SCTRL bits [4–7 and 12–15] that are dedicated to ADCB.
Document Number: MC56F8458XRMAD
Rev. 0, 03/2016
Addendum to Rev. 2.0 of the
MC56F8458x Reference Manual
MC56F8458x Reference Manual
Supports 56F84587, 56F84585, 56F84567, 56F84565
Document Number: MC56F8458XRM
Rev. 2, 3/2014
MC56F8458x Reference Manual, Rev. 2, 3/2014
2 Freescale Semiconductor, Inc.
Contents
Section number Title Page
Chapter 1
About This Document
1.1 Overview.......................................................................................................................................................................49
1.1.1 Purpose...........................................................................................................................................................49
1.1.2 Audience........................................................................................................................................................49
1.2 Conventions..................................................................................................................................................................49
1.2.1 Numbering systems........................................................................................................................................49
1.2.2 Typographic notation.....................................................................................................................................50
1.2.3 Special terms..................................................................................................................................................50
Chapter 2
Introduction
2.1 Introduction...................................................................................................................................................................51
2.1.1 Core Overview...............................................................................................................................................51
2.1.2 Memory Overview.........................................................................................................................................52
2.1.3 Peripheral Overview......................................................................................................................................52
2.2 Application Examples...................................................................................................................................................52
2.3 Features.........................................................................................................................................................................53
2.3.1 MC56F844x/5x/7x product family................................................................................................................54
2.3.2 Block Diagram...............................................................................................................................................56
2.3.3 56800EX 32-bit Digital Signal Controller Core............................................................................................57
2.3.4 Operation Parameters.....................................................................................................................................58
2.3.5 Packages.........................................................................................................................................................59
2.3.6 On-Chip Memory and Memory Protection....................................................................................................59
2.3.7 Peripherals......................................................................................................................................................59
2.3.7.1 System Modules.........................................................................................................................59
2.3.7.2 General Purpose I/O (GPIO)......................................................................................................61
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2.3.7.3 Timers and PWM modules........................................................................................................61
2.3.7.4 Clock Modules...........................................................................................................................64
2.3.7.5 Analog Modules.........................................................................................................................65
2.3.7.6 Communication Interfaces.........................................................................................................66
2.3.7.7 Power Management....................................................................................................................68
Chapter 3
Chip Configuration
3.1 Introduction...................................................................................................................................................................69
3.2 Digital Signal Controller (DSC) Core Configuration...................................................................................................69
3.3 System modules............................................................................................................................................................70
3.3.1 System Integration Module (SIM) Configuration..........................................................................................70
3.3.2 MCM Configuration......................................................................................................................................71
3.3.3 Inter-Peripheral Crossbar Switch (XBAR) and AND/OR/INVERT (AOI) Configuration...........................72
3.3.3.1 Number of inputs and outputs....................................................................................................72
3.3.3.2 XBARA and XBARB Inputs.....................................................................................................72
3.3.3.3 XBAR Interconnections.............................................................................................................74
3.3.3.4 XBARA Outputs........................................................................................................................75
3.3.3.5 AOI module register write protection........................................................................................77
3.3.4 Interrupt Controller (INTC) Configuration....................................................................................................77
3.3.4.1 Reset/Interrupt Vector Table......................................................................................................78
3.3.5 DMA Controller Configuration.....................................................................................................................87
3.3.5.1 DMA channel assignments........................................................................................................88
3.3.6 Power Management Controller (PMC) Configuration...................................................................................89
3.4 Clock Modules..............................................................................................................................................................90
3.4.1 On-Chip Clock Synthesis (OCCS) Configuration.........................................................................................90
3.5 Memories and Memory Interfaces................................................................................................................................91
3.5.1 Flash Memory Controller (FMC) Configuration...........................................................................................91
3.5.2 Flash Memory Configuration.........................................................................................................................91
3.5.2.1 Flash memory types and terminology........................................................................................92
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3.5.2.2 FTFL_FOPT Register................................................................................................................92
3.6 Security and Integrity....................................................................................................................................................93
3.6.1 Computer Operating Properly (COP) Module Configuration........................................................................93
3.6.1.1 COP low power clocks...............................................................................................................93
3.6.2 External Watchdog Monitor (EWM) Configuration......................................................................................94
3.6.2.1 EWM low power clocks.............................................................................................................94
3.6.2.2 EWM_OUT pin state in Low Power Modes..............................................................................95
3.6.2.3 EWM_IN signal.........................................................................................................................95
3.6.3 Cyclic Redundancy Check (CRC) Configuration..........................................................................................95
3.7 Analog...........................................................................................................................................................................96
3.7.1 SAR Analog-to-Digital Converter (ADC) Configuration..............................................................................96
3.7.1.1 SAR ADC Instantiation.............................................................................................................97
3.7.1.2 SAR ADC Channel Assignments..............................................................................................97
3.7.1.3 SAR ADC clock in stop modes..................................................................................................98
3.7.1.4 SAR ADC alternate clock..........................................................................................................98
3.7.1.5 SAR ADC Reference Options....................................................................................................98
3.7.1.6 SAR ADC Hardware Conversion Trigger Source.....................................................................98
3.7.2 Cyclic Analog-to-Digital Converter (ADC) Configuration...........................................................................99
3.7.2.1 Cyclic ADC Instantiation...........................................................................................................99
3.7.2.2 Cyclic ADC SYNC Signal Connections....................................................................................99
3.7.2.3 Cyclic ADC and PWM Connections.........................................................................................100
3.7.3 Comparator (CMP) Configuration.................................................................................................................100
3.7.3.1 Comparator Channel Assignments.............................................................................................101
3.7.3.2 Comparator Voltage References................................................................................................101
3.7.4 12-bit Digital-to-Analog Converter (DAC) Configuration............................................................................102
3.8 Timers and PWM..........................................................................................................................................................102
3.8.1 PWM Configuration.......................................................................................................................................102
3.8.1.1 PWM auxiliary signals and analog inputs..................................................................................103
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3.8.2 PDB Configuration........................................................................................................................................103
3.8.2.1 PDB Trigger Connections..........................................................................................................104
3.8.3 PIT Configuration..........................................................................................................................................105
3.8.3.1 PIT low power clocks................................................................................................................105
3.8.3.2 PIT master/slave selection.........................................................................................................106
3.8.4 TMR Configuration........................................................................................................................................106
3.8.5 ENC Configuration........................................................................................................................................107
3.9 Communication interfaces............................................................................................................................................107
3.9.1 CAN Configuration........................................................................................................................................107
3.9.1.1 FlexCAN3 glitch filter...............................................................................................................108
3.9.1.2 FlexCAN3 Supervisor Mode.....................................................................................................108
3.9.2 Serial Peripheral Interface (SPI) Configuration.............................................................................................109
3.9.3 Inter-Integrated Circuit (I2C) Configuration.................................................................................................109
3.9.4 I2C module address matching to wake the device from stop mode...............................................................110
3.9.5 SCI Configuration..........................................................................................................................................111
3.10 Human-machine interfaces (HMI)................................................................................................................................111
3.10.1 GPIO Configuration.......................................................................................................................................111
3.10.1.1 GPIO Port D[4:0] configuration................................................................................................112
3.10.1.2 GPIO unbonded pads.................................................................................................................113
Chapter 4
Memory Map
4.1 Introduction...................................................................................................................................................................115
4.2 Program/Data Memory Maps.......................................................................................................................................115
4.3 Core and System Peripheral Memory Map...................................................................................................................116
4.4 Slave Peripheral Memory Map.....................................................................................................................................117
Chapter 5
Clock Distribution
5.1 Overview.......................................................................................................................................................................121
5.2 Clock definitions...........................................................................................................................................................121
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5.3 System clock source configuration...............................................................................................................................122
5.4 Module clocks...............................................................................................................................................................123
Chapter 6
Reset and Boot
6.1 Reset Configuration......................................................................................................................................................125
6.2 System Boot..................................................................................................................................................................126
6.2.1 FOPT boot options.........................................................................................................................................126
6.2.2 Boot Procedure for Normal Operation...........................................................................................................126
6.2.3 Boot sequence................................................................................................................................................127
Chapter 7
Power Management
7.1 Overview.......................................................................................................................................................................129
7.2 Architecture...................................................................................................................................................................129
7.3 External Supplies and Regulation.................................................................................................................................130
7.4 User Power Management Methods...............................................................................................................................130
7.5 Power Modes................................................................................................................................................................131
7.6 Power mode transitions.................................................................................................................................................133
Chapter 8
Signal Multiplexing and Signal Descriptions
8.1 Introduction...................................................................................................................................................................137
8.2 Signal Multiplexing Integration....................................................................................................................................137
8.3 Signal Multiplexing and Pin Assignments....................................................................................................................138
8.4 Pinout diagrams............................................................................................................................................................140
Chapter 9
Memory Resource Protection (MRP)
9.1 Overview.......................................................................................................................................................................143
9.2 Features.........................................................................................................................................................................144
9.3 Operation.......................................................................................................................................................................144
9.4 Programming Model Overview....................................................................................................................................148
9.5 Memory Resource Protection Restrictions...................................................................................................................148
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9.6 Base Address Setup.......................................................................................................................................................148
9.7 Programming Example.................................................................................................................................................150
Chapter 10
Miscellaneous Control Module (MCM)
10.1 Introduction...................................................................................................................................................................153
10.1.1 Features..........................................................................................................................................................153
10.2 Memory Map/Register Descriptions.............................................................................................................................154
10.2.1 Crossbar switch (AXBS) slave configuration (MCM_PLASC)....................................................................155
10.2.2 Crossbar switch (AXBS) master configuration (MCM_PLAMC)................................................................155
10.2.3 Core control register (MCM_CPCR).............................................................................................................156
10.2.4 Core fault address register (MCM_CFADR).................................................................................................157
10.2.5 Core fault attributes register (MCM_CFATR)..............................................................................................158
10.2.6 Core fault location register (MCM_CFLOC)................................................................................................159
10.2.7 Core fault interrupt enable register (MCM_CFIER)......................................................................................160
10.2.8 MCM interrupt status register (MCM_CFISR).............................................................................................160
10.2.9 Core fault data register (MCM_CFDTR).......................................................................................................161
10.2.10 Resource Protection Control Register (MCM_RPCR)..................................................................................162
10.2.11 User Flash Base Address Register (MCM_UFLASHBAR)..........................................................................163
10.2.12 User Program RAM Base Address Register (MCM_UPRAMBAR)............................................................163
10.2.13 Resource Protection Other Stack Pointer (MCM_SRPOSP).........................................................................164
10.2.14 Memory Protection Illegal PC (MCM_SRPIPC)...........................................................................................164
10.2.15 Resource Protection Misaligned PC (MCM_SRPMPC)...............................................................................166
10.3 Functional Description..................................................................................................................................................167
10.3.1 Core Data Fault Recovery Registers..............................................................................................................167
Chapter 11
System Integration Module (SIM)
11.1 Introduction...................................................................................................................................................................169
11.1.1 Overview........................................................................................................................................................169
11.1.2 Features..........................................................................................................................................................169
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11.1.3 Modes of Operation.......................................................................................................................................170
11.1.4 Block Diagram...............................................................................................................................................171
11.2 Memory Map and Register Descriptions......................................................................................................................173
11.2.1 Control Register (SIM_CTRL)......................................................................................................................174
11.2.2 Reset Status Register (SIM_RSTAT)............................................................................................................176
11.2.3 Software Control Register (SIM_SCR0).......................................................................................................177
11.2.4 Software Control Register (SIM_SCR1).......................................................................................................178
11.2.5 Software Control Register (SIM_SCR2).......................................................................................................178
11.2.6 Software Control Register (SIM_SCR3).......................................................................................................178
11.2.7 Most Significant Half of JTAG ID (SIM_MSHID).......................................................................................179
11.2.8 Least Significant Half of JTAG ID (SIM_LSHID).......................................................................................180
11.2.9 Power Control Register (SIM_PWR)............................................................................................................181
11.2.10 Clock Output Select Register (SIM_CLKOUT)............................................................................................182
11.2.11 Peripheral Clock Rate Register (SIM_PCR)..................................................................................................184
11.2.12 Peripheral Clock Enable Register 0 (SIM_PCE0).........................................................................................185
11.2.13 Peripheral Clock Enable Register 1 (SIM_PCE1).........................................................................................187
11.2.14 Peripheral Clock Enable Register 2 (SIM_PCE2).........................................................................................189
11.2.15 Peripheral Clock Enable Register 3 (SIM_PCE3).........................................................................................191
11.2.16 STOP Disable Register 0 (SIM_SD0)...........................................................................................................192
11.2.17 Peripheral Clock STOP Disable Register 1 (SIM_SD1)...............................................................................195
11.2.18 Peripheral Clock STOP Disable Register 2 (SIM_SD2)...............................................................................197
11.2.19 Peripheral Clock STOP Disable Register 3 (SIM_SD3)...............................................................................200
11.2.20 I/O Short Address Location Register (SIM_IOSAHI)...................................................................................202
11.2.21 I/O Short Address Location Register (SIM_IOSALO)..................................................................................202
11.2.22 Protection Register (SIM_PROT)..................................................................................................................203
11.2.23 GPIOA LSBs Peripheral Select Register (SIM_GPSAL)..............................................................................205
11.2.24 GPIOB MSBs Peripheral Select Register (SIM_GPSBH)............................................................................206
11.2.25 GPIOC LSBs Peripheral Select Register (SIM_GPSCL)..............................................................................207
11.2.26 GPIOC MSBs Peripheral Select Register (SIM_GPSCH)............................................................................208
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11.2.27 GPIOD LSBs Peripheral Select Register (SIM_GPSDL)..............................................................................210
11.2.28 GPIOE LSBs Peripheral Select Register (SIM_GPSEL)..............................................................................210
11.2.29 GPIOE MSBs Peripheral Select Register (SIM_GPSEH).............................................................................211
11.2.30 GPIOF LSBs Peripheral Select Register (SIM_GPSFL)...............................................................................212
11.2.31 GPIOF MSBs Peripheral Select Register (SIM_GPSFH).............................................................................213
11.2.32 GPIOG LSBs Peripheral Select Register (SIM_GPSGL)..............................................................................215
11.2.33 GPIOG MSBs Peripheral Select Register (SIM_GPSGH)............................................................................216
11.2.34 Internal Peripheral Select Register 0 (SIM_IPS0).........................................................................................217
11.2.35 Miscellaneous Register 0 (SIM_MISC0).......................................................................................................220
11.2.36 Peripheral Software Reset Register 0 (SIM_PSWR0)...................................................................................220
11.2.37 Peripheral Software Reset Register 1 (SIM_PSWR1)...................................................................................221
11.2.38 Peripheral Software Reset Register 2 (SIM_PSWR2)...................................................................................223
11.2.39 Peripheral Software Reset Register 3 (SIM_PSWR3)...................................................................................225
11.2.40 Power Mode Register (SIM_PWRMODE)....................................................................................................226
11.2.41 Non-Volatile Memory Option Register 2 (High) (SIM_NVMOPT2H)........................................................227
11.2.42 Non-Volatile Memory Option Register 2 (Low) (SIM_NVMOPT2L).........................................................228
11.2.43 Non-Volatile Memory Option Register 3 (High) (SIM_NVMOPT3H)........................................................228
11.3 Functional Description..................................................................................................................................................229
11.3.1 Clock Generation Overview...........................................................................................................................229
11.3.2 Power-Down Modes Overview......................................................................................................................230
11.3.3 STOP and WAIT Mode Disable Function.....................................................................................................231
11.4 Resets............................................................................................................................................................................232
11.5 Clocks...........................................................................................................................................................................232
11.6 Interrupts.......................................................................................................................................................................232
Chapter 12
Interrupt Controller (INTC)
12.1 Introduction...................................................................................................................................................................233
12.1.1 References......................................................................................................................................................233
12.1.2 Features..........................................................................................................................................................233
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12.1.3 Modes of Operation.......................................................................................................................................233
12.1.4 Block Diagram...............................................................................................................................................234
12.2 Memory Map and Registers..........................................................................................................................................235
12.2.1 Interrupt Priority Register 0 (INTC_IPR0)....................................................................................................236
12.2.2 Interrupt Priority Register 1 (INTC_IPR1)....................................................................................................237
12.2.3 Interrupt Priority Register 2 (INTC_IPR2)....................................................................................................239
12.2.4 Interrupt Priority Register 3 (INTC_IPR3)....................................................................................................240
12.2.5 Interrupt Priority Register 4 (INTC_IPR4)....................................................................................................242
12.2.6 Interrupt Priority Register 5 (INTC_IPR5)....................................................................................................244
12.2.7 Interrupt Priority Register 6 (INTC_IPR6)....................................................................................................245
12.2.8 Interrupt Priority Register 7 (INTC_IPR7)....................................................................................................247
12.2.9 Interrupt Priority Register 8 (INTC_IPR8)....................................................................................................249
12.2.10 Interrupt Priority Register 9 (INTC_IPR9)....................................................................................................251
12.2.11 Interrupt Priority Register 10 (INTC_IPR10)................................................................................................252
12.2.12 Interrupt Priority Register 11 (INTC_IPR11)................................................................................................254
12.2.13 Interrupt Priority Register 12 (INTC_IPR12)................................................................................................256
12.2.14 Vector Base Address Register (INTC_VBA)................................................................................................257
12.2.15 Fast Interrupt 0 Match Register (INTC_FIM0).............................................................................................257
12.2.16 Fast Interrupt 0 Vector Address Low Register (INTC_FIVAL0)..................................................................258
12.2.17 Fast Interrupt 0 Vector Address High Register (INTC_FIVAH0)................................................................258
12.2.18 Fast Interrupt 1 Match Register (INTC_FIM1).............................................................................................259
12.2.19 Fast Interrupt 1 Vector Address Low Register (INTC_FIVAL1)..................................................................259
12.2.20 Fast Interrupt 1 Vector Address High Register (INTC_FIVAH1)................................................................260
12.2.21 IRQ Pending Register 0 (INTC_IRQP0).......................................................................................................260
12.2.22 IRQ Pending Register 1 (INTC_IRQP1).......................................................................................................261
12.2.23 IRQ Pending Register 2 (INTC_IRQP2).......................................................................................................261
12.2.24 IRQ Pending Register 3 (INTC_IRQP3).......................................................................................................262
12.2.25 IRQ Pending Register 4 (INTC_IRQP4).......................................................................................................262
12.2.26 IRQ Pending Register 5 (INTC_IRQP5).......................................................................................................263
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12.2.27 IRQ Pending Register 6 (INTC_IRQP6).......................................................................................................263
12.2.28 Control Register (INTC_CTRL)....................................................................................................................264
12.3 Functional Description..................................................................................................................................................265
12.3.1 Normal Interrupt Handling.............................................................................................................................265
12.3.2 Interrupt Nesting............................................................................................................................................265
12.3.3 Fast Interrupt Handling..................................................................................................................................266
12.4 Resets............................................................................................................................................................................266
12.4.1 INTC after Reset............................................................................................................................................266
12.5 Clocks...........................................................................................................................................................................267
12.5.1 System Clock.................................................................................................................................................267
12.5.2 IPS Bus Clock................................................................................................................................................267
12.6 Interrupts.......................................................................................................................................................................267
Chapter 13
DMA Controller
13.1 Introduction...................................................................................................................................................................269
13.1.1 Overview........................................................................................................................................................269
13.1.2 Features..........................................................................................................................................................270
13.2 DMA Transfer Overview..............................................................................................................................................271
13.3 Memory Map and Registers..........................................................................................................................................272
13.3.1 DMA Request Control Register (DMA_REQC)...........................................................................................273
13.3.2 Source Address Register (DMA_SARn).......................................................................................................277
13.3.3 Destination Address Register (DMA_DARn)...............................................................................................278
13.3.4 DMA Status Register / Byte Count Register (DMA_DSR_BCRn)...............................................................278
13.3.5 DMA Control Register (DMA_DCRn)..........................................................................................................281
13.4 Functional Description..................................................................................................................................................284
13.4.1 Transfer Requests (Cycle-Steal and Continuous Modes)..............................................................................285
13.4.2 Channel Initialization and Startup..................................................................................................................285
13.4.2.1 Channel Prioritization................................................................................................................285
13.4.2.2 Programming the DMA Controller Module...............................................................................286
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13.4.3 Dual-Address Data Transfer Mode................................................................................................................287
13.4.4 Advanced Data Transfer Controls: Auto-Alignment.....................................................................................288
13.4.5 Termination....................................................................................................................................................288
Chapter 14
Power Management Controller (PMC)
14.1 Introduction...................................................................................................................................................................291
14.1.1 Overview........................................................................................................................................................291
14.1.2 Features..........................................................................................................................................................291
14.1.3 Modes of Operation.......................................................................................................................................292
14.1.4 Block Diagram...............................................................................................................................................293
14.2 Memory Map and Register Descriptions......................................................................................................................294
14.2.1 Control Register (PMC_CTRL).....................................................................................................................295
14.2.2 Status Register (PMC_STS)...........................................................................................................................296
14.3 Functional Description..................................................................................................................................................298
14.4 Resets............................................................................................................................................................................299
14.5 Clocks...........................................................................................................................................................................299
14.6 Interrupts.......................................................................................................................................................................300
Chapter 15
Crossbar AND/OR/INVERT (AOI) Module
15.1 Introduction...................................................................................................................................................................301
15.1.1 Overview........................................................................................................................................................301
15.1.2 Features..........................................................................................................................................................303
15.1.3 Modes of Operation.......................................................................................................................................303
15.2 External Signal Description..........................................................................................................................................303
15.3 Memory Map and Register Descriptions......................................................................................................................303
15.3.1 Boolean Function Term 0 and 1 Configuration Register for EVENTn (AOI_BFCRT01n)..........................305
15.3.2 Boolean Function Term 2 and 3 Configuration Register for EVENTn (AOI_BFCRT23n)..........................306
15.4 Functional Description..................................................................................................................................................308
15.4.1 Configuration Examples for the Boolean Function Evaluation.....................................................................309
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15.4.2 AOI Timing Between Inputs and Outputs.....................................................................................................310
Chapter 16
Inter-Peripheral Crossbar Switch A (XBARA)
16.1 Introduction...................................................................................................................................................................313
16.1.1 Overview........................................................................................................................................................313
16.1.2 Features..........................................................................................................................................................313
16.1.3 Modes of Operation.......................................................................................................................................314
16.1.4 Block Diagram...............................................................................................................................................314
16.2 Signal Descriptions.......................................................................................................................................................315
16.2.1 XBAR_OUT[0:NUM_OUT-1] - MUX Outputs...........................................................................................315
16.2.2 XBAR_IN[0:NUM_IN-1] - MUX Inputs......................................................................................................315
16.2.3 PROT_GIPSP_B Input..................................................................................................................................315
16.2.4 DMA_REQ[n] - DMA Request Output(s).....................................................................................................315
16.2.5 DMA_ACK[n] - DMA Acknowledge Input(s)..............................................................................................316
16.2.6 INT_REQ[n] - Interrupt Request Output(s)...................................................................................................316
16.3 Memory Map and Register Descriptions......................................................................................................................316
16.3.1 Crossbar A Select Register 0 (XBARA_SEL0).............................................................................................317
16.3.2 Crossbar A Select Register 1 (XBARA_SEL1).............................................................................................318
16.3.3 Crossbar A Select Register 2 (XBARA_SEL2).............................................................................................318
16.3.4 Crossbar A Select Register 3 (XBARA_SEL3).............................................................................................319
16.3.5 Crossbar A Select Register 4 (XBARA_SEL4).............................................................................................319
16.3.6 Crossbar A Select Register 5 (XBARA_SEL5).............................................................................................320
16.3.7 Crossbar A Select Register 6 (XBARA_SEL6).............................................................................................320
16.3.8 Crossbar A Select Register 7 (XBARA_SEL7).............................................................................................321
16.3.9 Crossbar A Select Register 8 (XBARA_SEL8).............................................................................................321
16.3.10 Crossbar A Select Register 9 (XBARA_SEL9).............................................................................................322
16.3.11 Crossbar A Select Register 10 (XBARA_SEL10).........................................................................................322
16.3.12 Crossbar A Select Register 11 (XBARA_SEL11).........................................................................................323
16.3.13 Crossbar A Select Register 12 (XBARA_SEL12).........................................................................................323
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16.3.14 Crossbar A Select Register 13 (XBARA_SEL13).........................................................................................324
16.3.15 Crossbar A Select Register 14 (XBARA_SEL14).........................................................................................324
16.3.16 Crossbar A Select Register 15 (XBARA_SEL15).........................................................................................325
16.3.17 Crossbar A Select Register 16 (XBARA_SEL16).........................................................................................325
16.3.18 Crossbar A Select Register 17 (XBARA_SEL17).........................................................................................326
16.3.19 Crossbar A Select Register 18 (XBARA_SEL18).........................................................................................326
16.3.20 Crossbar A Select Register 19 (XBARA_SEL19).........................................................................................327
16.3.21 Crossbar A Select Register 20 (XBARA_SEL20).........................................................................................327
16.3.22 Crossbar A Select Register 21 (XBARA_SEL21).........................................................................................328
16.3.23 Crossbar A Select Register 22 (XBARA_SEL22).........................................................................................328
16.3.24 Crossbar A Select Register 23 (XBARA_SEL23).........................................................................................329
16.3.25 Crossbar A Select Register 24 (XBARA_SEL24).........................................................................................329
16.3.26 Crossbar A Select Register 25 (XBARA_SEL25).........................................................................................330
16.3.27 Crossbar A Select Register 26 (XBARA_SEL26).........................................................................................330
16.3.28 Crossbar A Select Register 27 (XBARA_SEL27).........................................................................................331
16.3.29 Crossbar A Select Register 28 (XBARA_SEL28).........................................................................................331
16.3.30 Crossbar A Select Register 29 (XBARA_SEL29).........................................................................................332
16.3.31 Crossbar A Control Register 0 (XBARA_CTRL0).......................................................................................332
16.3.32 Crossbar A Control Register 1 (XBARA_CTRL1).......................................................................................334
16.4 Functional Description..................................................................................................................................................336
16.4.1 General...........................................................................................................................................................336
16.4.2 Functional Mode............................................................................................................................................337
16.5 Resets............................................................................................................................................................................337
16.6 Clocks...........................................................................................................................................................................337
16.7 Interrupts and DMA Requests......................................................................................................................................337
Chapter 17
Inter-Peripheral Crossbar Switch B (XBARB): AOI Input
17.1 Introduction...................................................................................................................................................................339
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17.2 Memory Map and Register Descriptions......................................................................................................................339
17.2.1 Crossbar B Select Register 0 (XBARB_SEL0).............................................................................................340
17.2.2 Crossbar B Select Register 1 (XBARB_SEL1).............................................................................................340
17.2.3 Crossbar B Select Register 2 (XBARB_SEL2).............................................................................................341
17.2.4 Crossbar B Select Register 3 (XBARB_SEL3).............................................................................................341
17.2.5 Crossbar B Select Register 4 (XBARB_SEL4).............................................................................................342
17.2.6 Crossbar B Select Register 5 (XBARB_SEL5).............................................................................................342
17.2.7 Crossbar B Select Register 6 (XBARB_SEL6).............................................................................................343
17.2.8 Crossbar B Select Register 7 (XBARB_SEL7).............................................................................................343
Chapter 18
On-Chip Clock Synthesis (OCCS)
18.1 Introduction...................................................................................................................................................................345
18.1.1 Overview........................................................................................................................................................345
18.1.2 Features..........................................................................................................................................................345
18.2 Modes of Operation......................................................................................................................................................346
18.2.1 Internal Clock Sources...................................................................................................................................347
18.2.2 Loop Controlled Pierce Crystal Oscillator.....................................................................................................347
18.2.3 External Clock Source - Crystal Oscillator Bypass Option...........................................................................348
18.2.4 External Clock Source - CLKIN....................................................................................................................348
18.3 Block Diagram..............................................................................................................................................................350
18.4 Pin Description..............................................................................................................................................................351
18.4.1 External Clock Reference..............................................................................................................................351
18.4.2 Oscillator IO (XTAL, EXTAL).....................................................................................................................351
18.4.3 CLKO.............................................................................................................................................................351
18.5 Memory Map and Register Descriptions......................................................................................................................352
18.5.1 PLL Control Register (OCCS_CTRL)...........................................................................................................352
18.5.2 PLL Divide-By Register (OCCS_DIVBY)....................................................................................................354
18.5.3 OCCS Status Register (OCCS_STAT)..........................................................................................................355
18.5.4 Oscillator Control Register 1 (OCCS_OSCTL1)...........................................................................................357
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18.5.5 Oscillator Control Register 2 (OCCS_OSCTL2)...........................................................................................358
18.5.6 External Clock Check Reference (OCCS_CLKCHKR)................................................................................360
18.5.7 External Clock Check Target (OCCS_CLKCHKT)......................................................................................361
18.5.8 Protection Register (OCCS_PROT)...............................................................................................................361
18.6 Functional Description..................................................................................................................................................362
18.7 Relaxation Oscillators...................................................................................................................................................366
18.7.1 Trimming Frequency on the Internal 8 MHz Relaxation Oscillator..............................................................366
18.7.2 Trimming Frequency on the Internal 32 kHz Relaxation Oscillator.............................................................366
18.8 External Reference........................................................................................................................................................367
18.9 Crystal Oscillator..........................................................................................................................................................367
18.9.1 Switching Clock Sources...............................................................................................................................367
18.10 Phase Locked Loop.......................................................................................................................................................369
18.10.1 PLL Recommended Range of Operation.......................................................................................................369
18.10.2 PLL Lock Time Specification........................................................................................................................369
18.10.2.1 Lock Time Definition.................................................................................................................369
18.10.2.2 Parametric Influences on Reaction Time...................................................................................369
18.11 PLL Frequency Lock Detector Block...........................................................................................................................370
18.12 Loss of Reference Clock Detector................................................................................................................................370
18.13 Resets............................................................................................................................................................................371
18.13.1 Resets.............................................................................................................................................................371
18.14 Clocks...........................................................................................................................................................................371
18.15 Interrupts.......................................................................................................................................................................372
Chapter 19
Flash Memory Controller (FMC)
19.1 Introduction...................................................................................................................................................................373
19.1.1 Overview........................................................................................................................................................373
19.1.2 Features..........................................................................................................................................................374
19.2 Modes of operation.......................................................................................................................................................374
19.3 External signal description............................................................................................................................................374
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19.4 Memory map and register descriptions.........................................................................................................................374
19.4.1 Flash Access Protection Register (FMC_PFAPR).........................................................................................379
19.4.2 Flash Bank 0 Control Register (FMC_PFB0CR)..........................................................................................381
19.4.3 Flash Bank 1 Control Register (FMC_PFB1CR)..........................................................................................383
19.4.4 Cache Tag Storage (FMC_TAGVDW0Sn)...................................................................................................384
19.4.5 Cache Tag Storage (FMC_TAGVDW1Sn)...................................................................................................385
19.4.6 Cache Tag Storage (FMC_TAGVDW2Sn)...................................................................................................386
19.4.7 Cache Tag Storage (FMC_TAGVDW3Sn)...................................................................................................387
19.4.8 Cache Data Storage (upper word) (FMC_DATAW0SnU)............................................................................387
19.4.9 Cache Data Storage (lower word) (FMC_DATAW0SnL)............................................................................388
19.4.10 Cache Data Storage (upper word) (FMC_DATAW1SnU)............................................................................388
19.4.11 Cache Data Storage (lower word) (FMC_DATAW1SnL)............................................................................389
19.4.12 Cache Data Storage (upper word) (FMC_DATAW2SnU)............................................................................389
19.4.13 Cache Data Storage (lower word) (FMC_DATAW2SnL)............................................................................390
19.4.14 Cache Data Storage (upper word) (FMC_DATAW3SnU)............................................................................390
19.4.15 Cache Data Storage (lower word) (FMC_DATAW3SnL)............................................................................391
19.5 Functional description...................................................................................................................................................391
19.5.1 Default configuration.....................................................................................................................................391
19.5.2 Configuration options....................................................................................................................................392
19.5.3 Wait states......................................................................................................................................................392
19.5.4 Speculative reads............................................................................................................................................393
19.6 Initialization and application information.....................................................................................................................394
Chapter 20
Flash Memory Module (FTFL)
20.1 Introduction...................................................................................................................................................................395
20.1.1 Features..........................................................................................................................................................396
20.1.1.1 Program Flash Memory Features...............................................................................................396
20.1.1.2 FlexNVM Memory Features......................................................................................................396
20.1.1.3 FlexRAM Features.....................................................................................................................396
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