Freescale Semiconductor MCF54455 Reference guide
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© Freescale Semiconductor, Inc., 2012. All rights reserved.
Freescale Semiconductor
MCF54455RM
Rev. 6.1, 03/2012
This is the MCF54455 Reference Manual set consisting of the following files:
• MCF54455 Reference Manual Errata, Rev 1
• MCF54455 Reference Manual, Rev 6
MCF54455 Reference Manual
by: Microcontroller Solutions Group
© Freescale Semiconductor, Inc., 2011. All rights reserved.
Freescale Semiconductor
Reference Manual Errata
MCF54455RMAD
Rev. 1, 11/2011
Table of Contents
This errata document describes corrections to the
MCF54455 Reference Manual, order number
MC54455RM. For convenience, the addenda items are
grouped by revision. Please check our website at
http://www.freescale.com for the latest updates.
The current available version of the MCF54455
Reference Manual is Revision 6.
MCF54455 Reference Manual
Errata
by: Microcontroller Solutions Group
1 Errata for Revision 6 . . . . . . . . . . . . . . . . . . . . . . . 2
2 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . 2
MCF54455 Reference Manual Errata, Rev. 1
Errata for Revision 6
Freescale Semiconductor2
1 Errata for Revision 6
2 Revision History
Table 2 provides a revision history for this document.
Table 1. MCF54455 Reference Manual Rev 6 Errata
Location Description
Section 16.2, “External Signal
Description”/Table 16-2/Page
16-11
Add pin N7 to the VSS pin list for the 360 TEPBGA.
Table 2. Revision History Table
Rev. Number Substantive Changes Date of Release
1.0 Initial release. Correct errors in section 16.2, “External Signal Description”. 11/2011
MCF54455 Reference Manual Errata, Rev. 1
Freescale Semiconductor 3
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© Freescale Semiconductor, Inc. 2011. All rights reserved.
MCF54455RMAD
Rev. 1
November 2011
MCF54455 Reference Manual
Devices Supported:
MCF54450
MCF54451
MCF54452
MCF54453
MCF54454
MCF54455
Document Number: MCF54455RM
Rev. 6
5/2011
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MCF54455RM
Rev. 6
5/2011
Freescale Semiconductor iii
Table of Contents
About This Book .............................................................................................................xxv
Audience .................................................................................................................xxv
Suggested Reading ..................................................................................................xxv
General Information ................................................................................................xxv
ColdFire Documentation ...................................................................................... xxvi
Conventions .......................................................................................................... xxvi
Register Figure Conventions ............................................................................... xxvii
Chapter 1
Overview
1.1 MCF5445x Family Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1.3 Operating Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.4 Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.5 Chip Level Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.6 Module-by-Module Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.6.1 Version 4 ColdFire variable-length RISC processor . . . . . . . . . . . . . . . . . . . . . 1-5
1.6.2 On-chip Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1.6.3 Phase Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1.6.4 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1.6.5 Chip Configuration Module (CCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1.6.6 Reset Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1.6.7 System Control Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1.6.8 Crossbar Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1.6.9 Peripheral Component Interconnect (PCI) Bus . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1.6.10 Universal Serial Bus (USB) 2.0 On-The-Go (OTG) Controller . . . . . . . . . . . . . 1-6
1.6.11 DDR SDRAM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1.6.12 FlexBus (External Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
1.6.13 Synchronous Serial Interface (SSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
1.6.14 ATA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
1.6.15 Fast Ethernet Media Access Controller (FEC MAC) . . . . . . . . . . . . . . . . . . . . . 1-7
1.6.16 Random Number Generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
1.6.17 Real Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
1.6.18 Software Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
1.6.19 Programmable Interrupt Timers (PIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
1.6.20 DMA Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
1.6.21 DMA Serial Peripheral Interface (DSPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
1.6.22 Universal Asynchronous Receiver Transmitters (UARTs) . . . . . . . . . . . . . . . . 1-9
iv Freescale Semiconductor
1.6.23 I2C Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
1.6.24 Interrupt Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
1.6.25 Edge Port Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
1.6.26 DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
1.6.27 General Purpose I/O interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
1.6.28 System Debug Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
1.6.29 JTAG Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
1.7 Memory Map Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
1.7.1 Internal Peripheral Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
1.8 Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
Chapter 2
Signal Descriptions
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.2 Signal Properties Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.3 Signal Primary Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.3.1 Reset Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.3.2 PLL and Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.3.3 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.3.4 FlexBus Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
2.3.5 SDRAM Controller Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
2.3.6 PCI Controller Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2.3.7 Serial Boot Facility Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2.3.8 External Interrupt Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2.3.9 DMA Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2.3.10 Fast Ethernet Controller (FEC0 and FEC1) Signals . . . . . . . . . . . . . . . . . . . . 2-14
2.3.11 I2C I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
2.3.12 ATA Controller Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
2.3.13 DMA Serial Peripheral Interface (DSPI) Signals . . . . . . . . . . . . . . . . . . . . . . . 2-17
2.3.14 Synchronous Serial Interface (SSI) Signals . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
2.3.15 Universal Serial Bus (USB) Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
2.3.16 UART Module Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
2.3.17 DMA Timer Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
2.3.18 Debug Support Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
2.3.19 Test Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
2.3.20 Power and Ground Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
2.4 External Boot Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
Chapter 3
ColdFire Core
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Freescale Semiconductor v
3.2 Memory Map/Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
3.2.1 Data Registers (D0–D7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
3.2.2 Address Registers (A0–A6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
3.2.3 Supervisor/User Stack Pointers (A7 and OTHER_A7) . . . . . . . . . . . . . . . . . . . 3-8
3.2.4 Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3.2.5 Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
3.2.6 Cache Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
3.2.7 MMU Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
3.2.8 Vector Base Register (VBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
3.2.9 Status Register (SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
3.2.10 Memory Base Address Register (RAMBAR) . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
3.3.1 Version 4 ColdFire Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
3.3.2 Instruction Set Architecture (ISA_C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
3.3.3 Exception Processing Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
3.3.4 Processor Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18
3.3.5 Instruction Execution Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27
Chapter 4
Memory Management Unit (MMU)
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4.2 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
4.2.1 Address Space ID (ASID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4.2.2 MMU Base Address Register (MMUBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4.2.3 MMU Control Register (MMUCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
4.2.4 MMU Operation Register (MMUOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
4.2.5 MMU Status Register (MMUSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
4.2.6 MMU Fault, Test, or TLB Address Register (MMUAR) . . . . . . . . . . . . . . . . . . . 4-8
4.2.7 MMU Read/Write Tag Entry Registers (MMUTR) . . . . . . . . . . . . . . . . . . . . . . . 4-8
4.2.8 MMU Read/Write Data Entry Register (MMUDR) . . . . . . . . . . . . . . . . . . . . . . . 4-9
4.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
4.3.1 Virtual Memory Management Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
4.3.2 Debugging in a Virtual Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15
4.3.3 Virtual Memory Architecture Processor Support . . . . . . . . . . . . . . . . . . . . . . . 4-15
4.3.4 Effective Address Attribute Determination . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17
4.3.5 MMU Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18
4.3.6 MMU TLB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18
4.3.7 MMU Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18
4.3.8 MMU Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20
4.3.9 MMU Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23
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Chapter 5
Enhanced Multiply-Accumulate Unit (EMAC)
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.2 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
5.2.1 MAC Status Register (MACSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
5.2.2 Mask Register (MASK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
5.2.3 Accumulator Registers (ACC0–3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
5.2.4 Accumulator Extension Registers (ACCext01, ACCext23) . . . . . . . . . . . . . . . . 5-8
5.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
5.3.1 Fractional Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
5.3.2 EMAC Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
5.3.3 EMAC Instruction Execution Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
5.3.4 Data Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
5.3.5 MAC Opcodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
Chapter 6
Cache
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
6.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
6.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
6.2 Cache Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
6.2.1 Cache Line States: Invalid, Valid-Unmodified, and Valid-Modified . . . . . . . . . . 6-3
6.2.2 The Cache at Start-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
6.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
6.3.1 Cache Control Register (CACR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
6.3.2 Access Control Registers (ACRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
6.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9
6.4.1 Caching Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12
6.4.2 Cache Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14
6.4.3 Cache Coherency (Data Cache Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16
6.4.4 Memory Accesses for Cache Maintenance . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16
6.4.5 Cache Locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17
6.4.6 Cache Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20
6.4.7 Cache Operation Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22
6.4.8 CPUSHL Enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26
6.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-28
Chapter 7
Static RAM (SRAM)
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
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7.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
7.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
7.2 Memory Map/Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
7.2.1 SRAM Base Address Register (RAMBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
7.3 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
7.3.1 SRAM Initialization Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
7.3.2 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
Chapter 8
Clock Module
8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
8.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
8.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
8.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
8.2 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5
8.2.1 PLL Control Register (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6
8.2.2 PLL Status Register (PSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8
8.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9
8.3.1 PLL Frequency Multiplication Factor Select . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9
8.3.2 Lock Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10
8.3.3 Loss-of-Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10
8.3.4 System Clock Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11
8.3.5 Clock Operation During Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12
Chapter 9
Power Management
9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
9.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
9.2 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
9.2.1 Wake-up Control Register (WCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
9.2.2 Peripheral Power Management Set Register (PPMSR0) . . . . . . . . . . . . . . . . . 9-3
9.2.3 Peripheral Power Management Clear Register (PPMCR0) . . . . . . . . . . . . . . . 9-4
9.2.4 Peripheral Power Management Registers (PPMHR0 and PPMLR0) . . . . . . . 9-4
9.2.5 Low-Power Control Register (LPCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7
9.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7
9.3.1 Peripheral Shut Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8
9.3.2 Limp mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8
9.3.3 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8
9.3.4 Peripheral Behavior in Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9
9.3.5 Summary of Peripheral State During Low-power Modes . . . . . . . . . . . . . . . . 9-14
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Chapter 10
Universal Serial Bus Interface – On-The-Go Module
10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
10.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
10.1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
10.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
10.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
10.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
10.2.1 USB OTG Control and Status Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6
10.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7
10.3.1 Module Identification Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
10.3.2 Device/Host Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13
10.3.3 Capability Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14
10.3.4 Operational Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-18
10.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-47
10.4.1 System Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-47
10.4.2 DMA Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-47
10.4.3 FIFO RAM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-47
10.4.4 Physical Layer (PHY) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-47
10.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-48
10.5.1 Host Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-48
10.5.2 Device Data Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-49
10.5.3 Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-56
10.5.4 Servicing Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-74
10.5.5 Deviations from the EHCI Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-75
Chapter 11
Chip Configuration Module (CCM)
11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
11.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
11.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
11.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
11.2 External Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
11.2.1 BOOTMOD[1:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
11.2.2 FB_AD[7:0] (Reset Configuration Override) . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
11.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
11.3.1 Chip Configuration Register (CCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
11.3.2 Reset Configuration Register (RCON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7
11.3.3 Chip Identification Register (CIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8
11.3.4 Miscellaneous Control Register (MISCCR) . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8
11.3.5 Clock-Divider Register (CDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11
11.3.6 USB On-the-Go Controller Status Register (UOCSR) . . . . . . . . . . . . . . . . . 11-11
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11.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13
11.4.1 Reset Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13
11.4.2 Boot Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-19
11.4.3 Low Power Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-20
Chapter 12
Serial Boot Facility (SBF)
12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
12.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
12.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2
12.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2
12.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2
12.3.1 Serial Boot Facility Status Register (SBFSR) . . . . . . . . . . . . . . . . . . . . . . . . . 12-3
12.3.2 Serial Boot Facility Control Register (SBFCR) . . . . . . . . . . . . . . . . . . . . . . . . 12-3
12.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4
12.4.1 Serial Initialization and Shift Clock Frequency Adjustment . . . . . . . . . . . . . . . 12-4
12.4.2 Reset Configuration and Optional Boot Load . . . . . . . . . . . . . . . . . . . . . . . . . 12-5
12.4.3 Execution Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6
12.5 Initialization Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6
12.5.1 SPI Memory Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6
12.5.2 FAST_READ Feature Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7
Chapter 13
Reset Controller Module
13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1
13.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1
13.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1
13.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2
13.2.1 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2
13.2.2 RSTOUT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2
13.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2
13.3.1 Reset Control Register (RCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2
13.3.2 Reset Status Register (RSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3
13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
13.4.1 Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
13.4.2 Reset Control Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5
13.4.3 Concurrent Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7
Chapter 14
System Control Module (SCM)
14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1
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14.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1
14.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1
14.2 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1
14.2.1 Master Privilege Register (MPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2
14.2.2 Peripheral Access Control Registers (PACRx) . . . . . . . . . . . . . . . . . . . . . . . . 14-4
14.2.3 Core Watchdog Control Register (CWCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-7
14.2.4 Core Watchdog Service Register (CWSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-8
14.2.5 SCM Interrupt Status Register (SCMISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9
14.2.6 Burst Configuration Register (BCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-10
14.2.7 Core Fault Address Register (CFADR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-10
14.2.8 Core Fault Interrupt Enable Register (CFIER) . . . . . . . . . . . . . . . . . . . . . . . 14-11
14.2.9 Core Fault Location Register (CFLOC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-11
14.2.10 Core Fault Attributes Register (CFATR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-12
14.2.11 Core Fault Data Register (CFDTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-13
14.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-13
14.3.1 Access Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-13
14.3.2 Core Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-13
14.3.3 Core Data Fault Recovery Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-14
Chapter 15
Crossbar Switch (XBS)
15.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1
15.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3
15.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3
15.4 Memory Map / Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3
15.4.1 XBS Priority Registers (XBS_PRSn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4
15.4.2 XBS Control Registers (XBS_CRSn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5
15.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7
15.5.1 Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7
15.6 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8
Chapter 16
Pin Multiplexing and Control
16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1
16.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3
16.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3
16.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3
16.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-12
16.3.1 Port Output Data Registers (PODR_x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-16
16.3.2 Port Data Direction Registers (PDDR_x) . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-18
16.3.3 Port Pin Data/Set Data Registers (PPDSDR_x) . . . . . . . . . . . . . . . . . . . . . . 16-20
16.3.4 Port Clear Output Data Registers (PCLRR_x) . . . . . . . . . . . . . . . . . . . . . . . 16-23
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16.3.5 Pin Assignment Registers (PAR_x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-25
16.3.6 SDRAM Mode Select Control Register (MSCR_SDRAM) . . . . . . . . . . . . . . 16-38
16.3.7 PCI Mode Select Control Register (MSCR_PCI) . . . . . . . . . . . . . . . . . . . . . 16-39
16.3.8 Drive Strength Control Registers (DSCR_x) . . . . . . . . . . . . . . . . . . . . . . . . . 16-39
16.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-42
16.4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-42
16.4.2 Port Digital I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-42
16.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-43
Chapter 17
Interrupt Controller Modules
17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1
17.1.1 68 K/ColdFire Interrupt Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . 17-1
17.2 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2
17.2.1 Interrupt Pending Registers (IPRHn, IPRLn) . . . . . . . . . . . . . . . . . . . . . . . . . 17-4
17.2.2 Interrupt Mask Register (IMRHn, IMRLn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5
17.2.3 Interrupt Force Registers (INTFRCHn, INTFRCLn) . . . . . . . . . . . . . . . . . . . . 17-6
17.2.4 Interrupt Configuration Register (ICONFIG) . . . . . . . . . . . . . . . . . . . . . . . . . . 17-7
17.2.5 Set Interrupt Mask Register (SIMRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-8
17.2.6 Clear Interrupt Mask Register (CIMRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-9
17.2.7 Current Level Mask Register (CLMASK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-9
17.2.8 Saved Level Mask Register (SLMASK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-10
17.2.9 Interrupt Control Register (ICR0n, ICR1n, (n = 00, 01, 02, ..., 63)) . . . . . . . 17-11
17.2.10 Software and Level 1–7 IACK Registers (SWIACKn, L1IACKn–L7IACKn) . 17-15
17.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-16
17.3.1 Interrupt Controller Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-16
17.3.2 Prioritization Between Interrupt Controllers . . . . . . . . . . . . . . . . . . . . . . . . . 17-18
17.3.3 Low-Power Wake-up Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-18
17.4 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-18
17.4.1 Interrupt Service Routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-19
Chapter 18
Edge Port Module (EPORT)
18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1
18.2 Low-Power Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2
18.3 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2
18.4 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2
18.4.1 EPORT Pin Assignment Register (EPPAR) . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3
18.4.2 EPORT Data Direction Register (EPDDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-4
18.4.3 Edge Port Interrupt Enable Register (EPIER) . . . . . . . . . . . . . . . . . . . . . . . . . 18-5
18.4.4 Edge Port Data Register (EPDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-5
18.4.5 Edge Port Pin Data Register (EPPDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-5
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18.4.6 Edge Port Flag Register (EPFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-6
Chapter 19
Enhanced Direct Memory Access (eDMA)
19.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1
19.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1
19.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2
19.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2
19.2.1 Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2
19.2.2 Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3
19.3 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3
19.3.1 External Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3
19.4 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-4
19.4.1 eDMA Control Register (EDMA_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-4
19.4.2 eDMA Error Status Register (EDMA_ES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-5
19.4.3 eDMA Enable Request Register (EDMA_ERQ) . . . . . . . . . . . . . . . . . . . . . . . 19-8
19.4.4 eDMA Enable Error Interrupt Registers (EDMA_EEI) . . . . . . . . . . . . . . . . . . 19-9
19.4.5 eDMA Set Enable Request Register (EDMA_SERQ) . . . . . . . . . . . . . . . . . 19-10
19.4.6 eDMA Clear Enable Request Register (EDMA_CERQ) . . . . . . . . . . . . . . . . 19-10
19.4.7 eDMA Set Enable Error Interrupt Register (EDMA_SEEI) . . . . . . . . . . . . . . 19-11
19.4.8 eDMA Clear Enable Error Interrupt Register (EDMA_CEEI) . . . . . . . . . . . . 19-11
19.4.9 eDMA Clear Interrupt Request Register (EDMA_CINT) . . . . . . . . . . . . . . . . 19-12
19.4.10 eDMA Clear Error Register (EDMA_CERR) . . . . . . . . . . . . . . . . . . . . . . . . . 19-13
19.4.11 eDMA Set START Bit Register (EDMA_SSRT) . . . . . . . . . . . . . . . . . . . . . . 19-13
19.4.12 eDMA Clear DONE Status Bit Register (EDMA_CDNE) . . . . . . . . . . . . . . . 19-14
19.4.13 eDMA Interrupt Request Register (EDMA_INT) . . . . . . . . . . . . . . . . . . . . . . 19-15
19.4.14 eDMA Error Register (EDMA_ERR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-15
19.4.15 eDMA Channel n Priority Registers (DCHPRIn) . . . . . . . . . . . . . . . . . . . . . . 19-16
19.4.16 Transfer Control Descriptors (TCDn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-17
19.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-24
19.5.1 eDMA Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-24
19.5.2 eDMA Basic Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-25
19.6 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-28
19.6.1 eDMA Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-28
19.6.2 DMA Programming Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-31
19.6.3 DMA Arbitration Mode Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-31
19.6.4 DMA Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-32
19.6.5 eDMA TCDn Status Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-35
19.6.6 Channel Linking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-36
19.6.7 Dynamic Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-37
Chapter 20
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FlexBus
20.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1
20.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1
20.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1
20.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-2
20.2 External Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-2
20.2.1 Address and Data Buses (FB_An, FB_Dn, FB_ADn) . . . . . . . . . . . . . . . . . . . 20-3
20.2.2 Chip Selects (FB_CS[5:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-3
20.2.3 Byte Enables/Byte Write Enables (FB_BE/BWE[3:0]) . . . . . . . . . . . . . . . . . . 20-3
20.2.4 Output Enable (FB_OE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-3
20.2.5 Read/Write (FB_R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-4
20.2.6 Address Latch Enable (FB_ALE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-4
20.2.7 Transfer Size (FB_TSIZ[1:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-4
20.2.8 Transfer Burst (FB_TBST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-5
20.2.9 Transfer Acknowledge (FB_TA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-5
20.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-5
20.3.1 Chip-Select Address Registers (CSAR0 – CSAR5) . . . . . . . . . . . . . . . . . . . . 20-6
20.3.2 Chip-Select Mask Registers (CSMR0 – CSMR5) . . . . . . . . . . . . . . . . . . . . . . 20-7
20.3.3 Chip-Select Control Registers (CSCR0 – CSCR5) . . . . . . . . . . . . . . . . . . . . . 20-7
20.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-10
20.4.1 Chip-Select Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-10
20.4.2 Data Transfer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-11
20.4.3 Data Byte Alignment and Physical Connections . . . . . . . . . . . . . . . . . . . . . . 20-12
20.4.4 Address/Data Bus Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-12
20.4.5 Bus Cycle Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-13
20.4.6 FlexBus Timing Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-14
20.4.7 Burst Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-26
20.4.8 Misaligned Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-34
20.4.9 Bus Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-34
Chapter 21
SDRAM Controller (SDRAMC)
21.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1
21.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-2
21.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-2
21.1.3 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3
21.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3
21.3 Interface Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-5
21.3.1 Supported Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-5
21.3.2 SDRAM DDR Component Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-8
21.3.3 DDR SDRAM Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-8
21.4 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-9
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21.4.1 SDRAM Mode/Extended Mode Register (SDMR) . . . . . . . . . . . . . . . . . . . . 21-10
21.4.2 SDRAM Control Register (SDCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-11
21.4.3 SDRAM Configuration Register 1 (SDCFG1) . . . . . . . . . . . . . . . . . . . . . . . . 21-12
21.4.4 SDRAM Configuration Register 2 (SDCFG2) . . . . . . . . . . . . . . . . . . . . . . . . 21-15
21.4.5 SDRAM Chip Select Configuration Registers (SDCSn) . . . . . . . . . . . . . . . . 21-16
21.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-17
21.5.1 SDRAM Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-17
21.5.2 Read Clock Recovery (RCR) Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-26
21.6 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-27
21.6.1 DDR SDRAM Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-27
21.6.2 Low-power/Mobile SDRAM Initialization Sequence . . . . . . . . . . . . . . . . . . . 21-28
21.6.3 DDR2 SDRAM Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-28
21.6.4 Page Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-29
21.6.5 Transfer Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-30
Chapter 22
PCI Bus Controller
22.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1
22.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1
22.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1
22.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2
22.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2
22.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-3
22.2.1 Address/Data Bus (PCI_AD[31:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-3
22.2.2 Clock (PCI_CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-3
22.2.3 Command/Byte Enables (PCI_CBE[3:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-3
22.2.4 Device Select (PCI_DEVSEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-4
22.2.5 Frame (PCI_FRAME) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-4
22.2.6 Grant (PCI_GNT
[3:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-4
22.2.7 Initialization Device Select (PCI_IDSEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-4
22.2.8 Interrupt (PCI_INTA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-4
22.2.9 Initiator Ready (PCI_IRDY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-4
22.2.10 Parity (PCI_PAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-4
22.2.11 Parity Error (PCI_PERR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-4
22.2.12 Request (PCI_REQ[3:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-4
22.2.13 Reset (PCI_RST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-5
22.2.14 System Error (PCI_SERR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-5
22.2.15 Stop (PCI_STOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-5
22.2.16 Target Ready (PCI_TRDY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-5
22.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-5
22.3.1 PCI Type 0 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-7
22.3.2 General Control/Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-14
Freescale Semiconductor xv
22.3.3 PCI Arbiter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-25
22.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-27
22.4.1 PCI Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-28
22.4.2 Configuration Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-35
22.4.3 Internal Bus Initiator Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-36
22.4.4 Internal Bus Target Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-42
22.4.5 PCI Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-46
22.4.6 PCI Clock Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-52
22.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-53
22.4.8 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-53
22.5 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-53
22.5.1 Internal Bus-Initiated Transaction Mapping . . . . . . . . . . . . . . . . . . . . . . . . . 22-53
22.5.2 Address Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-54
Chapter 23
Advanced Technology Attachment (ATA)
23.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-1
23.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-1
23.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-2
23.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-2
23.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-3
23.2.1 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-4
23.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-5
23.3.1 Endianness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-6
23.3.2 Timing Registers (TIME_x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-7
23.3.3 FIFO Data Register (FIFO_DATA_n) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-7
23.3.4 FIFO_FILL Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-8
23.3.5 ATA Control Register (ATA_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-8
23.3.6 Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-9
23.3.7 FIFO Alarm Register (FIFO_ALARM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-12
23.3.8 Drive Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-12
23.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-13
23.4.1 Timing on ATA Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-13
23.4.2 Resetting ATA Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-21
23.4.3 Programming ATA Bus Timing and IORDYEN . . . . . . . . . . . . . . . . . . . . . . . 23-21
23.4.4 Access to ATA Bus in PIO Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-21
23.4.5 Using DMA Mode to Receive Data from ATA Bus . . . . . . . . . . . . . . . . . . . . 23-21
23.4.6 Using DMA Mode to Transmit Data to ATA Bus . . . . . . . . . . . . . . . . . . . . . . 23-23
Chapter 24
Cryptographic Acceleration Unit (CAU)
24.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-2
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Freescale Semiconductor MCF54455 Reference guide
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- Reference guide
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