MCF5373 Reference Manual
Devices Supported:
MCF5372
MCF5372L
MCF53721
MCF5373
MCF5373L
Document Number: MCF5373RM
Rev. 3
12/2008
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MCF5373RM
Rev. 3
12/2008
Register Memory Map Quick Reference
A
Overview
Signal Descriptions
ColdFire Core
Enhanced Multiply-Accumulate Unit (EMAC)
Cache
Static RAM (SRAM)
Clock Module
Power Management
Chip Configuration Module (CCM)
Reset Controller Module
System Control Module (SCM)
Crossbar Switch (XBS)
General Purpose I/O Module
Interrupt Controller Modules
Edge Port Module (EPORT)
Enhanced Direct Memory Access (eDMA)
FlexBus
SDRAM Controller (SDRAMC)
Fast Ethernet Controller (FEC)
Universal Serial Bus Interface – Host Module
Universal Serial Bus Interface – On-The-Go Module
FlexCAN
Synchronous Serial Interface (SSI)
Real-Time Clock
Pulse-Width Modulation (PWM) Module
Watchdog Timer Module
Programmable Interrupt Timers (PIT0–PIT3)
Queued Serial Peripheral Interface (QSPI)
UART Modules
I2C Interface
Message Digest Hardware Accelerator (MDHA)
DMA Timers (DTIM0–DTIM3)
1
2
3
4
5
6
7
8
9
10
11
12
13
13
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
Random Number Generator (RNG)
Debug Module
IEEE 1149.1 Test Access Port (JTAG)
Revision History
Symmetric Key Hardware Accelerator (SKHA)
36
B
Register Memory Map Quick Reference
A
Overview
Signal Descriptions
ColdFire Core
Enhanced Multiply-Accumulate Unit (EMAC)
Cache
Static RAM (SRAM)
Clock Module
Power Management
Chip Configuration Module (CCM)
Reset Controller Module
System Control Module (SCM)
Crossbar Switch (XBS)
General Purpose I/O Module
Interrupt Controller Modules
Edge Port Module (EPORT)
Enhanced Direct Memory Access (eDMA)
FlexBus
SDRAM Controller (SDRAMC)
Fast Ethernet Controller (FEC)
Universal Serial Bus Interface – Host Module
Universal Serial Bus Interface – On-The-Go Module
FlexCAN
Synchronous Serial Interface (SSI)
Real-Time Clock
Pulse-Width Modulation (PWM) Module
Watchdog Timer Module
Programmable Interrupt Timers (PIT0–PIT3)
Queued Serial Peripheral Interface (QSPI)
UART Modules
I2C Interface
Message Digest Hardware Accelerator (MDHA)
DMA Timers (DTIM0–DTIM3)
1
2
3
4
5
6
7
8
9
10
11
12
13
13
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
Random Number Generator (RNG)
Debug Module
IEEE 1149.1 Test Access Port (JTAG)
Revision History
Symmetric Key Hardware Accelerator (SKHA)
36
B
Freescale Semiconductor v
About This Book
Audience ...................................................................................................................... xxv
Organization ................................................................................................................ xxv
Suggested Reading ...................................................................................................xxviii
Hardware Specification ...................................................................................xxviii
General Information ..........................................................................................xxix
ColdFire Documentation ...................................................................................xxix
Conventions .................................................................................................................xxix
Register Figure Conventions ............................................................................ xxx
Acronyms and Abbreviations .......................................................................................xxxi
Terminology Conventions ..........................................................................................xxxiii
Chapter 1
Overview
1.1 MCF537x Device Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1.3.1 V3 Core Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
1.3.2 Debug Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
1.3.3 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
1.3.4 On-chip Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
1.3.5 Voice-over-IP (VoIP) System Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
1.3.6 SDR/DDR SDRAM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
1.3.7 USB Host and OTG Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
1.3.8 Synchronous Serial Interface (SSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
1.3.9 Fast Ethernet Controller (FEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
1.3.10 Cryptography Accelerators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
1.3.11 FlexCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
1.3.12 UARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
1.3.13 I
2
C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
1.3.14 QSPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
1.3.15 Pulse Width Modulation (PWM) Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
1.3.16 Real Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
1.3.17 DMA Timers (DTIM0-DTIM3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
1.3.18 Software Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
1.3.19 Periodic Interrupt Timers (PIT0–PIT3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
1.3.20 Clock Module and Phase Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
1.3.21 Interrupt Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
1.3.22 DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
1.3.23 FlexBus External Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
1.3.24 Reset Controller Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15
1.3.25 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15
1.4 Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15
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Chapter 2
Signal Descriptions
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.2 Signal Properties Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.2.1 Internal Pull-up/Pull-downs Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.3 Signal Primary Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.3.1 Reset Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.3.2 PLL and Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2.3.3 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2.3.4 FlexBus Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.3.5 SDRAM Controller Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.3.6 External Interrupt Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.3.7 DMA Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.3.8 Ethernet Module (FEC) Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
2.3.9 I2C I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
2.3.10 FlexCAN Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
2.3.11 Queued Serial Peripheral Interface (QSPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
2.3.12 Synchronous Serial Interface (SSI) Signals . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2.3.13 Universal Serial Bus (USB) Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2.3.14 Pulse Width Modulation (PWM) Module Signals . . . . . . . . . . . . . . . . . . . . . . 2-14
2.3.15 UART Module Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2.3.16 DMA Timer Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2.3.17 Debug Support Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
2.3.18 Test Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
2.3.19 Power and Ground Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
2.4 External Boot Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
Chapter 3
ColdFire Core
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.2 Memory Map/Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3.2.1 Data Registers (D0–D7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
3.2.2 Address Registers (A0–A6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
3.2.3 Supervisor/User Stack Pointers (A7 and OTHER_A7) . . . . . . . . . . . . . . . . . . . 3-6
3.2.4 Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
3.2.5 Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
3.2.6 Cache Control Register (CACR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
3.2.7 Access Control Registers (ACRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3.2.8 Vector Base Register (VBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3.2.9 Status Register (SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3.2.10 Memory Base Address Register (RAMBAR) . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
3.3.1 Version 3 ColdFire Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
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3.3.2 Instruction Set Architecture (ISA_A+) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
3.3.3 Exception Processing Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
3.3.4 Processor Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
3.3.5 Instruction Execution Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23
Chapter 4
Enhanced Multiply-Accumulate Unit (EMAC)
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.2 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
4.2.1 MAC Status Register (MACSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
4.2.2 Mask Register (MASK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
4.2.3 Accumulator Registers (ACC0–3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
4.2.4 Accumulator Extension Registers (ACCext01, ACCext23) . . . . . . . . . . . . . . . . 4-7
4.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
4.3.1 Fractional Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
4.3.2 EMAC Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
4.3.3 EMAC Instruction Execution Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13
4.3.4 Data Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14
4.3.5 MAC Opcodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14
Chapter 5
Cache
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5.2 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.2.1 Cache Control Register (CACR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.2.2 Access Control Registers (ACR0–ACR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
5.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
5.3.1 Cache Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
5.3.2 Cache Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
5.3.3 Caching Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
5.3.4 Cache-Inhibited Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
5.3.5 Cache Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
5.3.6 Cache Coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
5.3.7 Memory Accesses for Cache Maintenance . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
5.3.8 Cache Locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
5.3.9 Cache Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16
5.3.10 Cache Operation Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17
Chapter 6
Static RAM (SRAM)
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
6.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
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6.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
6.2 Memory Map/Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
6.2.1 SRAM Base Address Register (RAMBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
6.3 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
6.3.1 SRAM Initialization Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
6.3.2 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
Chapter 7
Clock Module
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
7.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
7.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
7.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
7.2 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
7.2.1 PLL Output Divider Register (PODR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6
7.2.2 PLL Control Register (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6
7.2.3 PLL Modulation Divider Register (PMDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7
7.2.4 PLL Feedback Divider Register (PFDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8
7.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8
7.3.1 PLL Dithered and Non-Dithered Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8
7.3.2 Dithering Waveform Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
7.3.3 PLL Frequency Multiplication Factor Select . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
7.3.4 System Clock Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11
7.3.5 Clock Operation During Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11
Chapter 8
Power Management
8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
8.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
8.2 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
8.2.1 Wake-up Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
8.2.2 Peripheral Power Management Set Registers (PPMSR0 & PPMSR1) . . . . . . . 8-3
8.2.3 Peripheral Power Management Clear Registers (PPMCR0 & PPMCR1) . . . . . 8-4
8.2.4 Peripheral Power Management Registers (PPMHR0, PPMHR1, & PPMLR0) . 8-4
8.2.5 Low-Power Control Register (LPCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7
8.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8
8.3.1 Peripheral Shut Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8
8.3.2 Limp mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8
8.3.3 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9
8.3.4 Peripheral Behavior in Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10
8.3.5 Summary of Peripheral State During Low-power Modes . . . . . . . . . . . . . . . . 8-15
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Chapter 9
Chip Configuration Module (CCM)
9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
9.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
9.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
9.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
9.2 External Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
9.2.1 RCON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
9.2.2 D[9:86:1] (Reset Configuration Override) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
9.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
9.3.1 Chip Configuration Register (CCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
9.3.2 Reset Configuration Register (RCON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4
9.3.3 Chip Identification Register (CIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4
9.3.4 Miscellaneous Control Register (MISCCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5
9.3.5 Clock Divider Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6
9.3.6 USB Host Controller Status Register (UHCSR) . . . . . . . . . . . . . . . . . . . . . . . . 9-7
9.3.7 USB On-the-Go Controller Status Register (UOCSR) . . . . . . . . . . . . . . . . . . . 9-7
9.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9
9.4.1 Reset Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9
9.4.2 PLL Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10
9.4.3 Oscillator Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11
9.4.4 Boot Device Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11
9.4.5 Output Pad Strength Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11
9.4.6 Chip Select Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11
Chapter 10
Reset Controller Module
10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
10.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
10.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
10.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
10.2.1 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
10.2.2 RSTOUT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
10.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
10.3.1 Reset Control Register (RCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
10.3.2 Reset Status Register (RSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
10.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
10.4.1 Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
10.4.2 Reset Control Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
10.4.3 Concurrent Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7
Chapter 11
System Control Module (SCM)
11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
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11.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
11.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
11.2 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
11.2.1 Master Privilege Register 0 (MPR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
11.2.2 Master Privilege Register 1 (MPR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4
11.2.3 Peripheral Access Control Registers (PACRx) . . . . . . . . . . . . . . . . . . . . . . . . 11-4
11.2.4 Bus Monitor Timeout Registers (BMTn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7
11.2.5 Core Watchdog Control Register (CWCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8
11.2.6 Core Watchdog Service Register (CWSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9
11.2.7 SCM Interrupt Status Register (SCMISR) . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10
11.2.8 Burst Configuration Register (BCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10
11.2.9 Core Fault Address Register (CFADR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11
11.2.10Core Fault Interrupt Enable Register (CFIER) . . . . . . . . . . . . . . . . . . . . . . . 11-12
11.2.11Core Fault Location Register (CFLOC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12
11.2.12Core Fault Attributes Register (CFATR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12
11.2.13Core Fault Data Register (CFDTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13
11.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14
11.3.1 Access Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14
11.3.2 Core Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14
11.3.3 Core Data Fault Recovery Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-15
Chapter 12
Crossbar Switch (XBS)
12.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
12.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3
12.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3
12.4 Memory Map / Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3
12.4.1 XBS Priority Registers (XBS_PRSn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4
12.4.2 XBS Control Registers (XBS_CRSn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5
12.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6
12.5.1 Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6
12.6 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7
Chapter 13
General Purpose I/O Module
13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1
13.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2
13.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3
13.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3
13.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10
13.3.1 Port Output Data Registers (PODR_x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-12
13.3.2 Port Data Direction Registers (PDDR_x) . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-14
13.3.3 Port Pin Data/Set Data Registers (PPDSDR_x) . . . . . . . . . . . . . . . . . . . . . . 13-15
13.3.4 Port Clear Output Data Registers (PCLRR_x) . . . . . . . . . . . . . . . . . . . . . . . 13-17
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13.3.5 Pin Assignment Registers (PAR_x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-19
13.3.6 FlexBus Mode Select Control Register (MSCR_FLEXBUS) . . . . . . . . . . . . . 13-26
13.3.7 SDRAM Mode Select Control Register (MSCR_SDRAM) . . . . . . . . . . . . . . 13-27
13.3.8 Drive Strength Control Registers (DSCR_x) . . . . . . . . . . . . . . . . . . . . . . . . . 13-28
13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-30
13.4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-30
13.4.2 Port Digital I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-30
13.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-31
Chapter 14
Interrupt Controller Modules
14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1
14.1.1 68 K/ColdFire Interrupt Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . 14-1
14.2 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2
14.2.1 Interrupt Pending Registers (IPRHn, IPRLn) . . . . . . . . . . . . . . . . . . . . . . . . . 14-4
14.2.2 Interrupt Mask Register (IMRHn, IMRLn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5
14.2.3 Interrupt Force Registers (INTFRCHn, INTFRCLn) . . . . . . . . . . . . . . . . . . . . 14-6
14.2.4 Interrupt Configuration Register (ICONFIG) . . . . . . . . . . . . . . . . . . . . . . . . . . 14-7
14.2.5 Set Interrupt Mask Register (SIMRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-8
14.2.6 Clear Interrupt Mask Register (CIMRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9
14.2.7 Current Level Mask Register (CLMASK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9
14.2.8 Saved Level Mask Register (SLMASK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-10
14.2.9 Interrupt Control Register (ICR0n, ICR1n, (n = 00, 01, 02, ..., 63)) . . . . . . . 14-11
14.2.10Software and Level 1 – 7 IACK Registers (SWIACKn, L1IACKn – L7IACKn) . 14-
14
14.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-15
14.3.1 Interrupt Controller Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-15
14.3.2 Prioritization Between Interrupt Controllers . . . . . . . . . . . . . . . . . . . . . . . . . 14-17
14.3.3 Low-Power Wake-up Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-17
14.4 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-18
14.4.1 Interrupt Service Routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-18
Chapter 15
Edge Port Module (EPORT)
15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1
15.2 Low-Power Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2
15.3 Interrupt/GPIO Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2
15.4 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2
15.4.1 EPORT Pin Assignment Register (EPPAR) . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3
15.4.2 EPORT Data Direction Register (EPDDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4
15.4.3 Edge Port Interrupt Enable Register (EPIER) . . . . . . . . . . . . . . . . . . . . . . . . . 15-5
15.4.4 Edge Port Data Register (EPDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5
15.4.5 Edge Port Pin Data Register (EPPDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5
15.4.6 Edge Port Flag Register (EPFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6
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Chapter 16
Enhanced Direct Memory Access (eDMA)
16.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1
16.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1
16.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2
16.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2
16.4.1 Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2
16.4.2 Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3
16.5 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3
16.5.1 External Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3
16.6 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4
16.6.1 eDMA Control Register (EDMA_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4
16.6.2 eDMA Error Status Register (EDMA_ES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5
16.6.3 eDMA Enable Request Register (EDMA_ERQ) . . . . . . . . . . . . . . . . . . . . . . . 16-8
16.6.4 eDMA Enable Error Interrupt Registers (EDMA_EEI) . . . . . . . . . . . . . . . . . . 16-9
16.6.5 eDMA Set Enable Request Register (EDMA_SERQ) . . . . . . . . . . . . . . . . . . 16-9
16.6.6 eDMA Clear Enable Request Register (EDMA_CERQ) . . . . . . . . . . . . . . . . 16-10
16.6.7 eDMA Set Enable Error Interrupt Register (EDMA_SEEI) . . . . . . . . . . . . . . 16-11
16.6.8 eDMA Clear Enable Error Interrupt Register (EDMA_CEEI) . . . . . . . . . . . . 16-11
16.6.9 eDMA Clear Interrupt Request Register (EDMA_CINT) . . . . . . . . . . . . . . . . 16-12
16.6.10eDMA Clear Error Register (EDMA_CERR) . . . . . . . . . . . . . . . . . . . . . . . . 16-13
16.6.11eDMA Set START Bit Register (EDMA_SSRT) . . . . . . . . . . . . . . . . . . . . . . 16-13
16.6.12eDMA Clear DONE Status Bit Register (EDMA_CDNE) . . . . . . . . . . . . . . . 16-14
16.6.13eDMA Interrupt Request Register (EDMA_INT) . . . . . . . . . . . . . . . . . . . . . 16-15
16.6.14eDMA Error Register (EDMA_ERR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-15
16.6.15eDMA Channel n Priority Registers (DCHPRIn) . . . . . . . . . . . . . . . . . . . . . 16-16
16.6.16Transfer Control Descriptors (TCDn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-17
16.7 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-24
16.7.1 eDMA Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-24
16.7.2 eDMA Basic Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-25
16.8 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-28
16.8.1 eDMA Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-28
16.8.2 DMA Programming Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-31
16.8.3 DMA Arbitration Mode Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-31
16.8.4 DMA Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-32
16.8.5 eDMA TCDn Status Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-35
16.8.6 Channel Linking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-36
16.8.7 Dynamic Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-37
Chapter 17
FlexBus
17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1
17.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1
17.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2
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17.2 External Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2
17.2.1 Address and Data Buses (FB_A[23:0], FB_D[31:0]) . . . . . . . . . . . . . . . . . . . 17-2
17.2.2 Chip Selects (FB_CS[5:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3
17.2.3 Byte Enables/Byte Write Enables (FB_BE/BWE[3:0]) . . . . . . . . . . . . . . . . . . 17-3
17.2.4 Output Enable (FB_OE
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3
17.2.5 Read/Write (FB_R/
W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3
17.2.6 Transfer Start (FB_TS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3
17.2.7 Transfer Acknowledge (FB_TA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3
17.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4
17.3.1 Chip-Select Address Registers (CSAR0 – CSAR5) . . . . . . . . . . . . . . . . . . . . 17-4
17.3.2 Chip-Select Mask Registers (CSMR0 – CSMR5) . . . . . . . . . . . . . . . . . . . . . . 17-5
17.3.3 Chip-Select Control Registers (CSCR0 – CSCR5) . . . . . . . . . . . . . . . . . . . . . 17-6
17.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-9
17.4.1 Chip-Select Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-9
17.4.2 Data Transfer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-10
17.4.3 Data Byte Alignment and Physical Connections . . . . . . . . . . . . . . . . . . . . . . 17-11
17.4.4 Bus Cycle Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-12
17.4.5 FlexBus Timing Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-13
17.4.6 Burst Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-24
17.4.7 Misaligned Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-30
17.4.8 Bus Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-30
Chapter 18
SDRAM Controller (SDRAMC)
18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1
18.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2
18.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2
18.1.3 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3
18.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3
18.3 Interface Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-5
18.3.1 Supported Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-5
18.3.2 SDRAM SDR Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-10
18.3.3 SDRAM DDR Component Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-12
18.3.4 DDR SDRAM Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-12
18.4 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-14
18.4.1 SDRAM Mode/Extended Mode Register (SDMR) . . . . . . . . . . . . . . . . . . . . 18-14
18.4.2 SDRAM Control Register (SDCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-15
18.4.3 SDRAM Configuration Register 1 (SDCFG1) . . . . . . . . . . . . . . . . . . . . . . . . 18-17
18.4.4 SDRAM Configuration Register 2 (SDCFG2) . . . . . . . . . . . . . . . . . . . . . . . . 18-19
18.4.5 SDRAM Chip Select Configuration Registers (SDCSn) . . . . . . . . . . . . . . . . 18-20
18.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-21
18.5.1 SDRAM Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-21
18.5.2 Read Clock Recovery (RCR) Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-26
18.6 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-27
18.6.1 Page Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-28
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18.6.2 Transfer Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-29
Chapter 19
Fast Ethernet Controller (FEC)
19.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1
19.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1
19.1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1
19.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3
19.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-4
19.2.1 Full and Half Duplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-4
19.2.2 Interface Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-4
19.2.3 Address Recognition Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-5
19.2.4 Internal Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-5
19.3 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-5
19.4 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-6
19.4.1 MIB Block Counters Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-7
19.4.2 Ethernet Interrupt Event Register (EIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-9
19.4.3 Interrupt Mask Register (EIMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-11
19.4.4 Receive Descriptor Active Register (RDAR) . . . . . . . . . . . . . . . . . . . . . . . . . 19-11
19.4.5 Transmit Descriptor Active Register (TDAR) . . . . . . . . . . . . . . . . . . . . . . . . . 19-12
19.4.6 Ethernet Control Register (ECR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-13
19.4.7 MII Management Frame Register (MMFR) . . . . . . . . . . . . . . . . . . . . . . . . . . 19-13
19.4.8 MII Speed Control Register (MSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-15
19.4.9 MIB Control Register (MIBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-16
19.4.10Receive Control Register (RCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-16
19.4.11Transmit Control Register (TCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-17
19.4.12Physical Address Lower Register (PALR) . . . . . . . . . . . . . . . . . . . . . . . . . . 19-18
19.4.13Physical Address Upper Register (PAUR) . . . . . . . . . . . . . . . . . . . . . . . . . . 19-19
19.4.14Opcode/Pause Duration Register (OPD) . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-19
19.4.15Descriptor Individual Upper Address Register (IAUR) . . . . . . . . . . . . . . . . . 19-20
19.4.16Descriptor Individual Lower Address Register (IALR) . . . . . . . . . . . . . . . . . 19-20
19.4.17Descr
iptor Group Upper Address Register (GAUR) . . . . . . . . . . . . . . . . . . 19-21
19.4.18Descriptor Group Lower Address Register (GALR) . . . . . . . . . . . . . . . . . . . 19-21
19.4.19Transmit FIFO Watermark Register (TFWR) . . . . . . . . . . . . . . . . . . . . . . . . 19-21
19.4.20FIFO Receive Bound Register (FRBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-22
19.4.21FIFO Receive Start Register (FRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-22
19.4.22Receive Descriptor Ring Start Register (ERDSR) . . . . . . . . . . . . . . . . . . . . 19-23
19.4.23Transmit Buffer Descriptor Ring Start Registers (ETSDR) . . . . . . . . . . . . . 19-23
19.4.24Receive Buffer Size Register (EMRBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-24
19.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-25
19.5.1 Buffer Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-25
19.5.2 Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-30
19.5.3 User Initialization (Prior to Setting ECR[ETHER_EN]) . . . . . . . . . . . . . . . . . 19-30
19.5.4 Microcontroller Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-31
19.5.5 User Initialization (After Setting ECR[ETHER_EN]) . . . . . . . . . . . . . . . . . . . 19-32
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19.5.6 Network Interface Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-32
19.5.7 FEC Frame Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-33
19.5.8 FEC Frame Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-34
19.5.9 Ethernet Address Recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-35
19.5.10Hash Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-37
19.5.11Full Duplex Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-40
19.5.12Inter-Packet Gap (IPG) Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-41
19.5.13Collision Managing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-41
19.5.14MII Internal and External Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-41
19.5.15Ethernet Error-Managing Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-41
Chapter 20
Universal Serial Bus Interface – Host Module
20.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1
20.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-2
20.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-2
20.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-2
20.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-3
20.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-3
20.2.1 USB Host Control and Status Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-4
20.3 Memory Map/Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-5
20.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-6
Chapter 21
Universal Serial Bus Interface – On-The-Go Module
21.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1
21.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1
21.1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-2
21.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-2
21.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3
21.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-4
21.2.1 USB OTG Control and Status Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-4
21.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-6
21.3.1 Module Identification Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-7
21.3.2 Capability Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-11
21.3.3 Operational Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-14
21.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-42
21.4.1 System Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-42
21.4.2 DMA Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-42
21.4.3 FIFO RAM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-42
21.4.4 Physical Layer (PHY) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-42
21.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-43
21.5.1 Host Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-43
21.5.2 Device Data Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-44
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21.5.3 Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-51
21.5.4 Servicing Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-69
21.5.5 Deviations from the EHCI Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-70
Chapter 22
FlexCAN
22.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1
22.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1
22.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-3
22.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-3
22.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-5
22.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-5
22.3.1 FlexCAN Configuration Register (CANMCR) . . . . . . . . . . . . . . . . . . . . . . . . . 22-6
22.3.2 FlexCAN Control Register (CANCTRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-8
22.3.3 FlexCAN Free Running Timer Register (TIMER) . . . . . . . . . . . . . . . . . . . . . 22-10
22.3.4 Rx Mask Registers (RXGMASK, RX14MASK, RX15MASK) . . . . . . . . . . . . 22-11
22.3.5 FlexCAN Error Counter Register (ERRCNT) . . . . . . . . . . . . . . . . . . . . . . . . 22-12
22.3.6 FlexCAN Error and Status Register (ERRSTAT) . . . . . . . . . . . . . . . . . . . . . . 22-13
22.3.7 Interrupt Mask Register (IMASK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-15
22.3.8 Interrupt Flag Register (IFLAG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-16
22.3.9 Message Buffer Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-16
22.3.10Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-20
22.3.11Transmit Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-20
22.3.12Arbitration Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-21
22.3.13Receive Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-21
22.3.14Matching Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-23
22.3.15Message Buffer Managing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-23
22.3.16CAN Protocol Related Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-25
22.3.17Time Stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-26
22.3.18Bit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-26
22.4 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-28
22.4.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-29
Chapter 23
Synchronous Serial Interface (SSI)
23.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-1
23.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-2
23.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-3
23.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-3
23.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-5
23.2.1 SSI_CLKIN — SSI Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-5
23.2.2 SSI_BCLK — Serial Bit Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-5
23.2.3 SSI_MCLK — Serial Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-5
23.2.4 SSI_FS — Serial Frame Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-5
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23.2.5 SSI_RXD — Serial Receive Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-5
23.2.6 SSI_TXD — Serial Transmit Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-6
23.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-7
23.3.1 SSI Transmit Data Registers 0 and 1 (SSI_TX0/1) . . . . . . . . . . . . . . . . . . . . 23-8
23.3.2 SSI Transmit FIFO 0 and 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-9
23.3.3 SSI Transmit Shift Register (TXSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-9
23.3.4 SSI Receive Data Registers 0 and 1 (SSI_RX0/1) . . . . . . . . . . . . . . . . . . . 23-10
23.3.5 SSI Receive FIFO 0 and 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-11
23.3.6 SSI Receive Shift Register (RXSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-11
23.3.7 SSI Control Register (SSI_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-13
23.3.8 SSI Interrupt Status Register (SSI_ISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-15
23.3.9 SSI Interrupt Enable Register (SSI_IER) . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-20
23.3.10SSI Transmit Configuration Register (SSI_TCR) . . . . . . . . . . . . . . . . . . . . . 23-21
23.3.11SSI Receive Configuration Register (SSI_RCR) . . . . . . . . . . . . . . . . . . . . . 23-23
23.3.12SSI Clock Control Register (SSI_CCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-24
23.3.13SSI FIFO Control/Status Register (SSI_FCSR) . . . . . . . . . . . . . . . . . . . . . 23-25
23.3.14SSI AC97 Control Register (SSI_ACR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-27
23.3.15SSI AC97 Command Address Register (SSI_ACADD) . . . . . . . . . . . . . . . . 23-28
23.3.16SSI AC97 Command Data Register (SSI_ACDAT) . . . . . . . . . . . . . . . . . . . 23-29
23.3.17SSI AC97 Tag Register (SSI_ATAG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-29
23.3.18SSI Transmit Time Slot Mask Register (SSI_TMASK) . . . . . . . . . . . . . . . . 23-30
23.3.19SSI Receive Time Slot Mask Register (SSI_RMASK) . . . . . . . . . . . . . . . . . 23-30
23.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-30
23.4.1 Detailed Operating Mode Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-30
23.4.2 SSI Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-43
23.4.3 External Frame and Clock Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-46
23.4.4 Supported Data Alignment Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-46
23.4.5 Receive Interrupt Enable Bit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-48
23.4.6 Transmit Interrupt Enable Bit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-48
23.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-49
Chapter 24
Real-Time Clock
24.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-1
24.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-1
24.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-2
24.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-2
24.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-3
24.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-3
24.3.1 RTC Hours and Minutes Counter Register (RTC_HOURMIN) . . . . . . . . . . . . 24-3
24.3.2 RTC Seconds Counter Register (RTC_SECONDS) . . . . . . . . . . . . . . . . . . . . 24-4
24.3.3 RTC Hours and Minutes Alarm Register (RTC_ALRM_HM) . . . . . . . . . . . . . 24-4
24.3.4 RTC Seconds Alarm Register (RTC_ALRM_SEC) . . . . . . . . . . . . . . . . . . . . 24-5
24.3.5 RTC Control Register (RTC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-5
24.3.6 RTC Interrupt Status Register (RTC_ISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-6
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24.3.7 RTC Interrupt Enable Register (RTC_IER) . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-7
24.3.8 RTC Stopwatch Minutes Register (RTC_STPWCH) . . . . . . . . . . . . . . . . . . . 24-8
24.3.9 RTC Days Counter Register (RTC_DAYS) . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-9
24.3.10RTC Day Alarm Register (RTC_ALRM_DAY) . . . . . . . . . . . . . . . . . . . . . . . . 24-9
24.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-10
24.4.1 Prescaler and Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-10
24.4.2 Alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-10
24.4.3 Sampling Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-11
24.4.4 Minute Stopwatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-11
24.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-12
24.5.1 Flow Chart of RTC Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-12
24.5.2 Programming the Alarm or Time-of-Day Registers . . . . . . . . . . . . . . . . . . . . 24-12
Chapter 25
Pulse-Width Modulation (PWM) Module
25.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-1
25.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-1
25.2 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-2
25.2.1 PWM Enable Register (PWME) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-3
25.2.2 PWM Polarity Register (PWMPOL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-4
25.2.3 PWM Clock Select Register (PWMCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-4
25.2.4 PWM Prescale Clock Select Register (PWMPRCLK) . . . . . . . . . . . . . . . . . . 25-5
25.2.5 PWM Center Align Enable Register (PWMCAE) . . . . . . . . . . . . . . . . . . . . . . 25-6
25.2.6 PWM Control Register (PWMCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-6
25.2.7 PWM Scale A Register (PWMSCLA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-7
25.2.8 PWM Scale B Register (PWMSCLB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-8
25.2.9 PWM Channel Counter Registers (PWMCNTn) . . . . . . . . . . . . . . . . . . . . . . . 25-9
25.2.10PWM Channel Period Registers (PWMPERn) . . . . . . . . . . . . . . . . . . . . . . 25-10
25.2.11PWM Channel Duty Registers (PWMDTYn) . . . . . . . . . . . . . . . . . . . . . . . . 25-10
25.2.12PWM Shutdown Register (PWMSDN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-11
25.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-12
25.3.1 PWM Clock Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-12
25.3.2 PWM Channel Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-14
Chapter 26
Watchdog Timer Module
26.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-1
26.1.1 Low-Power Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-1
26.1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-2
26.2 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-2
26.2.1 Watchdog Control Register (WCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-3
26.2.2 Watchdog Modulus Register (WMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-4
26.2.3 Watchdog Count Register (WCNTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-4
26.2.4 Watchdog Service Register (WSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-5
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Chapter 27
Programmable Interrupt Timers (PIT0–PIT3)
27.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-1
27.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-1
27.1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-1
27.1.3 Low-Power Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-1
27.2 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-2
27.2.1 PIT Control and Status Register (PCSRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-3
27.2.2 PIT Modulus Register (PMRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-5
27.2.3 PIT Count Register (PCNTRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-5
27.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-6
27.3.1 Set-and-Forget Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-6
27.3.2 Free-Running Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-6
27.3.3 Timeout Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-7
27.3.4 Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-7
Chapter 28
DMA Timers (DTIM0–DTIM3)
28.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-1
28.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-1
28.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-2
28.2 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-3
28.2.1 DMA Timer Mode Registers (DTMRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-3
28.2.2 DMA Timer Extended Mode Registers (DTXMRn) . . . . . . . . . . . . . . . . . . . . . 28-4
28.2.3 DMA Timer Event Registers (DTERn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-5
28.2.4 DMA Timer Reference Registers (DTRRn) . . . . . . . . . . . . . . . . . . . . . . . . . . 28-6
28.2.5 DMA Timer Capture Registers (DTCRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-7
28.2.6 DMA Timer Counters (DTCNn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-8
28.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-8
28.3.1 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-8
28.3.2 Capture Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-8
28.3.3 Reference Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-8
28.3.4 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-9
28.3.5 IEEE 1588 Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-9
28.4 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-9
28.4.1 Code Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-9
28.4.2 Calculating Time-Out Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-10
Chapter 29
Queued Serial Peripheral Interface (QSPI)
29.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-1
29.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-1
29.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-2
29.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-2
MCF5373 Reference Manual, Rev 3
xx Freescale Semiconductor
29.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-2
29.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-2
29.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-3
29.3.1 QSPI Mode Register (QMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-3
29.3.2 QSPI Delay Register (QDLYR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-5
29.3.3 QSPI Wrap Register (QWR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-6
29.3.4 QSPI Interrupt Register (QIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-6
29.3.5 QSPI Address Register (QAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-7
29.3.6 QSPI Data Register (QDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-8
29.3.7 Command RAM Registers (QCR0–QCR15) . . . . . . . . . . . . . . . . . . . . . . . . . . 29-8
29.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-9
29.4.1 QSPI RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-11
29.4.2 Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-12
29.4.3 Transfer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-13
29.4.4 Transfer Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-14
29.4.5 Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-14
29.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-15
Chapter 30
UART Modules
30.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-1
30.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-1
30.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-2
30.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-3
30.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-3
30.3.1 UART Mode Registers 1 (UMR1n) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-5
30.3.2 UART Mode Register 2 (UMR2n) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-6
30.3.3 UART Status Registers (USRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-8
30.3.4 UART Clock Select Registers (UCSRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-9
30.3.5 UART Command Registers (UCRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-9
30.3.6 UART Receive Buffers (URBn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-11
30.3.7 UART Transmit Buffers (UTBn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-12
30.3.8 UART Input Port Change Registers (UIPCRn) . . . . . . . . . . . . . . . . . . . . . . . 30-12
30.3.9 UART Auxiliary Control Register (UACRn) . . . . . . . . . . . . . . . . . . . . . . . . . . 30-13
30.3.10UART Interrupt Status/Mask Registers (UISRn/UIMRn) . . . . . . . . . . . . . . . 30-13
30.3.11UART Baud Rate Generator Registers (UBG1n/UBG2n) . . . . . . . . . . . . . . 30-15
30.3.12UART Input Port Register (UIPn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-15
30.3.13UART Output Port Command Registers (UOP1n/UOP0n) . . . . . . . . . . . . . 30-16
30.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-16
30.4.1 Transmitter/Receiver Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-16
30.4.2 Transmitter and Receiver Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . 30-18
30.4.3 Looping Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-22
30.4.4 Multidrop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-24
30.4.5 B
us Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-26
30.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-26
MCF5373 Reference Manual, Rev 3
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