Vishay IRFS9N60A Owner's manual

IRFS9N60A, SiHFS9N60A

www.vishay.com Vishay Siliconix

S21-0943-Rev. E, 20-Sep-2021 1Document Number: 91287

For technical questions, contact: hvm@vishay.com

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

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Power MOSFET

FEATURES

• Low gate charge Qg results in simple drive

requirement

• Improved gate, avalanche and dynamic dV/dt

ruggedness

• Fully characterized capacitance and avalanche

voltage and current

• Material categorization: for definitions of compliance

please see www.vishay.com/doc?99912

Note

This datasheet provides information about parts that are



RoHS-compliant and / or parts that are non RoHS-compliant. For



example, parts with lead (Pb) terminations are not RoHS-compliant.



Please see the information / tables in this datasheet for details

APPLICATIONS

• Switch mode power supply (SMPS)

• Uninterruptible power supply

• High speed power switching

APPLICABLE OFF LINE SMPS TOPOLOGIES

• Active clamped forward

•Main switch

Note

a. See device orientation

Notes

a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)

b. Starting TJ = 25 °C, L = 6.8 mH, Rg = 25 , IAS = 9.2 A (see fig. 12)

c. ISD  9.2 A, dI/dt  50 A/μs, VDD  VDS, TJ  150 °C

d. 1.6 mm from case

PRODUCT SUMMARY

VDS (V) 600

RDS(on) ()V

GS = 10 V 0.75

Qg max. (nC) 49

Qgs (nC) 13

Qgd (nC) 20

Configuration Single

N-Channel MOSFET

PAK (TO-263)

Available

ORDERING INFORMATION

Package D2PAK (TO-263) D2PAK (TO-263) D2PAK (TO-263)

Lead (Pb)-free and Halogen-free SiHFS9N60A-GE3 SiHFS9N60ATRR-GE3 a SiHFS9N60ATRL-GE3 a

Lead (Pb)-free IRFS9N60APbF IRFS9N60ATRRPbF a IRFS9N60ATRLPbF a

ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)

PARAMETER SYMBOL LIMIT UNIT

Drain-Source Voltage VDS 600 V

Gate-Source Voltage VGS ± 30

Continuous Drain Current VGS at 10 V TC = 25 °C ID

9.2

ATC = 100 °C 5.8

Pulsed Drain Current a IDM 37

Linear Derating Factor 1.3 W/°C

Single Pulse Avalanche Energy bEAS 290 mJ

Repetitive Avalanche Current a IAR 9.2 A

Repetitive Avalanche Energy a EAR 17 mJ

Maximum Power Dissipation TC = 25 °C PD170 W

Peak Diode Recovery dV/dt cdV/dt 5.0 V/ns

Operating Junction and Storage Temperature Range TJ, Tstg -55 to +150 °C

Soldering Recommendations (Peak temperature) dfor 10 s 300

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Notes

a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)

b. Pulse width  300 μs; duty cycle  2 %

c. Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80 % VDS

THERMAL RESISTANCE RATINGS

PARAMETER SYMBOL TYP. MAX. UNIT

Maximum Junction-to-Ambient RthJA -40

°C/W

Maximum Junction-to-Case (Drain) RthJC - 0.75

SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)

PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT

Static

Drain-Source Breakdown Voltage VDS VGS = 0, ID = 250 μA 600 - - V

VDS Temperature Coefficient VDS/TJ Reference to 25 °C, ID = 1 mA -0.66-

V/°C

Gate-Source Threshold Voltage VGS(th) VDS = VGS, ID = 250 μA 2.0 - 4.0 V

Gate-Source Leakage IGSS V

GS = ± 30 V - - ± 100 nA

Zero Gate Voltage Drain Current IDSS

VDS = 600 V, VGS = 0 V - - 25 μA

VDS = 480 V, VGS = 0 V, TJ = 125 °C - - 250

Drain-Source On-State Resistance RDS(on) V

GS = 10 V ID = 5.5 A b - - 0.75 

Forward Transconductance gfs VDS = 25 V, ID = 3.1 A 5.5 - - S

Dynamic

Input Capacitance Ciss VGS = 0 V,

VDS = 25 V,

f = 1.0 MHz, see fig. 5

- 1400 -

Output Capacitance Coss - 180 -

Reverse Transfer Capacitance Crss -7.1-

Output Capacitance Coss VGS = 0 V

VDS = 1.0 V, f = 1.0 MHz - 1957 -

VDS = 480 V, f = 1.0 MHz - 49 -

Effective Output Capacitance Coss eff. VDS = 0 V to 480 V c -96-

Total Gate Charge Qg

VGS = 10 V ID = 9.2 A, VDS = 400 V

see fig. 6 and 13 b

--49

nC Gate-Source Charge Qgs --13

Gate-Drain Charge Qgd --20

Turn-On Delay Time td(on)

VDD = 300 V, ID = 9.2 A

Rg = 9.1 , RD = 35.5

see fig. 10 b

-13-

Rise Time tr -25-

Turn-Off Delay Time td(off) -30-

Fall Time tf -22-

Gate Input Resistance Rgf = 1 MHz, open drain 0.5 - 3.2 

Drain-Source Body Diode Characteristics

Continuous Source-Drain Diode Current IS

MOSFET symbol

showing the

integral reverse

p - n junction diode

--9.2

Pulsed Diode Forward Current a ISM --37

Body Diode Voltage VSD TJ = 25 °C, IS = 9.2 A, VGS = 0 V b --1.5V

Body Diode Reverse Recovery Time trr TJ = 25 °C, IF = 9.2 A, dI/dt = 100 A/μs b - 530 800 ns

Body Diode Reverse Recovery Charge Qrr -3.04.4μC

Forward Turn-On Time ton Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)

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S21-0943-Rev. E, 20-Sep-2021 3Document Number: 91287

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TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

Fig. 1 - Typical Output Characteristics

Fig. 2 - Typical Output Characteristics

Fig. 3 - Typical Transfer Characteristics

Fig. 4 - Normalized On-Resistance vs. Temperature

0.1

100

0.1 1 10 100

20µs PULSE WIDTH

T = 25 C

J°

TOP

BOTTOM

VGS

15V

10V

8.0V

7.0V

6.0V

5.5V

5.0V

4.7V

V , Drain-to-Source Voltage (V)

I , Drain-to-Source Current (A)

4.7V

100

1 10 100

20µs PULSE WIDTH

T = 150 C

J°

TOP

BOTTOM

VGS

15V

10V

8.0V

7.0V

6.0V

5.5V

5.0V

4.7V

V , Drain-to-Source Voltage (V)

I , Drain-to-Source Current (A)

4.7V

0.1

100

4.0 5.0 6.0 7.0 8.0 9.0 10.0

V = 50V

20µs PULSE WIDTH

V , Gate-to-Source Voltage (V)

I , Drain-to-Source Current (A)

T = 25 C

J°

T = 150 C

J°

-60 -40 -20 020 40 60 80 100 120 140 160

0.0

0.5

1.0

1.5

2.0

2.5

3.0

T , Junction Temperature ( C)

r DS(on), Drain-to-Source On Resistance

(Normalized)

J°

V =

I =

10V

9.2A

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IRFS9N60A, SiHFS9N60A

www.vishay.com Vishay Siliconix

S21-0943-Rev. E, 20-Sep-2021 4Document Number: 91287

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Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage

Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage

Fig. 7 - Typical Source-Drain Diode Forward Voltage

Fig. 1 - Maximum Safe Operating Area

400

800

1200

1600

2000

2400

1 10 100 1000

C, Capacitance (pF)

V , Drain-to-Source Voltage (V)

V = 0V, f = 1MHz

C = C + C , C SHORTED

C = C

C = C + C

iss gs gd ds

rss gd

oss ds gd

iss

oss

rss

010 20 30 40 50

Q , Total Gate Charge (nC)

V , Gate-to-Source Voltage (V)

FOR TEST CIRCUIT

SEE FIGURE

I =

9.2A

V = 120V

V = 300V

V = 480V

0.1

100

0.2 0.5 0.7 1.0 1.2

V ,Source-to-Drain Voltage (V)

I , Reverse Drain Current (A)

V = 0 V

T = 25 C

J°

T = 150 C

J°

0.1

100

1000

10 100 1000 10000

OPERATION IN THIS AREA LIMITED

BY RDS(on)

Single Pulse

= 150 C

= 25 C

V , Drain-to-Source Voltage (V)

I , Drain Current (A)I , Drain Current (A)

10us

100us

1ms

10ms

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www.vishay.com Vishay Siliconix

S21-0943-Rev. E, 20-Sep-2021 5Document Number: 91287

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Fig. 8 - Maximum Drain Current vs. Case Temperature

Fig. 10a - Switching Time Test Circuit

Fig. 10b - Switching Time Waveforms

Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case

Fig. 12a - Unclamped Inductive Test Circuit Fig. 12b - Unclamped Inductive Waveforms

25 50 75 100 125 150

0.0

2.0

4.0

6.0

8.0

10.0

T , Case Temperature ( C)

I , Drain Current (A)

Pulse width ≤ 1 µs

Duty factor ≤ 0.1 %

D.U.T.

10 V

VDS

90 %

10 %

VGS

td(on) trtd(off) tf

0.01

0.1

0.00001 0.0001 0.001 0.01 0.1 1

Notes:

1. Duty factor D = t / t

2. Peak T = P x Z + T

1 2

JDM thJC C

t , Rectangular Pulse Duration (sec)

Thermal Response (Z )

thJC

0.01

0.02

0.05

0.10

0.20

D = 0.50

SINGLE PULSE

(THERMAL RESPONSE)

IAS

0.01 Ω

D.U.T

VDS

-VDD

Driver

15 V

20 V

IAS

VDS

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IRFS9N60A, SiHFS9N60A

www.vishay.com Vishay Siliconix

S21-0943-Rev. E, 20-Sep-2021 6Document Number: 91287

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THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

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Fig. 12c - Maximum Avalanche Energy vs. Drain Current

Fig. 13a - Basic Gate Charge Waveform Fig. 13b - Gate Charge Test Circuit

25 50 75 100 125 150

100

200

300

400

500

600

Starting T , Junction Temperature ( C)

E , Single Pulse Avalanche Energy (mJ)

TOP

BOTTOM

4.1A

5.8A

9.2A

QGS QGD

Charge

10 V

D.U.T.

3 mA

VGS

VDS

IGID

0.3 µF

0.2 µF

50 kΩ

12 V

Current regulator

Current sampling resistors

Same type as D.U.T.

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IRFS9N60A, SiHFS9N60A

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S21-0943-Rev. E, 20-Sep-2021 7Document Number: 91287

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THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

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Fig. 14 - For N-Channel



Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon

Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and

reliability data, see www.vishay.com/ppg?91287.

P.W. Period

di/dt

Diode recovery

dv/dt

Ripple ≤ 5 %

Body diode forward drop

Re-applied

voltage

Reverse

recovery

current

Body diode forward

current

VGS = 10 V a

VDD

ISD

Driver gate drive

D.U.T. ISD waveform

D.U.T. VDSwaveform

Inductor current

D = P.W.

Period

Note

a. VGS = 5 V for logic level devices

Peak Diode Recovery dv/dt Test Circuit

VDD

• dv/dt controlled by Rg

• Driver same type as D.U.T.

• ISD controlled by duty factor “D”

• D.U.T. - device under test

D.U.T. Circuit layout considerations

• Low stray inductance

• Ground plane

• Low leakage inductance

current transformer

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Document Number: 91364 www.vishay.com

Revision: 15-Sep-08 1

Package Information

Vishay Siliconix

TO-263AB (HIGH VOLTAGE)

Notes

1. Dimensioning and tolerancing per ASME Y14.5M-1994.

2. Dimensions are shown in millimeters (inches).

3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the

outmost extremes of the plastic body at datum A.

4. Thermal PAD contour optional within dimension E, L1, D1 and E1.

5. Dimension b1 and c1 apply to base metal only.

6. Datum A and B to be determined at datum plane H.

7. Outline conforms to JEDEC outline to TO-263AB.

Detail A

2 x e

2 x b2

2 x b

0.010 A B

MM ± 0.004 B

Base

metal

Plating b1, b3

(b, b2)

(c)

Section B - B and C - C

Scale: none

Lead tip

(Datum A)

2CC

View A - A

Seating plane

Gauge

plane

0° to 8°

Detail “A”

Rotated 90° CW

scale 8:1

L3 A1

MILLIMETERS INCHES MILLIMETERS INCHES

DIM. MIN. MAX. MIN. MAX. DIM. MIN. MAX. MIN. MAX.

A 4.06 4.83 0.160 0.190 D1 6.86 - 0.270 -

A1 0.00 0.25 0.000 0.010 E 9.65 10.67 0.380 0.420

b 0.51 0.99 0.020 0.039 E1 6.22 - 0.245 -

b1 0.51 0.89 0.020 0.035 e 2.54 BSC 0.100 BSC

b2 1.14 1.78 0.045 0.070 H 14.61 15.88 0.575 0.625

b3 1.14 1.73 0.045 0.068 L 1.78 2.79 0.070 0.110

c 0.38 0.74 0.015 0.029 L1 - 1.65 - 0.066

c1 0.38 0.58 0.015 0.023 L2 - 1.78 - 0.070

c2 1.14 1.65 0.045 0.065 L3 0.25 BSC 0.010 BSC

D 8.38 9.65 0.330 0.380 L4 4.78 5.28 0.188 0.208

ECN: S-82110-Rev. A, 15-Sep-08

DWG: 5970

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AN826

Vishay Siliconix

Document Number: 73397

11-Apr-05

www.vishay.com

RECOMMENDED MINIMUM PADS FOR D2PAK: 3-Lead

0.635

(16.129)

Recommended Minimum Pads

Dimensions in Inches/(mm)

0.420

(10.668)

0.355

(9.017)

0.145

(3.683)

0.135

(3.429)

0.200

(5.080)

0.050

(1.257)

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Revision: 01-Jan-2022 1Document Number: 91000

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Vishay IRFS9N60A Owner's manual

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