Tektronix PG 508 User manual

Brand: Tektronix

Model: PG 508

Category: Microphone accessories

Type: User manual

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Services

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Description

1-1

I

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1-1

SECTIO

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4

BASIC

OPERATION

Pe

r

io

d

and Dur

atio

n

Selectio

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1-2

D

u

ty

Facto

rs

1-2

Delaye

d

an

d

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ai

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Pu

lse

Selectio

n

1-2

Tra

n

sitio

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Time

Selectio

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1-3

O

u

t

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t

L

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1-3

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n

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Triggeri

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1-3

T

r

igger

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Tr

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PER

ATI

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SID

ERATIONS

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Termi

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ections

1-4

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ise

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SPE

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Instru

m

en

t

Description

Th

eP

G

508

is

α

50

MH

z

ge

n

eral

p

u

r

pose

full

fu

n

ction

pulse

generator

usable

in

all

TM

500-series

p

ower

modules

exce

p

t t

h

e

TM

501

.

It

is

co

m

p

atible

wit

h

M

OS

a

nd

ot

h

er

ge

n

eral

pu

r

p

ose

circ

u

itry

.

Im p

orta

n

t

featuresof

t

he

i

n

strume

n

t

include

indepen

d

ent

perio

d

and

d

uratio

n

con

trols

wit

h α

co

n

trol

error

lig

h

t,

inde

p

endent

p

u

lse

to

p

and

bottom

level

co

n

trols,

varia

b

le

leading

an

d

trailing

t

r

ansitio

n

time

ad

j

ustme

n

ts,

an

d

f

u

lly

a

d

j

usta

b

le

pulse

d

elay

ca

p

abilities

.

F

ront

pa n

el

controls

a

nd

con

n

ectors

p

rovi

d

e

α

trigger

or

sync

h

ronous

gate

in

p

ut

wit

h

level

an

d

slope

controls,

square

wave

out

p

ut

a

n

d

com

p

leme

n

tary

p

ulse

o

u

t

pu

t

for

h

ig

h

duty

factors

.

Delaye

d

and p

aire

d

pu

lse

an d

man

u

al

trigger

or

gate

ca

p

abilities

are

also

provi

d

ed

.

All

i

n

p

uts

an

d

outp

uts

are

i

n

ter

n

ally

termi

nated

in

50

Ω

exce

p

t t

h

e

TRIG/GAT

E

i

np

ut

w

h

ic

h

is

internally

selecta

b

le

foreither

50

Ω

o

r 1

ΜΩ

,

20 pF

i

np

ut

impe

d

ance

.

Special

positio

n

s

on

PER

IOD,

D

UR

ATIO

N

,

DE

L

AY,

an

d

TRA

N

SITIO

N

controls

p

ermit

customize

d

co n

trol

ranges

.

T

he

fro

n

t

p

a

n

el

is

color

code

d

for

easy

refere

nce

to

co

n

trols

a

n

d

t

h

eir

associated

f

u

nctio

ns

.

Gree

n

in

d

icates

triggeri

ng

fu

n

ctio

n

s

an

d

blue

in

d

icates

mode

fu

n

ctio

ns

.

Installation

an

d

R

emoval

T

he

P

G

508

is

calibrated

a

n

d

ready

for

use

w

hen

received

.

It

operates

in

any

two

com

p

artme

n

ts

of

t

he

ΤΜ

500-series

power

mod

u

les

.

See

t h

e p

ower

module

instruction

manual

for

li

ne

voltage

r

e

q

uireme

n

ts

a

nd

p

ower

module

o

p

eratio

n

.

F

ig

.

1-1

s

h

ows

t

he

installation

a

n

d

r

e

m

oval

proce

d

ure

.

M

ake

certai

n

t

he

power

mo

d

ule

is

off

w

h

e

n

inserti

ng

or

removing

t

he P

G

508

.

C

heck

t

h

att

h

e

P

G

508

is

fully

inserte

d

in

t

h

e

power

module

.

Pull

the

p

ower

switch

on

t

h

e

p

ower

mo

du

le

.

T

h

e

P

O

WER

lig

h

t

on

t

he

P

G

508

sh

o

u

ld

now

be

on

.

R

efe

r

to

t

he

Co

n

trols

and

Connectors

fol

d

o

u

t

page

i

n

Sectio

n

4

of

t

h

is

manual

for

α

com

p

lete

description

of

t

he

front

panel

controls

a

nd

co

nnectors

.

F

ig

.

1-1

.

P

G

508

i

n

stallatio

n a

nd

R

e

m

oval

.

Section

1---PG

508

Operating

In

st

r

uctio

n

s-PG

508

P

eriod

an

d

Du

r

ation

Selection

To

d

eter

m

i

n

e

t

h

e

custo

m

ca

p

acitor

val

ue

m

u

lti

p

ly

the

desi

r

ed

d

u

r

ation

o

r

d

elay

time

b

y

1

Χ

10-2

.

See

text

.

T

he p

erio

d ge

n

erato

r

ope

r

ates,

in

all

mo

des

exce

p

t

ΕΧΤ

TRIG

o

r

MAN,

at

α

rate

set

by

t

he

PER

IOD

ra

nge

switc

h

an

d

va

r

iable

co

n

t

r

ol

.

T

he

d

uratio

n

of

t

he output pulse

is

set

b

y

t

he

DURATION

r

ange

switc

h an

d

va

r

iable

control

.

Wh

e

n

t

he

DURATION

control

is

set

fo

r

αtime

greater

t

han

t

h

ePER

IOD,

t

h

e

CO

N

TRO

L

ERRO

R

lam

p

will

lig

h

t

.

Wh

en

t

he

D

UR

ATIO

N

co

n

trol

is

set

to

t

he

SQ

W

A

VE

positio

n

,

t

h

e

du

r

ation

time

is

d

ete

rm

i

ned

i

n

ternally

at

a

p

pr

oximately

50

ο/ο

of

t

he

p

erio

d

ti

m

e

.

T

h

e

custom

range

positio

ns on

t

he

PER

IOD

a

n

d

D

U

RATIO

N

controls

permit

u

ser-selecte

d pe

r

iod

a

nd

d

uratio

n

times

.

To

d

etermine

t

he

a

pp

roximate

ca

p

acitor

value

for

t

he d

esired

p

eriod,

multi

p

ly

t

h

e

p

e

r

io

d

time

in

seco

n

ds

b

y 5

Χ

10

-

' .

T

he

result

is

t

h

evalue

of

t

hecapacitor

i

n

F

arads

.

F

or

example,

α

50

ms

p

e

r

io

d

times

5Χ

10

-'

eq

uals

250

Χ

10

-6

or

250

μ

F

.

T

h

is

capacitor

mustbe

non-

polarized

and

h

ave

at

least

α

6

V

r

ating

.

Solde

r

t

h

is

ca

p

acitor

i

n

t

he p

ositio

n

s

h

own

i

n F

ig

.

1-2

.

To

d

etermine

t

he

capacitor

value

for

t

he

d

uration

time

d

esire

d

,

multi

p

ly

t

h

e

duration

time by

1

Χ

10

-2

.

F

or

example

α

50

ms

duration

time

re

q

uires

50

ms

times

1

Χ

P

erio

d

;"AT

Ι

Ν

10

-2

or α

500

μ

F ca

p

acitor

.

If

α

p

olarize

d

ca

p

acitor

is

use

d

,

observe

t

h

e

correct

p

ola

r

ity

.

Use

at

least

α

6

V

rated

cap

acitor

.

Co

nnect

t

h

is

cap

acitor as

s

h

ow

n

i

n

F

ig

.

1-2

.

Duty

F

actors

Duty

factors

greater

t

han

t

h

ose

sp

ecifie

d are

ob-

taina

b

le

on

several

ranges

.

Wh

en

t

h

e du

ty

facto

r

is

inc

r

eased

to

t

h

e

point

t

h

at

i

n

ter

n

al

circuitry

pr

eve

n

ts

completio

n

of

t

h

e

pulse

waveform,

the

CO

N

TRO

L

ERRO

R

lig

h

t

will flas

h

.

To

furt

h

er

i

ncrease

t

he duty

factor,

switc

h

to

t

h

e

com

p

leme

n

t

m

od

e

.

Set

t

h

e

D

UR

ATIO

N

control

for

α

p

u

lse

wi

d

t

h e

q

ual

to

t

h

e

d

esire

d

p

ulse

off

time an

d

p

ush

t

h

e

fro

n

t

p

a

n

el

CO

MPLE

M

E

N

T

(--)

pus

hb

utton

:

Delaye

d

and

P

ai

r

ed

P

ulse

Selection

In

t

h

e

pu

lse

d

elay

mode,

t

h

e

outp

ut

pulse

is

d

elayed

from

t

h

e

+TRIG

O

UT

sig

n

al

by

t

he

D

EL

AY

time

selecte

d

plus

α

specifie

d

fixed

d

elay

.

In

t

he

P

AI

RE

D

mode

of

o

p

eratio

n

,

t

he delay

controls

t

h

e

time

betwee

n

t

he

lea

d

i

ng

edges

of

t

h

e

p

ai

r

ed

p

u

lses

.

To

use

this

feature

pus

h

t

h

e

D

ELAY

b

utto

n and

trigger

t

h

e

external

device from

t

h

e

+TRIG

OUT

j

ac

k

.

Set

t

he

DE

L

AY

control

for

t

he d

esi

r

e

d

delay time

from

trigger

to

p

ulse

leading

ed ge

.

Use

t

he

varia

b

le

co

n

trol

labeled

CA

L

fo

r

ti

m

e a

dj

ustme

n

ts

betwee

n

ste

p

s

o

r

to

increase

t

he

delay

times

beyo

n

d

t

he

steps

.

TRIG/GAT

E

IN

input

imp

edan

ce

switc

h

.

F

i

g

.

1-2

.

L

ocat

i

on

s

of

pe

r

io

d

,

d

elay

and

dur

atio

n

custom

timi

ng

ca

p

acito

rs

and

TRIG/GATE

IN

input

im

p

e

da

n

ce

s

w

itc

h

.

R

emove

t

he

I

npu

t

b

oa

r

d

to

gai

n

access

to

t

he

d

elay

p

ads

.

REV

.

Α

,

A

PR

.

197

8

P

aired

pu

lses

are

obtai

ned

by

pus

h

i

ng both

t

h

e

D

EL

AY

and

UN

D

L

Y

b

u

ttons

.

An

initial

pulse

now

occurs

at

external

trigger

time

wit

h

t

he

secon

d

or

paire

d

p

ulse

delayed by

t

he

selected

delay time

.

The

CO

N

TRO

L

ERRO

R

lig

h

t

illuminates

if

t

h

e

d

elay

is

too

sh

ort

or

lo

ng

for

α

valid

p

ulse

train

.

Α

custom

d

elay

position

is

provi

de

d

on

t

h

e

DE

L

AY

switc

h

.

To

determine

t

h

e

val

ue

of

t

heca

p

acitor

require

d

,

multi

p

ly

t

h

e

desired

d

elay

time

i

n

seconds

by

1

Χ

10

-

Ζ

.

F

or

example,

α

50

ms

d

elay

time

re

q

uires

α

500

μ

F

ca

p

acitor

(50

ms

ti

m

es

1

Χ

10

-

Ζ

) .

U

se either

a

p

ola

r

ized

or

non-polarized

capacitor

wit

h

α

rati

n

g

of at

least

6

V

.

If

α

p

olarize

d

cap

acitor

is

u

sed,

observe

t

hep

olarity

mar

k

i

ngs

.

R

emove

t

he

i

np

ut

boar

d

and connect

t

he

capacitor

as

sh

ow

n

i

n F

ig

.

1-2

.

Transition

T

ime

Selectio

n

T

h

e

leadi

n

g

a

nd

traili

ng times

of

t

he p

ulses

may

be

varie

d

by

usi

n

g

t

he

TRA

N

SITIO

N

TIME

co

n

t

r

ol

an

d

t

he

LE

ADI

NG

a

nd

TRAI

L

I

N

G

va

r

iable

cont

r

ols

.

Select

t

he

desire

d

tra

n

sition

time

range

wit

h

t

he

TRA

N

SITIO

N

TIME

control

a

nd

vary

t

h

e

lea

d

i

ng and

traili

n

g

times

in-

d

epen

d

e

n

tly

wit

h

t

h

e

LE

ADI

N

G

an

d

TRAI

L

I

N

G

co

n

trols

.

Α

custo

m

range

position

is

also

provi

d

ed

on

t

h

e

TRA

N

SITIO

N

TIME

co n

trol

.

To

select

t

he

correct

capacitor

(i

n

F

arad

s)

for

this

ra

n

ge,

multi

p

ly

t

he

d

esire

d

transitio

n

ti

m

e

(in

seco

nd

s)

measured

from

10°/

ο

to

90°/

ο

poi

n

ts,

by 4

.4

Χ

10

-3

.

For

exa

mp

le,

α

d

esired

transitio

n

ti

m

e

of

50

ms

requires

α ca

p

aciator

of

220

μ

F

.

Con

n

ect

t

he

capacitoras sh

ow

n

i

n

Fig

.

1-3

.

U

se

αcapacitor

wit

h

at

least

α

10

V

rating

and

observe

p

olarity

r

equirements

.

Wh

en

t

he

tra

n

sitio

n times

become

la

r

ge

com

pared

wit

h

th

e

duratio

n

or

perio

d times an

d

t

h

e

pu

lse

d

oes

n

ot

reac

h

full

amplit

u

d

e,

t

he

CO

N

T

R

O

L

ERR

O

R

lig

h

t

will

flas

h

i

n

dicati

ng imp

ro

p

er

control

settings

.

Output

L

evels

T

h

e

o

u

t

pu

t

amplitude

and

offset

are

selected

b

y

i

n

depen

d

en

t

p

ulse

L

O

W

L

EV

E

L

and

H

IG

HLEV

E

L con-

trols

.

U

se

t

h

e

front

pa

n

el

voltage

calibratio

n

mar

k

s

fo

r

an

open

circuit

loa

d

an

d

divide

t

he values

b

y

two

w

h

en

t

h

e

P

G

508

is

o

p

erating

i

n

to

α

50

Ω

loa

d

.

The

O

U

TP

U

T

(VOLTS)

co

n

trols

are

interloc

ke

d

to

pr

eve

n

t

setti

ng

t

h

e

H

IG

H

L

E

VEL

m

ore

negative

t

han

t

h

e

L

O

W

LE

V

E

L

. . .

It

is

also

im

p

ossible

to

set

t

h

e

co n

trols

for

more

t

han

about

20

Vp

ea

k

to

pea

k out

p

u

t

am

p

lit

ud

e

i

n

to

an

o

p

e

n

circuit

o

r

10

V

i

n

to

50

Ω

.

P

ulse

amplitud

e

always

e

qu

als

t

he pulse

h

ig

h

level

minus

t

he

pu

lse

low

level

.

Offset

may

be

t

he

h

ig

h

level

or

t

he

low

level,

w

h

ic

h

ever

is

used

as

t

h

e

base

li

n

e

refere

n

ce

level

.

The

flexi

b

ility

of

t

h

is

met

h

o

d

is

useful

i

n ce

r

tai

n

a

pp

licatio

ns

suc

h as

logic

testing

.

E

it

h

er

t

he

h

ig

h

or

low

level

ca

n be

varied wit

h

out

disturbing

t

h

e

ot

h

er

.

REV

.

Β

,

A

PR

.

197

8

Operati

ng

Instructio

n

s-PG

508

To

determi

n

e

t

h

e

custom

ca

p

acito

r

value

m

u

lti

p

ly

t

he d

esired

d

ur

atio

n o

r

delay

time

by

1

Χ

10

-2

.

See

text

.

F

ig

.

1-3

.

L

ocatio

n

fo

r

tra

n

sitio

n

c

u

stom

timi

ng

capacito

r

.

T

he

p

ulse

h

ig

h an

d

low

levels

can

be

p

reset

.

Pu

sh the

PRESET

button a

nd

ad

ju st

t

h

e

HIGH

LE

V

EL and the

L

O

W

LE

VEL

poten

tiometers

wit

h

α

screw

d

river

for

t

he

d

esired

outp

ut

levels

.

E

xte

rn

al

T

riggering

a

nd

Gati

ng

Το

change

t

h

e'

ΓΗΙ

G/G

ΑΤΕ

IN

i

nput

i

mp

edance

r

e

m

ove

t

h

e

plug-i

n

from

t

he

mainframe

.

R

emove

t

h

e

left

si

d

e

cover

.

Set

t

he

sli

de

switc

h

,

locate

d

on

t

he

I

np

ut

boa

r

d

and

labele

d

I

npu

t

Impe

dan

ce,

to

eit

h

er

t

h

e

50

Ω

o

r

the

1

ΜΩ

positio

n

.

In

t

he

1

ΜΩ

positio

n

t

h

e

shun

t

capacita

nce

is

approximately

20 pF

.

Α

stan

d

ar

d

oscilloscope

p

ro

be

can

be

use

d

to

ac

qu

i

r

e

t

he

triggeri

ng

sig

n

al

from

t

he

external

circuit

r

y

.

If

α

compe

nsated

probe

is

use

d

,

calibrate

t

he

p

r

obe

on

t

h

e

i

npu

t

of

α

1

MO

20

pF

oscillosco

pe

first

.

Α

10

Χ

p

ro

be

allows

t

r

iggeri

n

g

d irectly

from

h

ig

h

impeda

nce

sources

s

uch as

M

OS

d

igital

circuit

r

y

wit

h an

effective

TRIG/GATE

L

EVE

L

range

of

+

:

.30

V

.

For

external

gating

select

t

he d

esire

d

p

erio

d

a

n

d

d

u r

atio

n

.

P

ress

t

he

SY

N

C

GATE

pus

h

button

.

Select

t

he

d

esired

trigger

slo

p

e

w

it

h

t

he+

or

~-

S

L

O

PE

bu

tto

n

.

T

he

OUTPUT

now

co

n

sists

of

pu

lses,

d

escri

be

d

by

t

he

f

r

o

n

t

p

a

n

el

controls,

w

h

enever

t

h

e

TRIG/GATE

IN

inp

u

t

ex-

cee

ds

t

he

TRIG/GATE

L

EVEL

cont

r

ol

setting

.

To

exter

n

ally

t

r

igger

t

he P

G

508,

connect

t

he

t

r

iggeri

ng

sig

n

al

to

t

h

e

TRIG/GATE

IN

co

nnecto

r

.

Select

t

he

slo

p

e

on

w

h

ic

h

triggeri

n

g

is

d

esi

r

e

d

wit

h

t

h

e

+

or

---

S

L

O

PE

b

utton

.

P

lace

t

h

eP

ERIOD

switc

h

i

n

t

h

e

ΕΧΤ

T

RIG

O

R

MAN

position

.

Now

adjust

the

TRIG/GATE

LEVELcontrol

for

t

h

e

d

esired

triggering

level

.

'T

he output

waveform

commences

ab

o

u

t

48 ns

after

t

he

triggering

signal

.

Operating

Instructions-PG508

For

external

DURATION

place

the

DURATION

control

i

n

t

h

e

ΕΧΤ

D

UR

p

osition,

and

t

h

e

PER

IOD

co n

trol

in

t

h

e

ΕΧΤ

T

R

IG

O

R

MAN

position

.

T

h

e

pe

r

io

d

and d

uratio

n

of

t

he

out

p

ut

waveform

are

now

co

n

trolled

by

t

he

triggeri

n

g

waveform

.

T

h

is is

an

extremely

useful

mo

d

e

of

o

p

eration

for

tra

n

slati

ng

logic

levels,

etc

.

If

t

he

PER

IOD

is

set

for

inter

n

al

o

p

eratio

n and

t

he

D

UR

ATIO

N

for

exter

n

al,

t

he

CO

N

TRO

L

ERR

OR

lig

h

t

illumi

n

ates

in

d

icati

ng an

illegal

mo

d

e

of

operatio

n

.

Th

e

TRIG'D/GAT

E

D

in

d

icator

lig

h

t

functio

ns as

α

TRIG/GATE

level

indicator

.

Wh

en

t

h

e-1-S

L

O

PE

is

selecte

d

and

t

h

e

exter

n

al

inp

u

t

level

excee

d

s

t

h

e

t

h

res

h

ol

d

set

by

t

he

T

R

IG/GATE

LEV

E

L co n

trol,

t

h

e

lig

h

t

is

on

continuous-

ly

.

F

or

i

npu

t

voltages

below

t

h

e

t

h

res

hold

t

h

e

lig

h

t

is

co

n

ti

nuously

off

.

Wh

en

t

he

i

n

p

ut

tra

n

sits

t

h

roug

h

t

h

e

t

hr

eshold

t

he

lig

h

t

flas

h

es

.

Wh

en

t

h

e-S

L

O

PE

is

selecte

d

t

he

lig

h

t

beh

aves

as

for

λ

-S

L

O

PE

selectio

n

.

H

owever,

t

he

p

olarities

are

reversed

.

TheT

R

IG'D/GATTED

i

nd

icator

lig

h

t

may

be

used

as

α

logic

level

i

nd

icator

for

troubleshooting

logic

circuitry

.

Set

t

he

TRIG/GATE

LEV

E

L

,

co

n

trol to

α

voltage

e

q

ual

to

t

h

e

midra

n

ge

val

u

e

of

t

he

logic

voltage

swing

.

If

an

atte

nuator

probe

is

use

d

for

signal

p

ic

k

u

p

,

re

m

em

b

er to

consid

er

t

he

atte

nu

ation

factor

w

hen

setti

ng

t

he

TRIG/GATE

LE

VEL

voltage

.

Trigger

Out

p

ut

T

he

signal

a

pp

earing

at

t

he co nnector

is

an ap-

proximate

square

wave

.

T

he

leadi

n

g

edge

(positive-going)

Output

Termi

n

ations

and

Co

nn

ections

T

h

eP

G

508

o

p

erates

as α

voltage

source

in

series

wit

h

an

i

n

ternal

50

Ω

im

ped

ance

.

M

aximum

p

ulse

fi

d

elity

is

obtai

ned

w

hen

t

he out

p

ut

op

erates

into

an

exter

n

al

50

Ω

impe

dance

.

The

out

p

ut

circuitry

of

t

h

eP

G

508

is

fully

p

rotecte

d

agai

n

st

any

voltage

transients

w

hen

o

p

erating

i

n

to

p

assive

loa

d

s

.

Table

1-1

lists

static

control

settings

t

h

at

illuminate

t

he

CO

N

TRO

L

ERR

OR

lig

h

t

a

nd

t

h

eir

corresponding

operati

n

g

modes

.

Some

of

t

h

ese

mo

d

es

may

be

u

seful

.

If

t

he

loa

d h

as

α

d

ovoltageacross

it,

co

nn

ect

α

b

loc

k

i

ng

capacitor

in

series

wit

h

t

h

e

O

U

TP

U

T

co

n

nector

an d

t

h

e

loa

d

.

M

a

k

e

certain

t

h

e time con

sta

n

t

of

t

h

e

capacitor

and

load

is

large

enoug

h

to

mai

n

tain

pulse top

flatness

.

p

recedes

the

output

pulse

by

α

s

pecified

fixed

delay

p

lus

t

h

e

delay

as

set

by

t

he

D

EL

AY

control

.

In

paired

p

u

lse

o

p

eratio

n

,

t

he

lea

d

ing

e

d

ge

p

rece

d

es

t

he

first

p

u

lse

b

y

t

he

fixed

delay

.

T

he

seco

nd

p

ulse

t

he

n

appears

after

t

he

set

d

elay

.

Α

com

p

leme

n

t

sq

uare

wave

(

n

egative-goi

n

g

leadi

n

g

edge)

is

also

available

at

t

he

front

panel by

movi

n

g

α

con

n

ector

on

t

h

e

timing

circuit

board

.

See

t

he

illustra-

tio

n

on

t

h

eR

ear

I

n

terface

Co

n

necto

r

Assignme

n

ts

at

t

h

e

rear of

t

h

is

man

u

al

for

t

h

e

locatio

n

of

t

h

is

co

n

nector

.

Manual

Trigger

To

use

t

h

is

featu

r

e p

lace

t

h

e

PER

IOD

switc

h

in

t

he

ΕΧΤ

TR

IG

OR

MAN

p

osition

.

Set

t

h

e

TRIG/GATE

LEVEL

control

fully

cloc

k

wise

.

If

t

he

+S

L

O

PE

is

selecte

d

,

t

he

ma

n

ual

trigger

will

occur

w

hen

t

he

MAN

button

is

d

epresse

d

.

If

t

h

e

--SL

O

PE

is

selecte

d

,

t

h

e

trigger

occ

u

rs

w

hen

t

h

e

butto

n

is

released

.

T

he

ma

n

ual

trigger

causes

o

n

e

out

p

ut

p

ulse,

or

α

set

of

paired pulses

if

t

he

D

EL

AY

a

nd

UN

D

L

Y

buttons

are

depresse

d

.

Control

E

rror

L

ig

h

t

T

h

e

CO

N

TR

O

L

ERR

O

R

lig

h

t

h

el

p

s

to

solve

set

up

pro

b

lems

by

i

n

dicati

ng

most

control

errors

.

Α

steadyglow

in

d

icates

static

co

n

trol setti

ng

errors

w

h

ile

α

flas

h

i

ng

lig

h

t

i

n

d

icates

d

y

n

amic

errors

.

In

eit

h

er

case,

t

h

e

control

settings

d

o

n

ot

co

r

rectly

i

nd

icate

t

he output

.

C

h

ec

k

t

he

co

n

t

r

ol setti

ngs

for

com

p

ati

b

ility

.

See

Table

1-1

.

Dynamic

fu

n

ctio

n

s

monitore

d are p

erio

d

,

d

elay,

duratio

n an

d

tra

n

sitio

n time

.

T

AB

LE

1-1

Control

Setti

n

gs



Operation

ΕΧΤ

TR

1G

Υ

O

R

ΜΑΝ

and~

ψ

---

SY

NC

GATE

ΕΧΤ

D

UR

and

Internal

P

eriod

ΕΧΤ

TRIG

O

R

MAN

and

SO

W

A

VE

(

ΙΝΤ

`

P

ERIOD)

SO

W

A

VE

(

ΙΝΤ

PE

R

IOD)

and

SY

NC

GATE

SO

W

A

VE

(

ΙΝΤ

PERIOD)

and

D

E

LAY

ΕΧΤ

D

UR

an

d

D

EL

AY

E

xter

n

al

Trigger

M

o

d

e

Square

W

ave

M

od

e

Truncated

s

q

uare

wave

w

h

en

gate

en

d

s

REV

.

Α

,

ΜΑΥ

,

197

6

R

iseti

ι

m

e

M

easurements

in

L

inear

Systems

Co

n

sider

t

he

r

ise

a

nd

falltime

of

associate

d

e

q

ui

p

me

n

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w

h

en

meas

u

ri

ng

t

he

rise

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m

e

of

α

li

neardevice

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t

h

e

risetime

of

t

he

d

evice u

nd

er

test

is

at

least

ten

times

slower

t

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t

he

combi

n

e

d

risetimes

of

t

h

eP

G

508,

t

he monitoring

oscillosco

p

e,

an

d

associate

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cables,

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he

error

introd

uce

d

will

n

ot

exceed

1

ο/ο

,

a

nd

u

sually

may

be

ig

nore

d

.

If

t

h

e

rise

or

falltime

of

t

h

e

test

d

evice

is

less

t

han

te

n

ti

m

es

slower

t

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t

h

e

com

b

i

n

e

d

risetimes

of

t

h

e

testing

systems,

dete

r

mi ne

t

h

e

act

u

al

risetime

of

t

he device

un

d

er

test

by

usi

n

g

t

he

followi

n

g

formula

:

R,

_=



U

R

Z

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

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z

z

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.

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uals

t

h

e

overall

rise

or

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of

t

h

e

entire

measu

r

e-

m

e

n

t

system

a

nd

R

i ,

R

2,

R,,

etc

.,

are

t

h

e

risetimes

or

falltimes

of

t

he

i

nd

ivi

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ual

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p

o

nen

ts

com

p

risi

ng

t

he

system

.

Extern

al

V

oltage

Co

n

trol

Th

e

h

ig

h

an d

low

level

output

voltages

can

be

con-

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d

externally

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h

roug

h p

i

n

s

22

Β

an d

Α

at

t

he

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interface

conn

ector

.

F

ig

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1-4

sh

ows

t

h

eeq

uivale

n

t

circ

u

it

.

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n

ectio

ns

must

be

made

fro

m

p

ad

Κ

to

pad L

and

p

ad

Μ

to

pad

Ν

located

as

s

h

ow

n

on

t

h

e a

dj

ustment

locatio

n

illust

r

ation

in

t

h

e

fol

d

out

pages

at

t

he

rear

of

t

h

is

ma

n

ual

.

Use or

d

inary

h

oo

ku p

wire

of

t

he p

ro

p

er

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n

gt

h

.

Solder

t

h

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to

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pa

d

s

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ote

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n

of

t

he

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xt

H

i

and

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xt

L

o

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on

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h

e

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ut

boar

d

.

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u

se

t

h

is

feat

u

re,

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t

he

f

r

o

n

t

p

an

el

co

n

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as

follows

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d

epress

t

he

PRESET

butto

n

(PRE

S

ET),

p

lace

t

h

e

PER

IOD

switc

h

in

t

he

ΕΧΤ

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Ι

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O

R

MAN

p

osition,

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UR

ATIO

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in

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UR

an

d

t

h

e

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EN

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(out)

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se

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river

to

ce

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ter

t

h

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xt

H

i

and

t

h

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p

reset

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IG

H

LEVEL

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Supp

ly

α

voltage

to

t

h

e

external

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ig

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n 22

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on

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nn

ecto

r )

equ

al

to

t

he

lowest

external

i

nput

voltage

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esired

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.

~

12

Κ

j

Ι

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xt

H

i

1

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Ι

R

1234

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Ι

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xt

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R

1230

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REV

.

Β

,

A

PR

.

197

7

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R

1236

Ι

Ι

R

1232

~

Use

r

i

n

stalle

d

ju

m

pe

r

s

-

Ι

-5 .2

V

F

ig

.

1-4

.

Eq

uivale

n

t

ci

r

cu

it

of

exte

rn

al

i

npu

t

fo

r

ou

t

p

ut

voltage

control

.

O

pe

r

ati

ng

I

n

structio

n

s-

P

G

508

Now

a

dj

ust

t

h

e

fro

n

t

p

a

n

el

preset

HIG

H

LE

V

EL

control

for

an

OU

T

PU

T

voltage

eq

ual

to

t

he

minim

u

m

d

esire

d

ou

t

pu

t

voltage

.

It

may

be

necessary

to

a

dju

st

t

he

preset

L

O

W

LE

V

EL

co

n

trol

as

t

he

OU

TP

U

T

voltage

is

limite

d

to

20

V

pea

k

to

pea

k

o

pe

n

circuit

.

T

he

h

ig

h

level

O

UT

PU

T

voltage

is

clam

p

e

d by

t

h

e

low

level

O

UT

PU

T

voltage

if

t

h

is

r

an

ge

is

excee

de

d

.

Now

apply

α

voltage

eq

ual

to

t

he

h

ig

h

est

exter

n

al

co

n

trol

voltage desired

to

t

he

same

rear

i

n

terface

co

nnector

(pin

22

Β

)

.

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j

ust

t

he

Ext

H

i

p

ote

n

-

tiometer

u

ntil

t

he h

ig

h

est

d

esired

o

u

tp

u

t

voltage

is

obtai

n

ed

.

It

may

be necessary

to

a

d

j

ust

t

he

preset

L

O

W

L

E

VEL

control

to

obtain

t

h

ed

esire

d

out

p

u

t

.

T

h

e

h

ig

h

level

OUTP

U

T

voltage cann

ot

go

below

t

he

low

level

OUTP

U

T

voltage

d

ue

to

t

h

e

level

control

voltage

clam

p

s

.

T

he

E

xt

H

i

an

d

t

h

e p

reset

HIG

H

LE

V

E

L

controls

interact

.

It

may

be

n

ecessary

to

re

p

eat

the

above

p

rocedu

re

several

times

until

t

he

d

esired

results

are

obtai

n

e

d

.

Now

push

t

h

e

N

O

RM CO

MP

LE

ME

N

T

switc

h

(CO

MPL

E

ME

N

T)

.

Center

t

he Ext

L

o

an

d p

reset

L

O

W

LEVE

L potentiometers

.

S

upp

ly

α

voltage

to

p

in

22

Α

of

t

he

rear

interface

co

nn

ector

equal

to

t

he

lowest

exte

rn

al

control

voltage

desire

d

.

A

dj

ust

t

he

p

reset

L

O

W

LEV

E

L

control

for

an

O

U

TP

U

T

voltage

e

q

ual

to

t

h

e

lowest

OU

TP

U

T

voltage

desi

r

e

d

.

C

h

ange

t

h

is

voltage

to

t

he

h

ig

h

est

d

esired

exter

n

al

co

n

trol

voltage

.

Ad

j

ust

t

he

Ext

L

o

potentiometer

for

t

he

h

ig

h

est

O

U

T

PU

T

voltage

desire

d

.

As

t

h

ese

a

dj

ustments

i

n

teract,

read

j

ust

t

he

preset

L

O

W

LEVEL

and

t

he

E

xt

Lo

potentiometers

for

t

he

desire

d

results

.

Do

n

ot

rea

dj

ust

t

he p

reset

HIG

H

LEV

EL

or

t

he E

xt

H

i

potentiometers

.

-

T

h

e

O

U

TP

U

T

voltages

now

vary

linearly

and

in

d

epe

nd

ently

wit

h

t

he

exter

n

al

co

n

trol

voltage

.

Cou

n

te

d

B

u

r

st

Using

t

he

DD

501

Digital

Delay

U

nit

Th

is

ap

p

licatio

n pe

r

mits

p

reselecti

ng

t

h

e

nu

mber

of

output

p

ulses

from

t

he

P

G

508

.

T

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i

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itiate

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n

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ulse,

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sig

n

al

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fro

m

t

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P

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L

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1-6

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PG

508-DD

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012-0208-00

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2044-30

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.

Α

,

A

PR

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1977

To

u

se

t

h

is

feat ur

e,

p

lace

t

h

e

DD

501

i

n

t

he

d

elay

interval

m

o

d

e

of

o

p

eration

b

y

moving

t

h

e

wi

r

e

st

r

ap

as

s

h

ow

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i

n

Pig

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1-5or cha

n

ging

con

n

ectio

n

s,

de

pe

nd

i

ng on

t

he

DD

501

availa

b

le

.

Co

nnectthe

P

G

508

a

n

d

t

he

DD

501

as sh

ow

n

in

F

ig

.

1-6

.

U

se

te

n

i

n

c

h

(Te

k

t r

on

ix

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art

Nu

m

b

er

012-0208-00)

o

r

sh

orter

cables

forinterconnecting

t

h

etwo

u

nits to

r

ed

uce

d

elays

.

M

ake

certai

n

t

he

PG

508

TRIG/GATE

IN

i

nput im-

p

eda

nce

is

set for

50

Ω

.

(See

E

xternal

Triggering

an

d

Gati

n

g

d

isc

u

ssio

n

an

d

Fig

.

1-2

.)

Set

t

h

e

controls

of

t

h

e

P

G

508

for

t

he

desire

d

output

waveform

wit

h

t

h

eP

G

508

i

n

FREE

R

UN

.

Do

n

ot

use

t

h

e

SQ

W

A

VE

mo

de

.

Place

t

h

e

P

G

508

i

n

t

h

e

-

Ι

-

S

L

O

P

E,

SY

NC

GATE

mode

a

n

d

set

t

h

e

TRIG/GATE

L

EV

E

L

control

at

t

h

e

2

o'clock

p

osition

.

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EVENTS

-+-

S

L

O

PE,

STA

RT+

S

L

O

PE

and

place

the

EV

E

N

TS

a

nd

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R

T

LEV

E

L

co

n

trols

at

t

h

e

2

o'clock

p

ositio

n

on

t

he

DD

501

.

T

h

e

t

h

ree

TRIG'D

lig

h

ts

on

t

he

DD

501

an

d

t

h

e

TRIG'D/GATED

lig

h

t

on

t

he

P

G

508

will

b

e

off

until

t

h

e

DD

501

is

t r

igge

r

ed

.

Up

o

n

receipt

of

α

trigger,

all

lig

h

ts

will

ill

u

mi

nate

.

If

n

ot,

check

t

he

set

up

an

d

slig

h

tly

a

d

j

ust

t

he L

E

VEL

co

n

trols

as

necessary

.

RE

V

.

Α

,

A

PR

.

1977

25

n

s

,

.

._

_

.__

..

ο

PG

508

+

T

R

IG

O

U

T

At

PG

508

r

ep

etitio

n

rates

b

elow

abou

t

20

MHz

t

he

ext

r

a

pu

lse

cou

n

t

is

o

ne

.

Fr

o

m

ab

out

20

MHz

to

50

MHz

t

he

w

orst

case

ext

r

a

pu

lse

co

u

nt

is

two

.

T

he

a

bove

conditio

ns a

r

e

t

r

ue

only

wit

h

te

n

i

nch

or

sh

o

r

te

r

interco

nn

ecti

n

g

cables

.

Fig

.

1-7

.

Typ

ical

pr

op

agatio

n d

elays

u

sing

PG

508

wit

h

DD

501

i

n

cou

n

ted

bu

r

st

m

ode

at

50

MHz

re

p

etitio

n

rate

.

_

χ

STA

R

T

TRIGG

ER

TODD

501

(5

n

s

o

r

lo

nge

r )

DD

501

DE

L

AY

I

N

TER

V

A

LO

U

TP

U

T

25

n

s

35

n

s_

.

.



Ι

TOTAL

TIME

FROM

DD

501

STA

R

T

TRIGGER

TO

F

I

R

ST

PG

508

PUL

SE

IS

-

85 ns

.

Operating

I

n

st

r

uctio

n

s-

P

G

508

Set

t

h

e

EV

EN

TS

D

EL

AY

CO

U

NT

Οη

t

he

DD

501

fo

r

o

n

e

less

t

h

a

n

t

he d

esired

num

b

er of

cou

n

ts

up

to

P

G

508

re

p

etitio

n

r

ates

of

ab

out 20

MH

z

.

See

below

fo

r

f

u

rt

he

r

i

n

for

m

atio

n

.

If

n

ecessary,

α

single

t r

igger

maybe

o

b

tai

ned

by

r

otati

n

g

t

h

e

DD

501

START

LEV

EL

co

n

t

r

ol

t

hr

oug

h

t

he

0

p

ositio

n

,

wit

h

no

extern

al

trigger

applie

d

.

Α

si

n

gle

t

r

igge

r

may

also

be

obtai

n

edby

u

si

n

g

t

he

TEKTRONIX

ma

n

ual

(O

n

eS

h

ot)

Trigge

r

Generator,

Te

k t r

onix

P

art

Nu

m

be

r

016-0597-00

.

All

ot

h

e

r

DD

501

a

nd

P

G

508

o

pe

r

ati

ng

co

n

trols

fu

n

ctio

n normally

.

Due

to

p

ropagation d

elays

in

t

h

eP

G

508,

DD

501 an

d

t

he

i

n

terco

nn

ecti

ng

cables,

one

or

more

pulses

in

a

dd

itio

n

to

t

h

e

desi

r

e

d

n

u

m

be

r

are generated

w

hen

t

h

eP

G

508

re

p

etitio

n

r

ates

a

r

e

set

between

20

MHz

and

50

MHz

.

T

h

ese

ext

r

a

p

u

lses

are

consistant

for

any

given

fre

q

uency

i

rr

esp

ective of

the

d

esire

d

EVEN

TS

DE

L

AY

CO

U

NT

setti

ng

.

To

determine

t

h

e

n

u

m

ber

of

extra

pu

lses

for

α

give

n

PG

508

perio

d

,

set

t

h

eP

G

508

an

d

t

he

DD

501

controls

as

previously

described

.

Now

a

dju

st

t

he

P

G

508

TRIG/GATE

L

EVEL

o

r t

h

e

DD

501

EV

ENTS

L

E

V

E

L

fo

r t

h

e

same

n

umbe

r

of

extra

p

ulses

at

DD

501

E

VE

N

TSDE

L

AY

CO

U

N

T

setting

of

ze

r

o a

nd

n

ine

.

EXTRA

TRIGGER

OU

TP

UT

WH

E

N

O

PER

ATI

NG

PG

508

at

50

MHz

Ι

.

<-----

D

E

SI

R

ED

CO

U

NT

O

F F

I

VE

EXTRA

P

G

508

P

U

L

S

E

O

U

T

PU

Τ

PUL

S

ES

αοαα

-

α

i

O

pe

r

ating

Instructions-PG

508

Defi

n

itio

ns

of

P

ulse

C

ha

r

acteristics

T

he

followi

n

g

is

α

glossary

of

commo

n p

ulse

c

h

aracteristics

u

sed

in

t

h

is

ma

n

ual

.

T

hey are

illust

r

ate

d

i

n

F

ig

.

1-8

.

Amplitude

.

T

he

m

aximum

absolute

p

eak value

of

α

pu

lse

m

eas

u

re

d

from

t

he

b

aseli

ne

r

ega

r

dless

of

sig

n

,

a

nd

excl

ud

i

n

g

un

wa

n

te

d

abe

rr

atio

n

s

o

r

ove

r

shoot

.

M

eas

u

re-

me

n

t

p

oi

n

ts

are

at

50

ο/ο

of

t

he

p

ulse

du

r

atio

n time

(

pu

lse

h

ig

h

level)

a

ndon

t

h

e

baseli

ne

(

p

ulse

low

level)

at

50

ο/ο

of

t

h

e

off

ti

m

e

(t

h

e

p

ulse

p

e

r

io

d

m

i

n

us

t

he

pu

lse

du

r

atio

n

) .

A

b

erratio

ns

.

U

nwa

n

te

d

deviatio

ns or excursions

i

n

t

h

e

pulse sh

ape

form

an

ideal

squ

are

corn

er

a

nd

flat

to

p

, i

.e

.,

oversh

oot,

und

ers

h

oot

or round

i

n

g,

ri

n

gi

n

g,

a

nd

tilt

or

slo

pe

.

B

aseli

n

e

.

T

he q

uiesce

n

t

do

voltage

refere

n

ce

level

of

t

h

e

p

ulse

waveform

.

Com

p

leme

n

tary

P

ulse

.

N

ormal

p

ulse

wit

h h

ig

h an

d

low

levels

i

n

terc

h

a

n

ge

d

.

Pu

lse

on-time

b

ecomes

pulse

off-

time

.

Duty

Factor

.

Someti

m

es

referre

d

to

as

d

u

ty

cycle

.

T

h

e

ratio

of

p

u

lse

du

ratio

n

to

p

erio

d

,

or

t

he

p

ro

duct

of

p

ulse

du

ration

and

pu

lse

repetitio

n

rate

.

Duty

factor

in

ο/ο

==

Duration/

P

erio

dΧ

100

.

F

alitime

.

T

he time

interval,

at

t

h

e

pulsetraili

n

ged

ge,

for

t

he pu

lse

amplit

u

de

to

fall

from

t

he

90%

am

p

litu

d

e

level

to

t

he

10%

ο

amplitu

d

e

level

.

Overs

h

oot



φ

4

Ρυ

1se

D

ur

atio

n

Pulse

Top

F

lat

n

ess

D

u

ty

F

actor

=

Pulse

D

u

ratio

n

/

P

ulse

P

erio

d

B

aseli

ne

F

lat

n

ess

Pulse

P

erio

d

Τ

=

1/

R

ate

F

ig

.

1-8

.

Pulse

cha

r

acteristics

.

Flat

ness

.

T

he

abse

n

ce

of

lo

ng term

variations

to

t

he

p

ulse

to

p

;

exclud

i

ngoversh

oot,

ringing

or

p

u

lse

ro

u

nding

.

Sometimes

r

eferred

to

as

tilt

or

slo

pe

.

H

ig

h

Level

.

The

most

p

ositive

value

of

α

pulse,

regar

d

less

of

unwanted

a

b

erratio

ns or oversh

oot,

measu

r

ed

at

α

p

oi

n

t

t

h

at

is

locate

d

at

50

ο/ο

of

t

h

e

p

ulse

d

uratio

n

.

L

ow

L

evel

.

Th

e

most

n

egative

value

of

α p

ulse,

rega

r

dless

of

un

wa

nted ab

erratio

ns

o

r

ove

r

s

h

oot,

measure

d

at

α

point

t

h

at

is

50%

ο

of

t

h

e

off

time

.

Offset

.

Α

do

p

otential

of

eit

he

r

p

olarity

ap p

lie

d

to

t

he

waveform

to bias

t

he

baseline

to

an

am

p

litu

d

e

ot

h

er

t

h

a

n

zero

.

Overs

h

oot

.

T

h

e

s

h

ort

term p

ulse

excursion

(o

r

tra

n

-

sie

n

t)

above

t

h

e

pu

lse

to

p

or

below

t

h

e

baseli

n

e,

w

h

ic

h

is

simultaneo

u

s

to

t

h

e

lea

d

i

ng

or

traili

ng

edge

of

t

h

e

p

ulse

.

P

erio

d

.

T

h

etime

interval

forafull

pulsecycle,

inverse

*

of

fre

qu

e

ncy

or repetition

rate,

or

t

h

e

interval

b

etween

corres

po

n

di

ng

pu

lse

am

p

litudes

of

two

co

n

secutive

υη

-

delayed

or

delaye

d

pu

lses

.

Ge

n

erally

meas

u

re

d b

etween

t

h

e

50

ο

/

ο

am

p

lit

u

de

levels

of

two

co

n

sec

u

tive

p

ulses

.

P

res

h

oot

.

Α

tra

n

sie

n

t

exc

u

rsio

n

t

h

at

prece

des

t

he

ste

p

fu

n

ctio

n

.

It

may

be

of

t

h

e

same

or

opposite

p

ola

r

ity

as

t

h

e

pulse

.

REV

.

Β

,

A

PR

.

1977

Pu

lse

Duration

.

T

h

e

time

interval

between

t

he

leadi

ng

a

nd

traili

n

g

e

d

ge

of

α pu

lse

at

w

h

ic

h the

insta

n

ta

n

eous

am

p

lit

ud

e

r

eac

h

es

50

ο/ο

of

t

he

pea

k

p

ulse

am

p

litude

.

P

olarity

.

T

he d

irectio

n

f

r

om

t

he

baseli

n

e

of

t

h

e

p

ulse

exc

u

rsio

n

,

eit

h

er

p

ositive-goi

ng

(+)

or

n

egative-goi

ng

R

ingi

n

g

.

P

erio

d

ic

abe

r

ratio

ns

t

h

at

d

ampen

in

time,

followi

ng

t

he

oversh

oot

.

PER

IOD

:

R

ange

:



<20

ns



to



>200

m

s



i

n



seven

deca

d

e

ste

ps

p

lus

va

r

iable,

wit

h

overlap

on

all

ra

n

ges

.

P

erio

d

s

longer

t

h

an

200

ms

can be o

b-

tai

ned

i

n

custom

range

p

ositio

n

.

J

itter

:



<0

.1

ο/ο

-i-50

p

s

.

D

EL

AY

:

(Time

b

etween

leadi

ng

transitio

ns

i

n the

paire

d

p

ulse

mode)

R

ange

:



<10

n

s



to



>100

ms



i

n



seve n

d

ecade

ste

p

s p

lus

variable,

wit

h

overla

p

on

all

r

an

ges

.

Delays

longer

t

h

an

100

ms

ca n

be

o

b-

tai

n

ed

i

n

custom

r

an

ge

p

osition

.

Duty

F

actor

:



Delays

to at

least

70

ο/ο

of

pu

lse

periods

for

perio

ds

of

0

.2

μ

s

or

greater,

d

ecreasing

to at

least

50

ο/ο

for

α 20 ns p

erio

d

.

seven

d

ecade

ste

p

s

p

l

us

variable,

wit

h

overla

p

on

all

r

anges

.

D

u

ratio

ns

lo

n

ger

t

han

100

ms

can

be

o

b-

tai

n

ed

i

n

custom

range

positio

n

.

An

ad

d

itio

n

al

positio

n

provides

du

r

atio

ns

of

a

pp

roximately

50

ο

/ο

of

t h

e p

erio

d

setting

for

square

wave

out

p

ut

.

Duty

F

actor

:



P

ulse

d

urations

to

at

least

70

ο

/

ο

of

p

ulse

p

erio

ds

for

perio

ds

of

>0

.2

μ

s,

d

ecreasing

to

at

least

50

ο/ο

fo

r

α 20

n

s p

eriod

.

Operating

I

n

st

r

uctions---PG

508

R

isetime

.

T

h

e

time

i

n

terval,

at

t

he

ste

p

fu

n

ctio

n

lea

d

i

n

g

ed

ge, for

t

h

e

p

ulse to

r

ise

from

t

h

e

10

ο

/

ο

to

90

ο/ο

am

p

litude

levels

.

R

ounding

or

U

nde

r

shoot

.

T

h

e

roun

d

i

ng

of

t

he pu

lse

corners

at

t

he ed

ges

of

α

ste

p

f

un

ctio

n

.

Tilt

o

r

Slope

.

Α

d

istortio

n

of

an

ot

h

erwise

flat-toppe

d

p

ulse,

c

h

aracterized

by

eit

h

er

α

decli

n

e

or

α

rise

of

t

he

p

ulse

top

(see

F

lat

n

ess)

.

J

itter

:



<0

.1%

ο

-1-50

ps

.

PUL

S

E

O

U

TP

U

T

:

Transitio

n

Times

: I

nd

e

pe

nd

ently

adjustable

lea

d

ing

a

nd

traili

ng

tra

n

sitio

n

times

from

<5

ns ty

p

ical

(<7

n

s

at

some

offset

a

nd

amplit

u

de

levels)

to

>50

ms,

measure

d from

t

h

e

10

ο

/ο

p

oi

n

t

to

t

he

90

ο

/

ο

poin

t,

i

n

six

d

ecade

steps

p

l

u

s

variable

.

V

aria

b

le

co

n

trols

wit

h

100

:1

ra

n

ge

(50

:1

on

5

n

s)

p

rovide overla

p

on

all

ra

n

ges

.

T

r

an

sition

times

lo

n

ge

r

than 50

ms

a

r

eob

tai

n

able

i

n

t

h

e

custo

m

ra

nge

p

ositio

n

.

Transitio

n

Deviatio

n

from

straig

h

t

li

ne

<5%

ο

L

i

n

earity

:



between

t

he 10

ο/ο

αη

d

90

ο

/

ο

poi

n

tfo

r

tra

n

sitio

n

times

greater

than

10

n

s

.

Am

p

litu

d

e

:



P

ulse

h

ig

h

a

nd

low

levels

i

n-

depe

nd

e

n

tly

ad

j

usta

b

le

ove

r

α

+20

V

ra

n

ge

from

α

50

Ω

low

reac

ta

nce

sou

r

ce

.

M

aximu

m

p

ulse

am

p

litu

d

e

into

α50

0

load

is->10 .V

p

eak

to

peak

;

minimum

is

<0

.5

V

p

eak

to

peak

.

M

aximum

p

ulse

am

p

litu

d

e

i

n

to

an

o

p

en

circ

u

it

is

>20

Vp

eak

to

p

ea

k

;

minimum

is

<1

.0

Vp

eak

to

pea

k

.

T

h

e

preset

level

con

trols

are

a

dj

ustable

over

t

h

e

same

ra

n

ges

.

Abe

r

ratio

n

s

:



<5

ο/ο

,

+50

m

V

into

α

50

Ω

loa

d

fo

r

pu

lse

levels

betwee

n

+5

V

.

May

i

ncrease

to

<,10

ο/ο

,

+-50

m

V

for

pu

lse

levels

o

u

tsi

de

t

h

is

r

a

n

ge

.

TRIGG

ER

O

U

TP

UT

:

Am

p

litu

de

:



>+2

V

from

50

Ω

.

J

itter

:

<-0

.1%

to

+50

ps

.

D

UR

ATIO

N

R

an

ge

:

<10

n

s

to

>100

ms

i

n

O

pe

r

ati

ng

Instructions--

P

G

508

Source

Impeda

nce

:

500

.

Duty

Cycle

:

I

n

te

rn

al

Trig-

ge

r i

ng

-50

ο/

ο

.

E

xter

n

al

Trig-

geri

ng



Determi

n

ed

b

y d

uty cycle

of

triggeri

n

g

sig

n

al

.

TRIGG

ER

/GATE

I

NPU

T

:

Se

n

sitivity

:



80

m

V

pea

k

to

pea

k

to >_10

MHz

;

250

m

V

pea

k

to

pea

k

to

50

MH

z

at

50

Ω

i

nput

impe

d

ance

.

I

np

ut

Im

ped

a

n

ce

:



I

n

ter

n

ally

selecte

d

,

50

Ω

o

r 1

MO

p

arallele

d by

-20

pF

.

M

aximum

I

np

ut

:



_4_5

V

pea

k

into

50

Ω

,

±-20

V

peak

into

1

ΜΩ

.

M

i

n

im

u

m

Input

P

ulse

W

i

d

t

h

:



10 n

s

.

Trigger

Level

:

P

olarity

:



F

ro

n

t

pa

n

el

selectable,

-h-

or

--

slope

.

R

an

ge

:



±3

V

.

TR

IG'D

GATED

LIG

HT

:

Flas

h

i

n

g

:



I

np

ut

triggered

at

greate

r

t

h

an

ap-

proximately

α

10

Hz

repetition

rate

o

r

followi

ng

t

h

e

in

p

ut

sig

n

al

at

slower

re

p

etitio

n

rates

.

On

:

(

L

ogic

T

r

ue)



T

RIG/GATE



IN



i

np

ut

potential

above

TR

IG/GAT

E

LEVEL

setting

with

-+-

SL

O

PE

selected

or

below

T

RIG/GATE

L

E

V

E

L

setti

ng

wit

h

SL

O

PE

selecte

d

.

Off

:

(

L

ogic

F

alse)

TRIG/GATE

IN

i

npu

t

potential

below

TRIG/GAT

E L

E

VEL

wit

h

S

L

O

PE

selecte

d

or

a

b

ove

TRIG/GATE

LEV

EL

wit

h

-

S

L

O

PE

selecte

d

.

Sy

nch

ro

nous

Gate

:



R

ate



ge

nerator



starts



syn-

ch

ro

nously

wit

h

external

gating

signal

and

co

m

pletes

t

he

last

out-

p

ut

pulse

.

PUL

S

E

DELAY

M

OD

ES

:

Und

elaye

d

,

d

elayed an

dp

ai

r

ed

.

P

aire

d p

ulse

m

ode

limite

d

to

25

MHz

.

M

i

n

imum

p

ulse

sep

aratio

n

gover

n

ed by

d

u

r

atio

n

d

uty

factor

s

p

ecificatio

n

.

F

IX

ED

DE

L

AYS

:

Trigger

O

u

t

to

Pu

lse

O

u

t

:



-=23

ns

.

Gate

I

np

ut to

Trigger

Out

:



-25

n

s

.

CO

N

TRO

L

ERR

O

R

L

IG

HT

:

Stead

y

On

:



I

nd

icates

invalid

operating

mo

d

e

.

O

u

tp

u

t

is

und

efi

n

ed

.

F

las

h

i

ng

:



Timing

con

trol setti

ngs

selecte

d

d

o

not

pro

p

erly

define

t

h

e

out

p

ut

p

u

lse

b

eca

use

valid

limits

have

bee

n

exceeded

.

Steady

Off

:



I

n

dicates

valid

o

p

eratio

n

fo

r

most

co

n

trol setti

ngs

.

P

O

W

ERRE

QU

I

REMEN

T

:

N

omi

n

al

:



40

W

atts

M

aximu

m

:



45

W

atts

P

O

WER

DISSI

P

ATIO

N

:

N

o

m

inal

:



25

W

atts

M

axim

u

m

:



28

W

atts

WE

IG

H

T

:



3

.5

lbs

.

I

n

tro

d

uction

R

efer

to

t

he block d

iagra

m

an

d

t

he

sc

h

ematics

i

n

t

h

e

fol

d

o

u

t

p

ages

at

t

he

rear

of

t

h

is

manual

as

well

as

t

h

e

followi

n

g

discussio

n

to

understan

d

t

h

e

operation

of

t

h

e

P

G

508

.

Input

Ci

r

cuitry

T

h

is

circuit

r

y

p

r

ocesses

t

h

e

external

trigger

or

gati

ng

sig

n

al

p

rovi

d

i

ng

trigge

r

i

n

g

waveforms

for

t

he

p

eriod

circ

u

it

.

T

h

e

50

Ω

input

impedance

for

t

h

is

circuitry

is

p

rovi

de

d

by

R

12,

switc

h

ed

in

orout

by

i

n

ter

n

al

switch

S12

.

Wh

en

R

12

is

ou

t

of

t

he

circuit,

t

he

i

n

put

impeda

n

ce

is

1

Μ

Ω

,

obtained

b

y R14

a

nd

R

16

.

Dio

des

C

R

16

a

nd

C

R

17

are p

rotective

d

io

des

.

T

h

e proper voltage

at

t

he

d

rai

n

of

020

is

set

by

VR

20

.

The

source

voltage

of

Q20

is

set

by

VR

22

.

Im

p

edan

ce

transformation,

wit

h

no

voltage

sh

ift,

is

obtai

n

e

d b

y

sou

r

ce

follower

Q20

.

Co

n

sta

n

t

cu

rrent

for

Q20

is

s

upp

lie

d

b

y

Q22

.

Α

d

ifferential

comparator

is

forme

d

b

y

025

an d

Q26

.

T

h

is

co

m

parator

compa

r

es

t

he

trigger

or gate inpu

t

level

wit

h

t

he

level

set

by

t

he

fro

n t

p

an

el

TRIG/GATE

control

.

Consta

n

t

curren

t

for

t

h

is

comparator

is

provided by

Q30

.

L

evel

co

n

t

r

ol

voltage

fo

r

t

h

e

d

iffere

n

tial

com

p

arator

is

p

rovi

ded by

o

p

eratio

n

al

a

m

p

lifier

U

40

.

T

he out

p

ut,

p

i

n

6,

swi

ngs over α

ra

n

ge

of

±3

V

.

T

hevoltage

at

ΤΡ

36

is

t

h

e

triggeri

n

g

level

voltage,

as

set

b

y

t

he

TRIG/GATE

LE

V

E

L

co

n

trol

.

If

t h

e

triggering

or

gati

n

g

voltage

at

t

he b

ase

of

Q25

is

more

p

ositive

t

h

at

ΤΡ

36,

t

hen

Q26

is

cond

u

cti

n

ga

nd

Q25

is

off

.

T

h

is

places

t

h

e

collector

of

Q26

more

positive

t

han

t

h

e

collector

of

Q25

.

Wh

en

t

h

e

gating

or

triggeri

ng

waveform

level

drops

below

-

ΤΡ

36,

Q25

con

d

ucts

an

d

Q26

turns

off

.

T

h

is

switc

h

i

n

g

waveform

is

applie

d

to

t

he

b

ases

of

U

60A

a

n

d

U60

B

,

op

erating

as

α

differential

p

air

.

T

he

collector

of

U

60A

d

rives

U

60C

i

n α

casco

de

mo

d

e

of

o

p

eratio

n

.

T

he

collector

of

U

60C

drives

t

h

e

base

of

U

60D

w

h

ic

h

,

as an

emitter

followe

r

,

drives

the

i

np

ut

of

U70

B

.

This

gate

operates as αdual

i

np

ut

Sc

h

mitt

trigger

sha

p

er

.

Wh

en

t

h

e

emitter

of

U

60D

goes

to

about

4

.2

V

above

g

r

o

und,

p

i

n 7

of

U70

B

goes

h

ig

h

.

Wh

en

t

he

emitter

of

U

60D

d

ro

ps

to

about

3

.8

V,

p

in

7

of

U

70

B

drops

to

its

low

level

.

T

he

i

n

verti

n

g

out

p

ut

termi

n

al,

p

in

6,

is

always

in

t

he

op

p

osite state

from

p

i

n 7

.

P

ositive

fee

dback

for

t

h

is

p

ortio

n

of

t

he

Sc

h

mitt

is

p

rovided

by

R

72

.

If

t

he

unit

is

ma

n

ually

triggere

d

,

p

i

n 10

of

U

70

B

is

momentarily

co

n

necte

d

to

+-5

V

.

P

i

n

10 of

U

70

B

,

along

wit

h

R

75

a

nd

R

76

now

acts

as α

Sc

h

mitt

s h

ape

r

for

t

h

e

ma

n

ual

t

r

igger

.

T

h

is

actio

n h

ol

d

s

t

h

e

outp

u

t,

p

i

n

7,

h

ig

h

and

t

he

i

n

verti

ng

outp

ut,

p

in 6,

low

as

long

as

t

h

e

MAN

button

is

de

p

resse

d

.

REV

.

Α

,

ΜΑΥ

,

1976

Wh

en

t

he p

lus slo

p

e

is

selected

for

triggeri

ng

or

gati

n

g,

f-5

V

is

a

pp

lie

d

to

p

i

n

4

of

U

70A

.

T

h

is

gate

is

now

i

nh

ibited

an

d

t

he

sig

n

al

p

asses

t

hroug

h

U

70C

.

As

t

he outp

uts

of

U

70A

and

C

are

co

n

nected

toget

h

er,

α

h

ig

h

on

eit

h

er

outp

ut

overri

des

t

he low

.

P

in

13 of

U

70C

is

low

as

lo

n

g

as

t

he a

n

o

d

es

of

C

R

82

an

d

CR

84 are

low,

w

h

ic

h

occurs

w

hen

t

he

logic

circuitry

h

as

e

n

abled

t

he

i

n

p

ut

circuitry

.

Wh

en

t

he co n

trol

logic

is

set

to

d

isable

t

he

i

np

ut

circuitry,

t

he

anodes

of

t

hese d

iodes

are

raised to

+5

V

w

h

ic

h

disables

gates

U

70Aand

U

70C

.

P

in

12

of

U

70C

now

s

h

ifts

b

etween

t

he h

ig

h

and

low

state

corres

p

o

nd

i

ng

wit

h

t

h

e

input

gate

or

trigger

.

T

h

e

ouput

from

U

70C,

p

in

14,

is

p

assed

to

t

he

perio

d

circuitry

.

Α

h

ig

h

at

t h

e ou

tput

of

U

70C

turns

t

he

p

eriod

circuitry

off

and

α

low

starts

t

he

period

generator

.

T

R

IG'D/GAT

E

D

Lig

h

t

Circuitry

Trigge

r

ed

M

ode

Section

2--PG

508

Tra

n

sistors

0100,

Q102,

Q110

and

t

h

eir

associated

compone

n

ts

com

p

ose

t

he

circuitry

t

h

at

o

p

erates

t

he

f

r

ont

p

anel

TRIG'D/GAT

E

lig

h

t

emitting

d

io

de

.

T

he

p

air

Q100

a

n

d

Q102

form α modified

astable

multivibrator,

w

h

ile

Q110

o

p

erates

as α

voltage

source

.

Wh

en

t

h

e

output

of

U

70A

or

U

70C

is

h

ig

h

(perio

d

generator

off)

or

t

he

logic

circ

u

itry

h

as

in

h

ibite

d

t

h

e

i

nput

circuitry,

t

h

e

baseofQ100

is

h

ig

h

.

This

causes

t

he

base

of

Q102

to

be

low

t

hr

oug

h

R

106

.

T

he

collector

of

0102

is

now

h

ig

h

a

n

d

t

he

lig

h

t

emitti

ng d

io

de

is

off

.

Wh

en

t

he b

ase

of

Q100

goes

Ιοω

,

t

h

e

base

of

Q102

goes

h

ig

h

,

t

h

e

collector

goes

low a

n

d

t

h

e

lig

h

t

emitting

diode

illuminates

.

T

h

e

lig

h

t

emitting

d

iode

circuitry

follows

t

he

triggeri

n

g

gate up

to

about

α5

H

z

r

ate,

i

.e

.,

about

100

ms

on

a

nd

100

ms

off

.

At

faster

gati

ng

frequen

cies,

C106

i

nh

ibits

t

he

c

h

angi

ng

states of

t

h

is

circuitry

at

about

t

h

e

5 Hz

rate

.

In

t

he

triggere

d

mo

d

e

of

o

p

eratio

n

S200-2

is

closed

.

T

h

is

p

laces

α

h

ig

h

on

p

i

n

10 of

U

140

B

loc

k

i

ng p

i

n 7

h

ig

h

a

nd p

i

n 6 low

ir

r

espective

of

t

he

level

on

p

i

n

11

.

T

h

is

disa

b

les

t

h

e

p

eriod

ge

n

erato

r

.

P

i

n 15

of

U

140C

now

follows

p

in

4

of

U

140A

in

coi

n

cide

n

ce

wit

h

t

h

e

in

p

ut

triggering

signal

.

P

in

14

of

U

140C

drives

Q244

and

p

i

n

15

d

rives

Q240

.

T

h

e

outp

ut

from

t

he

collector

of

0240

is

i

n

p

h

ase

wit

h

t

h

e

trigger

or

gate

i

nput

sig

n

al

p

rovidi

n

g

t

he

trigger

outp

u

t,

an

d

t

he ph

ase

of

t

he

waveform

at

t

he

collector

of

Q244

is

i

n

verted

.

Th

eory

of

O

p

eration-PG

508

P

e

r

iod

Generator

'T

h

is

circuitry

generates

t

he

inter

n

al

perio

d

timing

wavefor

m

.

In

t

h

is

mode,

U

140

B

o

p

erates

as

an

astable

multivibrator

.

Wh

en

eit

h

er

i

n

p

u

t

of

U

140

B

is

h

ig

h

,

pin

7

is

h

ig

h

and

pin

6

is

low

.

T

he switched

ti

m

i

ng cap

acita

n

ces

a

r

e co nn

ected

from

pin

7

to

pi

n

11

.

T

h

ese

ca

p

acitors

are

switc

hed

by

t

h

e

p

erio

d

range

switc

h

.

T

h

e

p

erio

d

variable

control,

R

190,

varies

t

he

resistance

in

t

he n

egative

fee

d

bac

k

loop

.

To

start

t

he p

erio

d

cycle,

assume

pin

7

of

U

140

B

goes

h

ig

h

an

d

p

i

n

6

low

.

T

h

is

positive

step,

at

p

i

n

7, is

couple

d

t

h

roug

h

t

he

period

timi

ng ca

p

acito

r

to pi

n

11

.

As

t

he

ti

m

ing

ca

p

acitor

d

isc

h

arges

t

h

ro

u

g

h

t

he

resista

nces

con

n

ecte

d

from

pin

11 to

p

i

n

6,

t

he

voltage

at

p

i

n

11

d

ecays

at

α

rate

d

etermi

n

ed by

t

he

timi

ng ca

p

acitor

and

t

h

ese

resistances

.

Wh

en t

he

switc

h

ing

level

(ap-

proximately

4

V)

is

reach

ed,

p

i

n

7

goes

low

an

d p

in

6

goes

h

ig

h

.

T

he

negative

ste

p

,

at

p

i

n

7,

is

couple

d th

roug

h

t

he

timing

capacitor,

and a

pp

ears

at

p

i

n

11

.

T

he cap

acitor

now

ch

arges

t

hroug h

t

h

e

resista

n

ces

un

til

t

he

switc

h

i

ng

level

is

reac

h

ed,

and

t

h

e

p

eriod

cycle

re

p

eats

.

T

he

symmetry

a

dju

stme

n

t

com

p

ensates

for

t

he

bias

current

t

h

ro

ugh

p

in

11

.

Wh

e

n

t

h

e

PER

IOD

switc

h

is

i

n

any

p

osition

ot

h

er

t

han

ΕΧΤ

TRIG

(MAN),

switch

S200-2

is

ope

n

ed

.

T

h

is

lowers

pin

10

of

U

140

B

and

p

e

r

mits

t

h

e

p

eriod

generator

to

o

p

erate

du

ri

ng

t

h

e

exte

rn

al

gate

on

time

.

Duri

ng

t

h

e

time

of

t

h

e

exter

n

al

gati

ng

sig

n

al

p

ins

4

and

2

of

U

140A

are

low

.

P

i

n 3

is

h

ig

h

.

As

transistors

0150

a

nd

0160

form

α

comparator,

wit

h

t

h

eir

bases

con

n

ecte

d

to

p

i

ns

3

and

1

of

U

140A

res

p

ectively,

t

h

e

collector

of

Q150

is

low

causi

ng

t

he

e

m

itte

r

of

0175

to

be

low,

as

well

as

pi

n

11 of

U

140

B

.

Th

is

allows

t

h

e

p

eriod

generator

to

o

pe

r

ate

.

During

t

he

gate

d

off

time

t

h

is

action

reverses

.

P

i

n

11 of

U

140

B

rises

a

nd

i

nh

ibits

t

he

p

erio

d

generator

.

R

esisto

r

R

170

an

dR

165

a

dj

ust

t

h

e

loc

k up voltage

at

pi

n

11

of

U

140

B

so

t

h

at,

at

tur

n on,

t

h

e

first

perio

d

ge

n

erated

is

i

d

en

tical

in

time

wit

h

subse

quen

t

p

eriods

.

R

esistor

R

165

is

switche

d

i

n

to

t

he

ci

r

cuit

only

on

the20 ns

ra

n

ge

.

Com

p

one

n

ts

R

177

and

C177

forma

time constant

to

h

el

p

com

pen

sate

for

first

perio

d

erro

r

.

Delay

Ge

n

erator

T

h

is

circuitry

p

rovi

d

es

t

he

d

elay

for

d

elaye

d

or

paired

p

ulse

op

eratio

n

.

As

t

h

e

sig

n

al

from

t

h

e

p

eriod

generato

r

of

t

he

exte

r

n

al

t

r

igger

i

npu

t

goes

from

h

ig

h

to

low

at

p

i

n 7

of

U

270

B

,

p

in

3

goes

h

ig

h

.

T

h

is

causes

p

i

n 5

of

U

270A

to

go

h

ig

h a

n

d

p

i

n 2

low

.

P

i

n 13

of

U

270D

and p

i

n

9

of

U

300

B

go

low

.

P

in

15

of

U

270D

goes

h

ig

h

bu

t

pin

10

of

U

300

B

d

oes

n

ot

follow

u

ntil

about

10 ns

later,

d

ue

to

t

h

e

delaying

action

of

R

275

a

nd

C275

.

Wh

en p

i

n

9

of

U

300

B

goes

low

p

in

6

goes

h

ig

h

,

assuming

pin

11

isalready

low

.

Pin

6stays

2-2

h

ig

h un

til

p

i

n 10

goes

h

ig

has

descri

bed

above

.

T

h

is

action

p

rovides

t

h

e

d

elay

gen

erator

wit

h

about

α 10

n

s

trigger

pulse

un

der

all

input

co

n

ditio

n

s

.

T

he

positive-going

trigger

pu

lse,

at

p

i

n 5

of

U

300A,

causes

pin

3

to

go

low

and

pin

2

h

ig

h

.

P

ositive

feed

b

ac

k

th

roug

h

R

300

a

nd

C300

causes

pi

n

4

to

go

h

ig

h

.

T

h

e

low

at

t

he

base

of

Q320

tur

ns

Q320

off

.

T

he

emitter

of

Q320

goes

n

egative

at

α

rate

determined

b

y

t

h

e

timi

ng

ca

p

acitor

and

c

u

rrent

source

Q342,

wit

h

its

variable

emitte

r

resista

n

ces

.

As

t

he

emitter

of

Q320

goes

negative,

it

p

ulls

t

he

base

of

Q294

negative

w

h

ic

h

lowers

p

i

n 4

of

U

300A

.

Wh

en

pin

4

reac

hes

t

he

switc

h

ing

t

h

res

h

old

(~4

.0

V)

pi

n 2

goes

low

an

d

pin

3

h

ig

h

.

T

h

e

timing

ca

p

acito

r

is

now

d

isc

h

arged

t

hroug

h

Q320

.

T

he

monostable

d

elay

ge

n

erator

is

now

reset

for

t

he

n

ext

trigger

pulse

.

Transistor

0290

provides

a

consta

n

t

load

for

t

he

power

sup

p

lies

irres

p

ective of

t

he

curre

n

t

flowi

ng

t

h

roug

h

Q294

.

Compo

n

ents

R

304,

R

306

and

C304

provi

d

e α delay

line

for

t

he

CO

N

TRO

L

ER

R

OR

lig

h

t

.

T

he

ou

p

ut

from

t

hedelay

generator

is

co

nn

ecte

d

to

pin

13

of

U

3000

.

P

i

n

15 of

U

3000

is

h

ig

h

during

t

he

d

elay

time and

p

i

n 14

low

.

Gates

U

360

B

an

dD

p

rovide

α

positive-goi

ng

t

r

igger

at

pin

15

of

U

360D

w

h

e

n

t

he d

elay

time ends

.

Gates

U

360A

a

n

d

C

p

rovide

α

p

ositive-going

trigger

at

p

in

14

w

hen

t

he delay

time

starts

.

As

t

he

d

elay

time

starts,

p

in

4

of

U

360A

goes

low

as

does

p

in

11

of

U

360C

.

P

in

10

of

U

360C

is

low

as

t

he

anode

of

C

R

378

is

gro

un

d

ed

t

h

roug

h

t

h

e

UN

D

L

Y

switc

h

.

T

h

e

low

at

p

in

11

of

U

360C

allows

pin

14

to

go

h

ig

h

.

P

in

14

stays

h

ig

h

until

t

h

e

propagation

time

t

h

ro

u

g

h gate U

360A

an

d

t

h

e

delayi

ng

actio

n

of

8364

an

d

C366

allow

t

h

e

h

ig

h

ge

n

erated

i

n

U

360A,

from

pi

n

2,

to

reset

U

360C

t

hroug

h

p

i

n 10

.

T

h

is

causes

pin

14

to

retur

n

to

its

low

state

.

The

widt

h

of

t

h

e output

trigger

p

ulse

is

about 6 ns

.

To

obtain

t

h

e

delayed

trigger,

t

he an

ode

of

C

R

378

is

con

n

ecte

d

to

-

Ι

--5

V

d

isabling

gate U

360C

.

T

h

ea

n

ode

of

CR

382

is

grou

n

de

d throug

h the

DL

Yswitc

h

.

Gates

U

360

B

a

nd

U

360D

now

o

p

erate

in

exactly

t

he

same

ma

nner

as

U

360A

an d

C

.

Α

positive

trigger

p

ulse

a

pp

ears

on

pin

15

of

U

360D

w

hen

t

he

d

elay

time

e

nds

(pi

n

6

of

U

360

B

goes

from

h

ig

h

to

low)

.

In

t

h

e p

aired

pulse

mode

bot

h

gates

operate

.

Gate

U

360C

p

rovi

d

es α

positive-going

trigger

at

t

h

e

start

of

t

he d

elay time

a

nd

U

360D

α

p

ositive

trigger

at

t

h

e

end

of

t

h

e

d

elay

time

.

Duratio

n

Generator

T

h

is

circuitry

generates

t

he

d

uratio

n times

.

Gate

U

400

B

acce

p

ts

t

he d

elaye

d

or

u

n

delayed

positive triggers

from

t

he

d

elay

generator

.

T

he

result

is

α

p

ositive-going

pulse

at

p

i

n 5

or

U

400A

.

T

h

is

triggers

t

he d

uration

generator

w

h

ic

h operates

in

t

he

same

manner

as

t

hed

elay

generator

.

R

efer to

t

h

e

d

iscussio

n un

d

er

t

h

e

h

ea

d

ing

Delay

Ge

n

e

r

ator

for

α

d

escri

p

tio

n

of

t

he

d

uration

generator

o

p

eratio

n

.

Gate

U

4000

is

an

output

buffer

.

P

i

n

12

goes

h

ig

h

duri

n

g

t

h

e

p

ulse

d

uration

time

an

d

if

pin

13

is

low,

p

i

n 15

goes

h

ig

h

an

d

p

in

14

low

.

P

in

13

controls

U

4000

i

n

th

e

square

wave

a

n

d

exter

n

al

d

uration

mo

des

.

Duration

an

d

Delay

Co

n

trol

Error

L

ig

h

t

Circuitry

Th

is

circ

u

itry

illu

m

i

n

ates

t

he

CO

N

TRO

L

ERR

O

R

lig

h

t

w

he

n

t

he d

uration

or

delay times

a

r

e

greater

t

han

t

h

e

p

erio

d

s

of

t

h

eir

respective

triggers

.

T

he p

ositive

pulse

from

t

he

duratio

n

generator

is

fed

i

n

to

t

h

e

D

i

np

ut,

p

i

n

10,

of

U

480A

.

Th

e

cloc

k

enable

line

is

low

.

If

t

he

d

uration

time

is

set

so

t

h

at

α

trigger

p

u

lse

(connected

to

t

he

cloc

k

i

n)

for

t

h

e

next

duration

p

ulse

occurs

before

t

he output

of

t

h

e

d

uratio

n

ge

n

erator

goes

low,

t

he

h

ig

h

on

t

he

D

i

n

put,

pi

n

10 of

U

480A,

is

transferre

d

to

t

he

output,

p

i

n

1

.

T

h

is

h

ig

h

is

co

nnected

to

t

h

e

set

i

n

p

u

t,

p

i

n

5,

of

U

480

B

wh

ic

h

causes

t

h

e outp

ut,

pi

n

2,

of

U

480

B

to

go

h

ig

h

illuminating

the

error

lig

h

t

.

Wh

e

n

t

h

e

out

p

ut,

p

in

2,

of

U

480

B

goes

h

ig

h

,

t

he

inputs

to

U

480A

an

d

Β

are

disable

d

t

h

roug

h

t

h

e

cloc

k

enable

li

ne

p

reve

n

ti

ng

furt

h

er

trigger

in

p

uts

until

both

fli

p

flops

are

reset

.

Wh

en

th

e

output,

pin

2,

of

U

480

B

goes

a

nd

stays

h

ig

h

,

C487

starts

to

ch

arge

to

t

he

voltage

on

pi

n

2,

t

hroug h

R

490

.

T

h

is

ta

k

es a

pp

roximately

100

ms

.

Wh

e

n

t

he

reset

i

n

p

u

ts

to

U

480A

an

d

Β

,

p

i

ns 13 and

4,

reac

h

th

e

h

ig

h

level

(about

4

.0

V)

U

480A an

d

Β

are

reset

a

n

d

C487

d

isc

h

arges

t

hroug h

R

490

.

Wh

en

t

h

ese

reset

i

npu

ts

retur

n

to

t

he

low

level

both

fli

p

flo

ps are

rea

d

y

to

accept

triggers

and

t

h

e

error

cycle

is

rea

d

y

to

re

p

eat

.

If

t

he d

elay

time

is

set for

α time

greater

t

han

t

h

e

period

of

t

he

d

elay

triggers,

t

h

e

h

ig

h

on

pi

n 7

of

U

480

B

transfers

to

p

in

2

d

irectly,

an

d

th

e

lig

h

t

is

illuminate

d

.

R

eset

ta

kes

p

lace

in

t

he

same

m

anner

as described

above

.

Also

conn

ected

to

t

h

is

circuitry

is

α

line

from

t

h

e

tra

n

sitio

n

time board

wh

ic

h

also

lig

h

ts

t

he

CO

N

TRO

L

ERROR

lig

h

t

.

"T

he

CO

N

TRO

L

ERR

O

R

lig

h

t

is

also

illuminate

d

for

certai

n

i

m

pro

p

er

control

setti

ngs

.

F

ig

.

2-1

sh

ows

α

simplifie

d

sc

hematic

for

t

h

e

CO

N

T

R

O

L

ERR

O

R

i

n

d

icator

logic

an

d co

n

trol

settings

causi

ng

illumi

n

ation

.

V

ariable

Transition

Time

Circuitry

T

h

is

circuitry

controls

t

he

output

tra

n

sitio

n times

.

R

esistors

R

534

an

d

R

536

provide

equivale

n t

50

Ω

termi

n

a-

tio

n

im ped

a

nce

for

t

he

normal

(positive-going)

i

np

utfrom

t

he

duratio

n

generator

.

Also,

R

520

an

dR

522

p

rovi

d

e

an

ide

n

tical

termi

n

ation

impe

dan

ce

for

t

he

com

p

leme

n

t

i

np

ut

(negative-going)

fro

m

th

e

du

r

ation

ge

n

erator

.

T

h

ese

i

np

uts

d

rive

t

h

e

bases

of

Q525

a

n

d

Q530

.

Wh

en

t

he

in

p

ut

from

t

he

du

ratio

n

generator

is

h

ig

h

an

d

t

he

com

p

le-

ment

is

low,

t

he

collector

of

Q530

d

rops

from

groun

d

to

abo

u

t

--1/2

V

.

T

h

is

turns

Q565

on

an

d

Q560

off

.

T

h

e

ad

j

usta

b

le

co

n

sta

n

t

current

t

h

ro

ugh

Q545,

to

1-15 V,

is

now

passed

t

h

roug

h

R

578,

from

t

he

--

15

V

supply

.

Transistor

Q560

is

tu rn

ed

off

as

its

b

ase

is

connecte

d

to

groun

d

.

Ze

n

er

d

iodes

V

R620

an

dV

R630

lowerth

evoltage

from

t

h

e

b

ases

of

Q565

an

d

Q560

to

t

he

bases

of

Q625

an

d

Q630

by

about

7

.5

V

.

Tran

sisto

r

Q625

is

t

h

erefore

off

an

d

Q630

is

co

n

ducti

ng

.

Curre

n

t

flows from

--15

V

th

roug

h

αη

T

h

eory

of

O

p

eration---

P

G

508

adj

ustable

curre

n

t

source

Q635

an

d

t

hen

th

roug

h

Q630to

c

harge

t

he

particular

cap

acitor

d

etermine

d

b

y

t

h

e

tra

n

si-

tio

n time

selected

.

As

t

h

e cap

acitor

charges

t

hrough

α

co

n

sta

n

t

curren

t

so

u

rce,

t

h

e

j

unction

of

CR

584

an

d

C

R

600

goes

n

egative

at

α

li

near

rate

u

n

til

t

he

d

io

de

C

R

600

turns

on

.

T

h

is

diode

serves

as

t

h

e

n

egative

clamp

.

T

h

e

voltage

at

t

he

anode

of

C

R

600

is

set

by

R

615

t

hroug h

Q608

and

0600

.

T

h

e voltage

at

t

he

ju

nction

of

C

R

584

a

n

d

C

R

600

remains

low

for

t

he pulse

d

uration

.

At

t

he e

nd

of

t

he pulse d

uration

time,

t

h

e

collector

of

Q530

goes

p

ositive

.

Th

is

actio

n

tur

ns

Q565

off

a

nd

Q560

on

.

C

ur

re

n

t

from

t

h

e

--i-15

V

supply

flows

t

h

ro

ughconstant

current

source

0545,

t

h

e

n

th

roug

h

0560

raisi

n

g

t

he

j

un

ction

of

C

R

584

a

nd

CR

600

at

α

li

near

rate

d

etermine

d

by

t

h

e

capacitor

val

ue

an

d

t

he curren

t

available

.

T

he

j

un

ctio

n

of

C

R

584

and

CR

600

goes

p

ositive

u

ntil

C

R

584

turns

on

.

T

h

e

voltage

at

t h

e

cat

h

ode

of

C

R

584

is

set

by

R

570

t

hroug h

Q575

and

Q580

.

Tran

sisto

r

0625

is

tur

n

ed

on

,

an

d

Q630

off,

p

assi

ng cu

rrent

from

co n

sta

n

t

current

source

Q635

t

hroug

h

Q625,

C

R

604,

and

R

604

to

groun

d

.

T

h

e

lea

d

ing

a

nd

traili

ng

transitio

n

times

are

varie

d

indepen

d

ently

by

varying

t

h

e

a

m

ou n

t

of

curre

n

t

passing

t

h

ro

ugh co

n

sta

n

t

current

source

tra

n

sistors

0635

and

Q545

.

T

he

o

u

t

pu

t

waveform

at

t

he

j

un

ction

of

CR

584

and

CR

600

passes

to

t

he

gate

of

fet

Q680

.

This

fet

serves

as

α

source

follower

for

drivi

n

g

Q685

a

nd

Q690

.

T

hese

tran-

sistors

com

p

ose

α

linear

differe

n

tial

a

mp

lifier

.

T

he

clamp

levels

for

d

iodes

C

R

584

an

d

C

R

600

are

set

so

t

h

at

Q685

an

d

0690

are

slig

h

tly

overdrive

n

.

T

h

is

serves

to

r

emove

any

ri

n

gi

n

g

or ot

h

er

sig

n

al

irregularities

at

t

h

e

to

p

an

d

botto

m

of

t

h

e

waveform

.

Operatio

n

al

amplifier

U

665

p

rovi

d

es,

alo

ng

wit

h

Q660,

consta

n

t

curren

t

for

Q685

and

Q690

.

Transition

"rime

Control

Error

L

ig

h

t

Circuit

r

y

Th

is

circuitry

ill

u

minates

t

he

co

n

trol

er

r

or

lig

h

t

w

h

e

n

th

e

lea

d

ing

tra

n

sition

ti

m

e

is

greater

t

han

t

h

e p

ulse

du

ration

time,

or

w

h

en

t

he

traili

ng

tra

n

sitio

n

ti

m

e

is

greater

t

h

an

t

h

e

pulse

off

time

.

The

i

n

verted

sig

n

al

from

t

he

leading

an

d

traili

ng

ge

n

erator

a

pp

ears

at

t

he base

of

Q704

t

h

ro

u

g

h

fet

follower

Q700

.

Α

d

iffere

n

tial

amplifier

is

formed

by

Q704

an

d

Q706

.

T

he outpu

t

is

ta

k

en

from

t

he

collector

of

Q706

.

Tran

sistors

Q704

a

n

d

0706

are

over-

d

riven

to

reduce

t

he wi

nd

ow

of

comparisio

n

.

Duri

n

g

t

he

p

ulse

on

time,

t h

e

base

of

Q704

is

negativewith

res

p

ect

v

o

grou

nd

.

T

h

is

action

causes

t

h

e

collector

of

0706

to

also

go

negative,

d

riving

t

he

base

of

Q715,

an

emitter

follower

n

egative

.

T

h

e

emitter

of

Q715

is

co

nn

ecte

d

to

p

i

n

s

7

an

d

10,

t

he

D

in

p

ut

of

fli

p

flo

p

s U

720A

and

Β

.

T

he

waveforms

drivi

n

g

t

he

transitio

n

time

circuitry

are

also

ap

plie

d

to

gates

U

740A

and

Β

.

P

in

6

of

U

740

B

is

h

ig

h

during pu

lse

time

w

h

ile

p

i

n 4

of

U

740A

is

low

.

Th

ep

urpose

of

t

he

fo

u

r

gates

i

n

U

740

is

to

d

elay

t

h

e

signal

αρ

-

2-

3

T

h

eory

of

Operation--PG

508

DE

L

AY

proximately

t

he

same

amou

n

t

as

t

h e

circuitry

i

n

t h

e

variable

transition

time

ge

n

erator

.

The

p

ositive-going

waveform

from

pin

14 of

U

740C

is

fed

t

h roug h p

i

n

6

to

t h

e

cloc

k

input,

pin

6,

of

fli

p

flo

p U

720A

. -

The

n

egative-goi

n

g

out

p

ut

from

p

i

n

15

is

fe

d

to

t

h e

cloc

k

i

np

ut

pin

11,

of

fli

p

flop

U

720B

.

Flip

flo

p

U

720A

senses

t

he pulse

traili

n g

timi

ng

error

a

nd

U

720

B

,

t

he

p

ulse

lea

d

ing

timing

error

.

If

t

he

lea

d

i

n g

time

from the o

u

t

pu

t

of

t

h

e

variable

tra

n

sitio

n

ti

m

e gen

erator

is

slow

enoug

h

so

t

h

at

t

h

e

D

i

n put

of

U

720

B

has

n

ot

d

ro

p

pe

d

below

a

pp

roximately

t

h e

50°/

ο

p

oi

n

t,

w

hen

t

he

waveform

at

t

h e

cloc

k

in

p

ut

of

fli

p

flo

p

Switc

h

es

are

close

d

w

hen

cont

r

ols

are

in

t

he

labele

d

p

ositio

n

.

T

he

CO

NT

R

O

L

ERR

O

R

lig

h

t

ill

um

inates

w

h

en

t

he un

it

is

set

to

o

pe

r

ate

Dela

y

a

nd

S

qu

a

r

e

W

ave

Delay

an

d E

xter

n

al

D

u

ration

I

n

ternal

Pe

r

io

d

a

nd

Exter

n

al

D

u

ratio

n

I

n

te

rn

al

P

e

r

io

d

,

Sy

n

c

hr

on

o

us Gate a

ndS

qu

a

r

e

W

ave

E

xte

rn

al

T

r

igge

r

and

S

qu

a

r

e

W

ave

E

xte

rn

al

Trigge

r

and Synch

ro

nous Gate

u

nd

e r

t

he

followi

ng cond

itions

:

F

ig

.

2-1

.

Sim

p

lified

sc

h

ematic

fo

r

CONTRO

L

ER

RO

R

indicato

r

logic

wit

h con

trol

setti

n

gs

causi

ng

illuminatio

n

.

To

CO

N

TRO

L

E

R

RO

R

L

ig

h

t

Circ

u

it

U

720

B

(waveform

driving

t

h

e

tra

n

sition

time

board)

goes

p

ositive

(e

n

d

of

p

ulse),

t

he h

ig

h

on

D

input,

p

i

n

10,

tra

n

sfers

to

t

he out

p

ut,

p

i

n

15,

a

nd

t

h

e

CO

N

T

RO

L

ERRO

R

lamp

is

lit

.

Wh

en

p

in

15,

of

fli

p

flop

U

720

B

goes

h

ig

h

,

C734

sta

r

ts

to

ch

arge

t

h rough

R

728

.

Wh

en

t

he voltage

at

p

i

n 13

of

U

720

B

a

n d

p

in

5

of

U

720A

reac

h

es

t

h e

h

ig

h

level

(-4

.0

V),

both

fli

p

flops

are

reset

to

t

h

eir

initial

con

d

itio

n

s

and

t

h

e

CONTRO

L

ERROR

lig

h

t

goes

out

.

If

t

he

trailing

ti

m

e

of

t

h

e

pulse

is

slow

e

n

oug

h so

t

h

at

t

he

D

i

np

ut

of

fli

p

flop

U

720A

has not

reac

hed

t

he

h

ig

h

level

w

hen

t

he pulse

at

t

he

cloc

k

te

rm

i

n

al (p

i

n

6)

of

fli

p

flo

p U

720A

goes

h

ig

h

(lea

d

ing

p

o

r

tio

n

of

t

he

n

ext p

ulse

drivi

ng

t

he

tra

n

sitio

n

circuitry)

t

he 0

termi

n

al,

p

i

n

3, of

fli

p

flo

p

U

720A

goes

h

ig

h

.

T

h

is

h

ig

h

is

connected

to

t

he

set

termi

n

al,

p

i

n

12,

of

U

720

B

causing

t

h

e

1

terminal

of

U

720

B

to

go

h

ig

h

illuminating

t

he

CO

NTR

O

L

ERR

O

R

lig

h

t

.

T

he on time

an

d

reset

fort

h

is

error

i

n

dicati

n

g

mode

now

p

rocee

ds

as

previously

d

escribed

.

L

evel

Co

n

trol

M

ulti

p

lier

T

h

is

circuitry

p

rovides

i

n

de

pe

n

den

t

to

p

a

n

d

bottom

level

co

n

trol

of

t

h

e

out

p

ut

p

ulse

by

controlling

t

he

am

p

litu

d

e

and

offset

of

t

h

e

d

rive

sig

n

al

to

t

h

e

li

near

outp

u

t

am

p

lifier

.

Also

i

n

clu

d

ed

is

circuitry

to

accom

p

lis

h

t

he

n

ormal

com

p

leme

n

t

functio

n

a

nd

t

he p

reset

fu

n

ction

.

Co

n

t

r

ol

voltage

clam

p

s

to

e

n

sure

t

h

e

out

p

ut

amplifier

is

n

ot

over d

rive

n

are

also

p

rovi

ded

.

Am

p

litu

d

e

co n

trol

of

t

h

e

sig

n

al

occurs

i

n

t

h

e a

n

alog

multi

p

lier,

U

850

.

T

he

p

ulse

sig

n

al

p

rovi

des

t

h

e

Χ

i

np

ut,

and

th

e

level

control

voltages

p

rovide

t

he

Υ

in

p

ut

.

T

he

Χ

-

Υ

p

roduct

of

t

h

ese

i

np

uts

is

co

n

verte

d

to

α

d

rive

curren

t

for

t

he outp

ut

am

p

lifier

.

I

np

ut

and

com

p

lement

p

ulses

from

t

he

varia

b

le

tra

n

si-

tion

time gen

erator

are a

pp

lied

to

t

h

e

bases

of

Q825

and

Q840

.

T

h

ese

tra

n

sistors

form

α

d

iffere

n

tial

am

p

lifie

r

,

su

pp

lied

by co

n

stant

curren

t

source

U

800

B

an

d

Q820

.

Α

p

ositive-going

sig

n

al

at

t

he

base

of

Q825,

wit

h

t

he

complementary

(negative-goi

n

g)

sig

n

al at

t

h

e

base

of

Q840

causes

t

he

sig

n

al

curren

tat

p

i

n

11

of

t

he

multiplierto

go

negative

an

d

t

h

e

signal

current

at

pin

12

to

go

positive

.

Wh

en

t

h

e

pulse

p

olarity

reverses,

at

t

h

e

b

ases

of

0825

an d

Q840,

t

he

sig

n

al

curre

n

t

also reverses

polarity

at

pins

11

a

n

d

12

.

T

h

e

difference

between

t h

e

currents

at

p

ins

11

an d

12

corres

p

o

nd

s

to

t

h

e

Χ

sig

n

al

i

np

ut

for

t

h

e

multi

p

lier

.

T

he

total

curren

t

flowing from

pins

2

an

d 3

of

U

850

is

essentially

eq

ual

to

t

he current

req

u

ire

d by

t

h

e

constant

currentsource,

U

895A

an

d

Q900

.

H

owever,

t

he

d

ifference

in

currents

between

t

hese

pins

corresponds

to

t

he

Υ

input

signal for

t

h

e

multiplier

.

T

he

am

p

litu

d

e

differe

nce

of

t

h

ese

curren

ts is

con

t

r

olle

d

by U

895

B

.

This

is

α

do

differential

am

p

lifier

w

h

ic

h

am

p

lifies

t

h

e

differe

n

ce

betwee

n

t

h

e

h

ig

h

&

low

level

control

voltages

to

prod uce

t

h

eΥ

i

np

ut

sig

n

al

.

Gain

ad

j

ust

m

e

n

t

for

t

h

eΥ

input

sig

n

al is

provide

d

b

yR

885

.

T

he h

ig

h a

nd

low

level

co

n

trol

voltages

a

r

e

d

etermine

d

by

t

h

eir

respective

front

panel

co

n

trols,

R

770

B

an

d

R

770A

.

If

t

he

preset

function

is

selecte

d

,

t

he

preset

h

ig

h an

d

preset

low

potentio

m

eters,

R

775

and

R

785,

p

rovi

de

t

he

T

h

eory

of

Operation--PG

508

co

n

trol

voltages

.

T

h

esevoltages

are

buffere

d by u

n

ity

gai

n

am

p

lifiers

U

780A

a

nd

U

780

B

.

B

ot

h

co

n

trol

voltages

ra

n

ge

betwee

n

0

a

nd

-

Ι

--5

.2

V

.

Wh

en

t

h

e

co n

trol

voltages

a

r

e

eq

ual,

t

he

Υ

i

nput

is

zero

an

d

t

he

m

ultiplier

sig

n

al

out

p

ut

(X-Y)

e

qu

als

zero

.

Α

differe

n

ce of

-42

.6

V

b

etwee

n

t

heh

ig

h

a

nd

low

level

co

n

trol

voltages

correspo

n

ds

to

maximum

out

p

ut

am

p

litu

de

from

t

h

e

p

ulse

gen

erator

.

T

he

n

ormal

complement

switc

h

inverts

t

he

level

co

n

trol

voltage

i

n

p

uts

to

differential

am

p

lifier

U

895

B

.

H

owever,

si

nce

t

he

differe

nce

betwee

n

t

h

e

voltages

is

un

c

h

ange

d

,

t

he

control voltage

i

np

ut

sig

n

al

h

as

co

n

sta

n

t

amplitu

d

e,

but

reverses

polarity

.

T

h

is

com

p

lements

t

h

e

pulse

generator

outpu

t

.

T

h

e

normal

com

p

leme

n

t

bala

nce ad

-

j

ustment,

R

910,

ensures

t

h

at

t

he

Υ

multiplier

inp

u

t

respon

ds

equally

to

ch

anges

in

eit

h

er

t

h

e

h

ig

h

or

low

level

control

voltages

.

T

h

e

signal

current

at

p

ins

5

and

6

of

U

850

is

t

he pu

lse

signal

.

Since

Q845,

in

con

j

un

ctio

n

wit

h

U

800

B

,

p

rovides

α

co

n

sta

n

t

current

si

nk

,

t

he

cur

r

e

n

t

t

hr

oug

h

R

954,

from

t

h

e

emitter

of

commo

n

base

stage

Q954,

also

contains

signal

cu

r

re

n

t

variations

.

T

h

e

cur

r

en

t

d

rive

r

for

t

he outp

ut

amplifier

is

Q954

.

T

h

e

sig

n

al

curren

ts

i

n

to

p

i

n

s

8a

nd 9

of

U

850

also

con

tai

n

t

h

e

p

ulse

signal

.

H

owever

con

sta

n

t

curren

t

si

nk

R

847,

an

d

commo

n b

ase

stage

Q950

a

r

e

inclu

d

e

d only as α

bala

ncing

t

h

ermal

loa

d

for

t

h

e

mul-

ti

p

lier

.

To

obtai

n

i

n

depe

ndent

co

n

trol

of

t

h

e

output

p

ulse

h

ig

h

an

d

low

levels,

t

h

e

co n

trol

voltages

are

average

d

by

resistor

n

etwor

k

R

914,

R

915,

R

918

a

nd

R

920

.

H

ig

h

a

nd

L

ow

trac

k

i

ng

potentimeters,

R

915

an

d

R

920,

are

a

d

-

j

ustable

to

provi

d

e

minimum

interaction

betwee

n p

ulse

levels

.

T

he

d

o

voltage

from

t

h

is

n

etwor

k

,

along

wit

h

t

he

voltage

from

t

h

e

offset

ad

j

ustment

R

925,

is

summe

d

an

d

inverte

d

by

U

930A

.

U

930

B

proves

furt

h

er

gain

an

d

level

s

h

ifting

an

d

, i

n

con

j

unction

wit

h

Q945,

serves

as

α

level

controlle

d

offset

generator

.

Α

d

o

current

sou

r

ce

to

t

he

collector

of

0954

is

provi

de

d

by

Q945

.

T

h

e

collector

of

Q954

is

t

he

virt

u

al

ground

inp

u

t

to

t

h

eo

u

tput

amplifier

.

Wh

en

t

he

h

ig

h a

nd

low

level

control

potentiometers

are

both

at

mid

ra

n

ge

(-42

.6

V

zero

out

pu

t)

Q945

sources

all

t

h

e

quiescent

bias

current

required

b

y

Q954,

w

h

ic

h

is

a

pp

roximately

15

m

A

.

T

h

erefore,

t

here

is

no

curre

n

t

d

rive

to

t

h

e

outp

ut

am

p

lifier

t

h

roug h

R

975

or

R

1055

.

If

t

he

h

ig

h

level

control

is

t

urned

fully

cw(maximum

o

u

t

put),

t

h

e

low

level

control

voltage

remains

at

+2

.6

V

.

T

h

e

h

ig

h

level

control

voltage

i

n

creases

to

+-5

.2

V

.

T

h

is

causes

t

h

e

voltage output

of

U

930A

to

decrease,

causi

ng

t

he

offset

generator

U

930

B

a

nd

Q945

to

sou

r

ce

ap

p

roximately

20

mA

.

T

h

is is

an

i

ncrease

of

5

mA

.

T

h

is

d

iffere

nce

i

n co n

trol

voltage

setti

ngs

also

causes

maximum

d

ifference

in

t

he

con

trol

voltage

i

np

ut

sig

n

al to

t

he

multiplier

.

This

action

also

causes

10

mA

p

ea

k

to

peak

sig

n

al

curren

t

variations

in

t

he

collector

current

of

Q954

.

Si

nce

t

he

sig

n

al

curren

t

T

h

eo

r

y of

Operation--PG

508

variatio

ns and do

offset

curren

ts

are

summed

at

t

he

collectors

of

Q945

an d

Q954,

t

he

out

p

ut

p

ulse

h

ig

h

level

ch

anges

to

maximu

r

n voltage

a

nd

t

he low

level

re

m

ai

ns

at

0

V

.

It

follows

that

any

p

ositive

increase

in

eit

herthe

h

ig

h

or

low

level

co

n

trol

voltages

causes

an

i

n

crease

in

t

he

do

offset

cu

rrent

.

Α

d

ecrease

i

n

eit

h

er

control

voltage

causes

α

d

ecrease

in

offset

current

.

However,

sig

n

al

cu

rr

ent

variations

res

p

o

nd only

to

d

ifferences

b

etwee

n

t

h

ese

control

voltages

.

'T

he

la

r

ger

t

he

voltage

differe

n

ce,

t

he

larger

t

he

signal

curren

t

am

p

lit

u

de

i

n

to

t

he out

p

ut

amplifier

.

Since

t

h

e

dy

n

amic

range

of

t

h

e

p

ulse

ge n

erator

output

is

4

-

or

- 20

V,

a

nd

t

he

maximum

am

p

lit

ud

e

is

only

20

V

pea

k

to

pea

k

,

clam

p

ing

circuits

areprovided

to

preven

t

t

h

e

differe

nce b

etween

t

he

h

ig

h and

low

level

control

voltages

f

r

om

excee

d

ing

+2

.6

V,

w

h

ic

h corresp

on

d

s

to

maximum

outpu

t

.

Α

clampi

n

g

circ

u

it

also

p

revents

t

he

h

ig

h

level

from

becoming

less

t

h

an

t

h

e

low

level

co

n

trol

voltage

.

"T

he

level

control

unity

gai

n

am

p

lifiers

U

780A

an

d

U

780

B

con

tai

n

α

precision

d

io

d

e

clam

p

com

p

osed

of

C

R

782,

C

R

790,

R

780,

an

dR

782

.

Si

nce

t

h

e

feed

back

for

U

780A

is

ta

ken

from

the cath

od

e

of

C

R

790,

t

he

voltage

at

t

he

ju

nctio

n

of

C

R

782

a

nd

C

R

790

is

eq

ual

to

t

h

e

low

level

control voltage

plus

o

ne d

iode

dro

p

(C

R

790)

.

If

t

h

e

h

ig

h

level

attempts

to

d

ecrease

below

t

h

e

low

level

or

attempts

to

i

n

crease

ab

ove

t

h

e

h

ig

h

level

co n

trol

voltage,

C

R

782

co

n

ducts

clampi

ng

t

he

h

ig

h

level

at

t

h

e

low

level

voltage

.

Cur

r

en

t

limiting

for

U

780

B

,

du

ri

n

g

clam

p

ing,

is

p

rovi

d

e

d

by R

780

.

U

800A

is

also

configured

as α p

recisio

n

clamping

circuit

.

T

he

o

u

tput

at pi

n

1

is

eq

ual

to

t

he low

level

control

voltage

pl

us 2

.6

Vp

l

u

s

o

ne d

iode

dro

p

.

T

h

e

r

efore,

if

t

he

h

ig

h

level

voltage

atte

m

pts

to

excee

d

t

h

e

low

level

plus

2

.6

volts,

or

t

he

low

level

is

d

ecreased

m

ore

t

h

a

n 2

.6

Vb

elow

t

h

e

h

ig

h

level,

C

R

805

cond

ucts

an

d

t

h

e

h

ig

h

level

is

clamped

at

t

he

low

level

co

n

trol

voltage

p

lus

2

.6

volts

.

Th

e

low

level

co n

t

r

ol

always

overri

des

t

he

h

ig

h

level

control

.

Cu

r

re

n

t

limiti

ng

for

U

780

B

,

duri

n

g

cla

m

ping,

is

provi

de

d

by

R

780

.

Output

Am

plifier

Th

e

p

ositive

and n

egative

d

o

voltages

for

t

h

is

am

p

lifie

r

are

p

rovided

by

dual

p

ower

supplies

w

h

ic

h

trac

k

t

h

e

h

ig

h

a

n

d

low

level

co

n

trol

voltages

.

T

h

ese

trac

king su

p

plies

ensure

t

h

at

t

he

p

ositive

pote n

tial is

at

least

6

V

above

t

he

outp

u

t

pu

lse

h

ig

h

level

a

nd

t

he

n

egative

p

ote

n

tial

is

at

least

6

volts

b

elow

t

he out

p

ut

p

ulse

low

level

.

'T

h

is

ar

r

angeme

n

t

e

nables

t

h

e

p

ulse

ge

ne

r

ator

to

provi

de α40

V

dy

n

amic

range,

wit

h α 20

V

p

ea

k

to

p

ea

k

maxim

u

m

output

pu

lse,

w

h

ile

maintaining

min

imum

p

owe

r

d

issipation

an

d

2-

6

voltage

re

q

uirements

for

t

h

e

amplifier

tra

n

sistors

.

T

h

e

ra

nge

of

t

he

p

ositive

trac

k

i

ng

supply

is

-

Ι

-6

to

-

Ι

-26

V,

wit

h

α

-6

to

---26

V

ra

nge

for

t

h

e

negative

supply

.

Th

e

outp

ut

circuit

functio

n

s

as α

linear

cu

r

re

n

t

drive

n

operational

am

p

lifier

wit

h

α

closed

loop

transresistance

gai

n

of

2

V

/mA

.

N

egative

feedbac

k

t

hroug

h

R

1042

to

t

he

i

n

p

u

t

no

de

(collectors

of

Q945

and

Q954)

causes

α

virt

u

ral

g

r

ou

n

d

at

t

he

i

np

ut

.

Α

10

mA

p

eak

to

p

ea

k

input

signal

creates

α

20

V

pea

k

to

pea

k

outp

ut

p

ulse

(o

pen

circuit)

.

Si

nce

t

he out

p

ut

a

m

plifier

is

α co

m

plementary

circuit,

only

t

he

op

eratio

n

of

one

side

will

b

e

explaine

d

.

F

or

α p

ositive-going

ou

tput pulse,

cur

r

e

n

t

is

drive

n

i

n

to

t

he

in

p

u

t

no

d

e

.

"This

action

causes

an

i

ncrease

i

n

base

curren

t

to

Q975

w

h

ic

h

d

ecreases

t

h

e

b

ase

d

rive

to

Q980

.

Α

casco

d

e

circuit

is

formed

by

Q980

an

d

Q990,

wit

h

R

985

an

d L

980

servi

ng as α co

n

sta

n

t

current

so urce

to

t

he

commo

n

collector-emitter

connection

.

'T

h

erefore,

w

hen

t

he base d

rive

to

0980

is

decreased,

t

h

e

current

in

Q990

i

n

creases

.

(T

he constan

t

curren

t

source

su

pplies

ap-

proximately

60

mA

w

h

ic

h

,

wit

h

no

signal,

is

e

qu

ally

d

ivi

de

d

between

Q980

an

d

Q990

.)

Anot

he

r

constan

t

cur

r

e

n

t

source,

Q1000,

causes

α 2

.0

V

d

ro

p

across

R

1002

.

T

he

emitter

follower,

Q995,

buffers

t

h

is

p

otential

and

p

rovides

α voltage

source

for

t

he base

of

t

he

cascode

transistor,

Q990

.

An

i

n

creasi

ng curren

t

t

h

roug h

0990

i

n

creases

t

he b

ase

curren

t

from

t

he

out

p

ut

parallel

emitter

followers,

Q1010

an

d

Q1015

.

T

h

e

emitters

of

t

h

ese

tra

n

sistors

drive

t

h

e

out

p

ut

positive

t

hroug h

α

networ

k

of

resisto

r

s a

n

d

ca

p

acitors

.

Compone

n

ts

R

1020,

R

1024,

and

C1024,

i

n

t

h

is

n

etwor

k

,

are

ad

j

ustable

to

provi

d

e

an

i

n

ter

n

al

resistive

50

Ω

te

r

mi n

atio

n

for

t

he out

p

ut

.

N

etwor

k

C1048

an

d

R

1048,

wit

h p

ote

ntiometer

R

1050,

p

rovides

tra

n

sie

n

t

res

p

o

nse

p

ea

k

i

n

g

for

t

he

am

p

lifier

.

Eq

uivale

n

t

biasi

ng

for

t

h

e

complementary

outp

ut

emitter

followers

is

p

rovided by

C

R

990,

R

990,

and

C

R

992

.

W

it

h zero

out

p

ut,

t

h

e

q

uiesce

n

t

current

in

eac

h output

follower

is

a

pp

roximately

20

mA

.

T

he

o

u

tput

potential

is

availa

b

le

at

t

he

rea

r

i

n

terface

connector,

pin

25A,

for

mo

n

itori

n

g

t

he

out

p

ut

am

p

litude

.

P

ower

Supply

-

The

-1-11

.5

Vd

c from

t

he main

frame

p

rovi

des

t

h

e

raw

su

pp

ly

voltage

for

t

he

series

regulate

d

+5

.2

Vd

c

su

pp

ly

.

T

h

e

precisio

n

voltage

regulator,

U

1210,

i

n

clu

des

α

temperature

compe

n

sate

d voltage

refe

r

ence

su

p

ply

at

p

i

n

6

.

T

he

+5

.2

V

p

oten

tiometer,

R

1210,

wit

h

t

h

e

voltage

divider

R

1209

and

R

1211 p

rovides

t

he reference

in

p

ut

to

t

h

e

non-inverting

i

np

ut,

pi

n 5

.

T

h

e

output

voltage

is

applie

d

to

t

he

i

n

verting

i

np

ut,

pi

n

4,

t

h

roug h

R

1217

.

Se

n

si

n

g

d

ifferences

i

n

t

he

two

i

nput

pote

n

tials,

t

he

regulator

amplifier

p

rovides

b

ase

cu

rrent

drive

f

r

om

p

i

n

10

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Tektronix PG 508 User manual

Brand: Tektronix

Model: PG 508

Category: Microphone accessories

Type: User manual

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