Document Number: 316704-001
Intel
®
Core
TM
2 Duo processor
and Mobile Intel
®
GME965
Express Chipset
Development Kit User Manual
June 2007
2 316704-001 / Development Kit User’s Manual
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR
IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT
AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY
WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL
PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY,
OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended
for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Intel Corporation may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights
that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide
any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual
property rights.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel
reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from
future changes to them.
Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor
family, not across different processor families. See http://www.intel.com/products/processor_number
for details.
The Intel
®
Core
TM
2 Duo processor and Mobile Intel
®
GME965 Express Chipset may contain design defects or errors known as
errata which may cause the product to deviate from published specifications. Current characterized errata are available on
request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an order number and are referenced in this document, or other Intel literature may be obtained
by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com
.
BunnyPeople, Celeron, Celeron Inside, Centrino, Centrino logo, Core Inside, Dialogic, FlashFile, i960, InstantIP, Intel, Intel logo,
Intel386, Intel486, Intel740, IntelDX2, IntelDX4, IntelSX2, Intel Core, Intel Inside, Intel Inside logo, Intel. Leap ahead., Intel.
Leap ahead. logo, Intel NetBurst, Intel NetMerge, Intel NetStructure, Intel SingleDriver, Intel SpeedStep, Intel StrataFlash, Intel
Viiv, Intel vPro, Intel XScale, IPLink, Itanium, Itanium Inside, MCS, MMX, Oplus, OverDrive, PDCharm, Pentium, Pentium Inside,
skoool, Sound Mark, The Journey Inside, VTune, Xeon, and Xeon Inside are trademarks or registered trademarks of Intel
Corporation or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2007, Intel Corporation. All Rights Reserved.
316704-001 / Development Kit User’s Manual 3
Contents
1 About This Manual ............................................................................................6
1.1 Content Overview...................................................................................6
1.2 Text Conventions ...................................................................................6
1.3 Glossary of Terms and Acronyms..............................................................8
1.4 Support Options...................................................................................13
1.4.1 Electronic Support Systems ......................................................13
1.4.2 Additional Technical Support .....................................................13
1.5 Product Literature.................................................................................13
1.6 Related Documents...............................................................................14
2 Getting Started............................................................................................... 15
2.1 Overview ............................................................................................ 15
2.1.1 Development Board Features ....................................................15
2.2 Included Hardware and Documentation ...................................................17
2.3 Software Key Features ..........................................................................17
2.3.1 AMI BIOS............................................................................... 18
2.4 Before You Begin.................................................................................. 18
2.5 Setting Up the Development Board .........................................................20
2.6 Configuring the BIOS ............................................................................22
3 Theory of Operation ........................................................................................ 24
3.1 Block Diagram .....................................................................................24
3.2 Mechanical Form Factor.........................................................................24
3.3 Thermal Management ...........................................................................25
3.4 System Features and Operation..............................................................25
3.4.1 Mobile Intel
®
GME965 GMCH..................................................... 25
3.4.2 ICH8-M..................................................................................27
3.4.3 POST Code Debugger...............................................................31
3.5 Clock Generation..................................................................................31
3.6 Power Management States..................................................................... 31
3.7 Power Measurement Support..................................................................33
4 Hardware Reference ........................................................................................ 39
4.1 Primary Features..................................................................................39
4.2 Back Panel Connectors ..........................................................................41
4.2.1 TV-Out D-Connector ................................................................42
4.3 Configuration Settings...........................................................................43
4.4 Power On and Reset Buttons ..................................................................47
4.5 LEDs ..................................................................................................48
4.6 Other Headers, Slots and Sockets ...........................................................49
4.6.1 H8 Programming Headers.........................................................49
4.6.2 Expansion Slots and Sockets.....................................................50
Appendix A . Heatsink Installation Instructions ....................................................................64
4 316704-001 / Development Kit User’s Manual
Figures
Figure 1. Development Board Block Diagram.......................................................24
Figure 2. Development Board Component Locations ............................................. 39
Figure 3. Back Panel Connector Locations ...........................................................42
Figure 4. D-Connector to Component Video Cable................................................43
Figure 5. D-Connector to Composite Video Cable .................................................43
Figure 6. D-Connector to S-Video Cable ............................................................. 43
Figure 7. Configuration Jumper and Switch Locations ...........................................44
Figure 8. LED Locations ...................................................................................48
Figure 9. Heatsink and Backplate ......................................................................64
Figure 10. Backplate Pins .................................................................................65
Figure 11. Applying the Thermal Grease .............................................................66
Figure 12. Squeezing Activation Arm..................................................................66
Figure 13. Installing the Heatsink ...................................................................... 67
Figure 14. Plugging in the Fan ..........................................................................68
Figure 15. Completed Assembly ........................................................................68
Tables
Table 1. Text Conventions ..................................................................................7
Table 2. Terms and Acronyms.............................................................................8
Table 3. Acronyms .........................................................................................10
Table 4. Intel Literature Centers........................................................................ 13
Table 5. Related Documents .............................................................................14
Table 6. Development Board feature Set Summary ..............................................15
Table 7. BIOS Location Strapping Options........................................................... 30
Table 8. Primary System Clocks ........................................................................31
Table 9. Power Management States ...................................................................32
Table 10. Power Management M-States ..............................................................32
Table 11. Sleep Signals and M-State Definition.................................................... 33
Table 12. Development Board Voltage Rails ........................................................ 34
Table 13. Development Board Component Location Legend ...................................40
Table 14. Back Panel Connector Definitions.........................................................42
Table 15. Supported Configuration Jumper/Switch Settings...................................44
Table 16. LED Functions...................................................................................48
Table 17. Expansion Slots and Sockets...............................................................50
Table 18. PCI Express* (x16) Pinout (J6B2) ........................................................51
Table 19. ADD2 Slot (J6B2).............................................................................. 54
Table 20. MEC Slot (J6B2)................................................................................57
Table 21. PCI Express* (x1) Pinout (J6B1, J7B1, J8B4).........................................60
Table 22. IDE Connector ..................................................................................60
Table 23. SATA Port 0 ‘Direct Connect’ Connector Pinout (J8J1) .............................61
Table 24. SATA Ports 1 and 2 ‘Cable Connect’ Connector Pinout (J7J3, J7H1)...........61
Table 25. SATA Power Connection (J7H2) ...........................................................62
Table 26. Fan Connectors (J2B3, J2C1) ..............................................................62
Table 27. Fan Connector (J2F1) ........................................................................62
Table 28. Front Panel Connector........................................................................62
Table 29. USB Headers ....................................................................................63
316704-001 / Development Kit User’s Manual 5
Revision History
Document
Number
Revision
Number
Description Revision Date
316704 001 Initial public release. June 2007
§
About This Manual
6 316704-001 / Development Kit User’s Manual
1 About This Manual
This user’s manual describes the use of the Intel
®
Core
TM
2 Duo processor and Mobile
Intel
®
GME965 Express Chipset development kit. This manual has been written for
OEMs, system evaluators, and embedded system developers. This document defines
all jumpers, headers, LED functions, and their locations on the development board,
along with subsystem features and POST codes. This manual assumes basic familiarity
in the fundamental concepts involved with installing and configuring hardware for a
personal computer system.
For the latest information about the Intel
®
Core
TM
2 Duo processor and Mobile Intel
®
GME965 Express Chipset Development Kit, visit:
http://developer.intel.com/design/intarch/devkits/index.htm
For design documents related to this platform please visit:
Processor: http://developer.intel.com/design/intarch/core2duo/tech_docs.htm
Chipset: http://www.intel.com/products/embedded/chipsets.htm
1.1 Content Overview
Chapter 1.0, “About This Manual” — This chapter contains a description of conventions
used in this manual. The last few sections explain how to obtain literature and contact
customer support.
Chapter 2.0, “Getting Started”— Provides complete instructions on how to configure
the development board and processor assembly by setting jumpers, connecting
peripherals and providing power.
Chapter 3.0, “Theory of Operation” — This chapter provides information on the system
design.
Chapter 4.0, “Hardware Reference”— This chapter provides a description of jumper
settings and functions, development board debug capabilities, and pinout information
for connectors.
Appendix A, “Heatsink Installation Instructions” gives detailed installation instructions
for the Intel
®
Core
TM
2 Duo processor heatsink.
1.2 Text Conventions
The notations listed in Table 1 may be used throughout this manual.
About This Manual
316704-001 / Development Kit User’s Manual 7
Table 1. Text Conventions
Notation Definition
# The pound symbol (#) appended to a signal name indicates that the signal
is active low. (e.g., PRSNT1#)
Variables Variables are shown in italics. Variables must be replaced with correct
values.
Instructions Instruction mnemonics are shown in uppercase. When you are
programming, instructions are not case-sensitive. You may use either
uppercase or lowercase.
Numbers Hexadecimal numbers are represented by a string of hexadecimal digits
followed by the character H. A zero prefix is added to numbers that begin
with A through F. (For example, FF is shown as 0FFH.) Decimal and binary
numbers are represented by their customary notations. (That is, 255 is a
decimal number and 1111 is a binary number. In some cases, the letter B
is added for clarity.)
Units of Measure
A
GByte
KByte
KΩ
mA
MByte
MHz
ms
mW
ns
pF
W
V
µA
µF
µs
µW
The following abbreviations are used to represent units of measure:
amps, amperes
gigabytes
kilobytes
kilo-ohms
milliamps, milliamperes
megabytes
megahertz
milliseconds
milliwatts
nanoseconds
picofarads
watts
volts
microamps, microamperes
microfarads
microseconds
microwatts
Signal Names Signal names are shown in uppercase. When several signals share a
common name, an individual signal is represented by the signal name
followed by a number, while the group is represented by the signal name
followed by a variable (n). For example, the lower chip-select signals are
named CS0#, CS1#, CS2#, and so on; they are collectively called CSn#.
A pound symbol (#) appended to a signal name identifies an active-low
signal. Port pins are represented by the port abbreviation, a period, and
the pin number (e.g., P1.0).
About This Manual
8 316704-001 / Development Kit User’s Manual
1.3 Glossary of Terms and Acronyms
Table 2 defines conventions and terminology used throughout this document.
Table 2. Terms and Acronyms
Term/Acronym Definition
Aggressor A network that transmits a coupled signal to another network.
Anti-etch Any plane-split, void or cutout in a VCC or GND plane.
Assisted Gunning
Transceiver Logic+
The front-side bus uses a bus technology called AGTL+, or Assisted
Gunning Transceiver Logic. AGTL+ buffers are open-drain, and require
pull-up resistors to provide the high logic level and termination. AGTL+
output buffers differ from GTL+ buffers with the addition of an active
pMOS pull-up transistor to assist the pull-up resistors during the first clock
of a low-to-high voltage transition.
Asynchronous
GTL+
The processor does not utilize CMOS voltage levels on any signals that
connect to the processor. As a result, legacy input signals such as A20M#,
IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PWRGOOD, SMI#, SLP#, and
STPCLK# utilize GTL+ input buffers. Legacy output signals (FERR# and
IERR#) and non-AGTL+ signals (THERMTRIP# and PROCHOT#) also
utilize GTL+ output buffers. All of these signals follow the same DC
requirements as AGTL+ signals, however the outputs are not actively
driven high (during a logical 0 to 1 transition) by the processor (the major
difference between GTL+ and AGTL+). These signals do not have setup or
hold time specifications in relation to BCLK[1:0], and are therefore
referred to as “Asynchronous GTL+ Signals”. However, all of the
Asynchronous GTL+ signals are required to be asserted for at least two
BCLKs in order for the processor to recognize them.
Bus Agent A component or group of components that, when combined, represent a
single load on the AGTL+ bus.
Crosstalk The reception on a victim network of a signal imposed by aggressor
network(s) through inductive and capacitive coupling between the
networks.
Backward Crosstalk - Coupling that creates a signal in a victim network
that travels in the opposite direction as the aggressor’s signal.
Forward Crosstalk - Coupling that creates a signal in a victim network that
travels in the same direction as the aggressor’s signal.
Even Mode Crosstalk - Coupling from a signal or multiple aggressors when
all the aggressors switch in the same direction that the victim is switching.
Odd Mode Crosstalk - Coupling from a signal or multiple aggressors when
all the aggressors switch in the opposite direction that the victim is
switching.
Flight Time Flight time is a term in the timing equation that includes the signal
propagation delay, any effects the system has on the T
CO
(time from
clock-in to data-out) of the driver, plus any adjustments to the signal at
the receiver needed to ensure the setup time of the receiver. More
precisely, flight time is defined as:
The time difference between a signal at the input pin of a receiving agent
crossing the switching voltage (adjusted to meet the receiver
About This Manual
316704-001 / Development Kit User’s Manual 9
Term/Acronym Definition
manufacturer’s conditions required for AC timing specifications; i.e.,
ringback, etc.) and the output pin of the driving agent crossing the
switching voltage when the driver is driving a test load used to specify the
driver’s AC timings.
Maximum and Minimum Flight Time - Flight time variations are caused by
many different parameters. The more obvious causes include variation of
the board dielectric constant, changes in load condition, crosstalk, power
noise, variation in termination resistance, and differences in I/O buffer
performance as a function of temperature, voltage, and manufacturing
process. Some less obvious causes include effects of Simultaneous
Switching Output (SSO) and packaging effects.
Maximum flight time is the largest acceptable flight time a network will
experience under all conditions.
Minimum flight time is the smallest acceptable flight time a network will
experience under all conditions.
Infrared Data
Assoc.
The Infrared Data Association (IrDA) has outlined a specification for serial
communication between two devices via a bi-directional infrared data
port. The development board has such a port and it is located on the rear
of the platform between the two USB connectors.
IMVP6+ The Intel Mobile Voltage Positioning specification for the Intel® Core™ 2
Duo Processor. It is a DC-DC converter module that supplies the required
voltage and current to a single processor.
Inter-Symbol
Interference
Inter-symbol interference is the effect of a previous signal (or transition)
on the interconnect delay. For example, when a signal is transmitted down
a line and the reflections due to the transition have not completely
dissipated, the following data transition launched onto the bus is affected.
ISI is dependent upon frequency, time delay of the line, and the reflection
coefficient at the driver and receiver. ISI may impact both timing and
signal integrity.
Media Expansion
Card
The Media Expansion Card (MEC) provides digital display options through
the SDVO interface. The MEC card also incorporates video-in via a x1 PCI
Express* port.
Network The network is the trace of a Printed Circuit Board (PCB) that completes
an electrical connection between two or more components.
Overshoot The maximum voltage observed for a signal at the device pad, measured
with respect to VCC.
Pad The electrical contact point of a semiconductor die to the package
substrate. A pad is only observable in simulations.
Pin The contact point of a component package to the traces on a substrate,
such as the motherboard. Signal quality and timings may be measured at
the pin.
Power-Good “Power-Good,” “PWRGOOD,” or “CPUPWRGOOD” (an active high signal)
indicates that all of the system power supplies and clocks are stable.
PWRGOOD should go active at a predetermined time after system
voltages are stable and should go inactive as soon as any of these
voltages fail their specifications.
Ringback The voltage to which a signal changes after reaching its maximum
absolute value. Ringback may be caused by reflections, driver oscillations,
or other transmission line phenomena.
About This Manual
10 316704-001 / Development Kit User’s Manual
Term/Acronym Definition
System Bus The System Bus is the microprocessor bus of the processor.
Setup Window The time between the beginning of Setup to Clock (TSU_MIN) and the
arrival of a valid clock edge. This window may be different for each type of
bus agent in the system.
Simultaneous
Switching Output
Simultaneous Switching Output (SSO) effects are differences in electrical
timing parameters and degradation in signal quality caused by multiple
signal outputs simultaneously switching voltage levels in the opposite
direction from a single signal or in the same direction. These are called
odd mode and even mode switching, respectively. This simultaneous
switching of multiple outputs creates higher current swings that may
cause additional propagation delay (“push-out”) or a decrease in
propagation delay (“pull-in”). These SSO effects may impact the setup
and/or hold times and are not always taken into account by simulations.
System timing budgets should include margin for SSO effects.
Stub The branch from the bus trunk terminating at the pad of an agent.
Trunk The main connection, excluding interconnect branches, from one end.
System
Management Bus
A two-wire interface through which various system components may
communicate.
Undershoot The minimum voltage extending below VSS observed for a signal at the
device pad.
VCC (CPU core) VCC (CPU core) is the core power for the processor. The system bus is
terminated to VCC (CPU core).
Victim A network that receives a coupled crosstalk signal from another network is
called the victim network.
Table 3 defines the acronyms used throughout this document.
Table 3. Acronyms
Acronym Definition
AC Audio Codec
ACPI Advanced Configuration and Power Interface
ADD2 Advanced Digital Display 2
ADD2N Advanced Digital Display 2 Normal
AGTL Assisted Gunning Transceiver Logic
AMC Audio/Modem Codec.
ASF Alert Standard Format
AMI American Megatrends Inc. (BIOS developer)
ATA Advanced Technology Attachment (disk drive interface)
ATX Advance Technology Extended (motherboard form factor)
BGA Ball Grid Array
About This Manual
316704-001 / Development Kit User’s Manual 11
Acronym Definition
BIOS Basic Input/Output System
CK-SSCD Spread Spectrum Differential Clock
CMC Common Mode Choke
CMOS Complementary Metal-Oxide-Semiconductor
CPU Central Processing Unit (processor)
DDR Double Data Rate
DMI Direct Memory Interface
ECC Error Correcting Code
EEPROM Electrically Erasable Programmable Read-Only Memory
EHCI Enhanced Host Controller Interface
EMA Extended Media Access
EMI Electro Magnetic Interference
ESD Electrostatic Discharge
EV Engineering Validation
EVMC Electrical Validation Margining Card
FCBGA Flip Chip Ball Grid Array
FCPGA Flip Chip Pin Grid Array
FIFO First In First Out - describes a type of buffer
FS Full-speed. Refers to USB
FSB Front Side Bus
FWH Firmware Hub
GMCH Graphics Memory Controller Hub
HDA High Definition Audio
HDMI High Definition Media Interface
HS High-speed. Refers to USB
ICH I/O Controller Hub
IDE Integrated Drive Electronics
IMVP Intel Mobile Voltage Positioning
IP/IPv6 Internet Protocol/Internet Protocol version 6
IrDA Infrared Data Association
ISI Inter-Symbol Interference
KBC Keyboard Controller
LAI Logic Analyzer Interface
LAN Local Area Network
LED Light Emitting Diode
About This Manual
12 316704-001 / Development Kit User’s Manual
Acronym Definition
LOM LAN on Motherboard
LPC Low Pin Count
LS Low-speed. Refers to USB
LVDS Low Voltage Differential Signaling
mBGA Mini Ball Grid Array
MC Modem Codec
MEC Media Expansion Card
MHz Mega-Hertz
OEM Original Equipment Manufacturer
PCIe PCI Express*
PCM Pulse Code Modulation
POST Power On Self Test
PLC Platform LAN Connect
RAID Redundant Array of Inexpensive Disks
RTC Real Time Clock
SATA Serial ATA
SIO Super Input/Output
SKU StockKeeping Unit
SMBus System Management Bus
SODIMM Small Outline Dual In-line Memory Module
SPD Serial Presence Detect
SPI Serial Peripheral Interface
SPWG Standard Panels Working Group - http://www.spwg.org/
SSO Simultaneous Switching Output
STR Suspend To RAM
TCO Total Cost of Ownership
TCP Transmission Control Protocol
TDM Time Division Multiplexed
TDR Time Domain Reflectometry
µBGA Micro Ball Grid Array
UDP User Datagram Protocol
UHCI Universal Host Controller Interface
USB Universal Serial Bus
VGA Video Graphics Adapter
VID Voltage Identification
About This Manual
316704-001 / Development Kit User’s Manual 13
Acronym Definition
VREG Voltage Regulator
XDP eXtended Debug Port
1.4 Support Options
1.4.1 Electronic Support Systems
Intel’s web site (http://www.intel.com/) provides up-to-date technical information and
product support. This information is available 24 hours per day, 7 days per week,
providing technical information whenever you need it.
1.4.2 Additional Technical Support
If you require additional technical support, please contact your Intel Representative or
local distributor.
1.5 Product Literature
In order to order hard copies of product literature the following instructions should be
followed:
1. Determine the SKU Number
If you do not know the SKU # of the document you are ordering, please select
the back button to view the document again. The SKU # is the first 6 digits of
the number on the PDF file, such as: 12345612.pdf or at the bottom of the
download page for that document.
2. Call, Mail or Email a request
Call: To place an order for a publication or text in hardcopy or CD form,
please contact our Intel® Literature Fulfillment Centers listed in Table 4
.
Table 4. Intel Literature Centers
Location Telephone Number
U.S. and Canada 1-800-548-4725
International 1-303-675-2148
Fax 1-303-675-2120
Mail a request to:
About This Manual
14 316704-001 / Development Kit User’s Manual
Intel Literature Fulfilment Center
P.O. Box 5937
Denver, Colorado 80217-9808
USA
Email a request to: [email protected]
Please make sure to include in your mailed/emailed request:
SKU #
Company Name
Your Name (first, last)
Full mailing address
Daytime Phone Number in case of questions
Note: Please be aware not all documents are available in all media types. Some may only be
available as a download.
1.6 Related Documents
Table 5 provides a summary of publicly available documents related to this
development kit. For additional documentation, please contact your Intel
Representative.
Table 5. Related Documents
Document Title Location
Intel® Core™2 Duo Processor for Mobile
Intel® 965 Express Chipset Family
Datasheet
http://www.intel.com/design/mobile/datashts/316
745.htm
Mobile Intel
®
965 Express Chipset Family
Datasheet
http://www.intel.com/design/mobile/datashts/316
273.htm
Intel
®
I/O Controller Hub 8 (ICH8) Family
Datasheet
http://www.intel.com/design/chipsets/datashts/3
13056.htm
Intel® Centrino® Pro processor technology
and Intel® Centrino® Duo processor
technology Design Guide For Intel®
Core™2 Duo Mobile Processor, Mobile
Intel® 965 Express Chipset Family and
Intel® 82801HBM ICH8M & Intel®
82801HEM ICH8M-E I/O Controller Hub
Based Systems
Contact your Intel representative for access to
this document
Intel
®
Core™2 Duo Mobile Processor,
Mobile Intel
®
965 Express Chipset Family
and ICH8M I/O Controller Hub Schematics
Contact your Intel representative for access to
this document
§
Getting Started
316704-001 / Development Kit User’s Manual 15
2 Getting Started
This chapter identifies the development kit’s key components, features and
specifications. It also details basic development board setup and operation.
2.1 Overview
The development board consists of a baseboard populated with the Intel
®
Core
TM
2
Duo processor, the Mobile Intel
®
GME965 Express Chipset, other system board
components and peripheral connectors.
Note: The development board is shipped as an open system allowing for maximum flexibility
in changing hardware configuration and peripherals. Since the board is not in a
protective chassis, take extra precaution when handling and operating the system.
2.1.1 Development Board Features
Features of the development board are summarized in Table 6.
Table 6. Development Board feature Set Summary
Development Board
Implementation
Comments
Processor
Intel
®
Core
TM
2 Duo processor with
4 MByte L2 Cache on 65nm process
FSB 533/667/800 MHz support
478 pin Flip Chip Pin Grid Array (Micro-
FCPGA) package
Mobile Intel
®
GME965 Express
Chipset (GMCH)
1299-pin Micro-FCBGA Package
Chipset
Intel
®
I/O Controller Hub 8-M
Enhanced (ICH8M-E)
676-pin BGA Package
Memory
Two DDR2 RAM SO-DIMM slots. Maximum 4GB of DDR2 Memory (RAM)
using 1Gb technology and stacked SO-
DIMMs.
Supports DDR2 frequency of 533 or
667MHz
Video
One PCI Express* Graphics Slot
One dual channel LVDS Connector
One VGA Connector
One TV D-Connector supporting S-
Video, Composite video and
Component video
The Mobile Intel
®
GME965 Express Chipset
(GMCH) has 2 video pipes which allows
support of dual independent display.
18-bpp and 24-bpp LVDS panel support
Support for two SDVO channels via x16
PCIe connector (through ADD2 or MEC
cards)
F
E
A
T
U
R
E
PCI One 5V PCI slot PCI revision 2.3 compliant (33MHz)
Getting Started
16 316704-001 / Development Kit User’s Manual
Development Board
Implementation
Comments
PCI Express*
Three x1 connectors
One x16 connector
Revision 1.1 compliant
There are Five x1 PCI Express* slots but
slots 2 and 4 are not intended for use with
PCI Express* add-in cards. Only slots 1, 3
and 5 are supported.
On-Board LAN
10/100/1000 Mbps connectivity
from the Intel
®
82566MM Gigabit
Platform LAN Connect component
The 82566MM is connected to the ICH via
the ICH’s GLCI and LCI interfaces.
SPI Two 16Mbit devices
PATA 33/66/100 1 Channel
ATA/Storage
3 SATA Ports 2 Cable Connector and 1 Direct Connect
Connector. RAID 0/1 support.
USB
10 USB 2.0/1.1 Ports Five ports provided on rear-panel, four
provided via headers (J6H3, J6H3) and
one via the PCI Express* docking
connector
LPC One LPC slot Includes sideband headers
BIOS AMI BIOS installed in an 8Mb FWH 40-pin TSOP socket
SMC/KBC
Hitachi H8S/2104 micro-controller
Two PS/2 ports
One scan matrix keyboard
connector
ACPI compliant
F
E
A
T
U
R
E
Clocks
CK-505 clock synthesizer and
DB800M clock buffer
Super I/O SMSC SIO1007-JV Supports IrDA and UART serial interfaces
RTC Battery-backed Real Time Clock
Thermal
Monitoring
Processor temperature sensor
Processor
Voltage
Regulator
IMVP-6+ for processor core
Desktop Mode ATX Power Supply
Power Supply
Mobile Mode Battery Pack (smart battery support)
AC Mobile Brick
Port 80 display Through Add-in card. Four seven-segment
displays
Debug
Interfaces
Extended Debug Port (XDP) XDP connector
Intel
®
AMT
support
Intel
®
Active Management
Technology 2.5
Supported on the development board with
M0, M1, and M-off management states
Getting Started
316704-001 / Development Kit User’s Manual 17
Development Board
Implementation
Comments
Power
Management
ACPI Compliant S0 – Power On
S3 – Suspend to RAM
S4 – Suspend to Disk
S5 – Soft Off
M0 – All Wells powered
M1 – Main Well down. Only ME power on
M-off – ME powered off
Form Factor ATX 2.2 like form factor 10 layer board – 12” x 10.2”
Note: Review the document provided with the Development Kit titled “Important Safety and
Regulatory Information”. This document contains safety warnings and cautions that
must be observed when using this development kit.
2.2 Included Hardware and Documentation
The following hardware and documentation is included in the development kit:
• One development board
• One Intel
®
Core
TM
2 Duo processor with 4 MB L2 Cache on 65nm process in
the 478 pin Flip-Chip Pin Grid Array (Micro-FCPGA) package (Installed)
• One Firmware Hub (FWH) (Installed)
• One GMCH (GME965) heatsink (Installed)
• One Type 2032, socketed 3 V lithium coin cell battery (Installed)
• One 256 MByte DDR2 SODIMM (200 Pin)
• One CPU thermal solution and CPU back plate (included in kit box – not
populated on board)
• One cable kit
• One Development Kit User’s Manual
• One Port 80 add-in card
2.3 Software Key Features
The driver CD included in the kit contains all of the software drivers necessary for
basic system functionality under the following operating systems: Windows* XP/XP
Embedded, Vista and Linux*.
Getting Started
18 316704-001 / Development Kit User’s Manual
Note: While every care was taken to ensure the latest versions of drivers were provided on
the enclosed CD at time of publication, newer revisions may be available. Updated
drivers for Intel components can be found at:
http://developer.intel.com/design/intarch/software/index.htm
For all third-party components, please contact the appropriate vendor for updated
drivers.
Note: Software in the kit is provided free by the vendor and is only licensed for evaluation
purposes. Refer to the documentation in your evaluation kit for further details on any
terms and conditions that may be applicable to the granted licenses. Customers using
the tools that work with Microsoft* products must license those products. Any targets
created by those tools should also have appropriate licenses. Software included in the
kit is subject to change.
Refer to http://developer.intel.com/design/intarch/devkits
for details on additional
software from other third-party vendors.
2.3.1 AMI BIOS
This development kit ships with AMI* BIOS pre-boot firmware from AMI* pre-
installed. AMI* BIOS provides an industry-standard BIOS platform to run most
standard operating systems, including Windows* XP/XP Embedded, Linux*, and
others.
The AMI* BIOS Application Kit (available through AMI*) includes complete source
code, a reference manual, and a Windows-based expert system, BIOStart*, to enable
easy and rapid configuration of customized firmware for your system.
The following features of AMI* BIOS are enabled in the development board:
• DDR2 SDRAM detection, configuration, and initialization
• Mobile Intel
®
GME965 Express Chipset configuration
• POST codes displayed to port 80h
• PCI/PCI Express* device enumeration and configuration
• Integrated video configuration and initialization
• Super I/O configuration
• CPU microcode update
• Active Management Technology
• RAID 0/1 Support
2.4 Before You Begin
The following additional hardware may be necessary to successfully set up and
operate the development board.
Getting Started
316704-001 / Development Kit User’s Manual 19
VGA Monitor: Any standard VGA or multi-resolution monitor may be used. The setup
instructions in this chapter assume the use of a standard VGA monitor, TV, or flat
panel monitor.
Keyboard: The development board can support either a PS/2 or USB style keyboard.
Mouse: The development board can support either a PS/2 or USB style mouse.
Hard Drives and Optical Disc Drives: Up to Three SATA drives and two IDE devices
(master and slave) may be connected to the development board. An optical disc drive
may be used to load the OS. All these storage devices may be attached to the board
simultaneously.
Video Adapter: Integrated video is output from the VGA connector on the back panel
of the development board. Alternately, a standard PCI Express* video adapter, ADD2
card or MEC video adapter may be used for additional display flexibility. Please contact
the respective vendors for drivers and necessary software for adapters not provided
with this development kit. Check the BIOS and the graphics driver, where appropriate,
for the proper video output settings.
Note: The enclosed driver CD includes drivers necessary for LAN, Integrated graphics, and
system INF utilities.
Network Adapter: A Gigabit network interface is provided on the development
board. The network interface will not be operational until after all the necessary
drivers have been installed. A standard PCI/PCI Express* adapter may be used in
conjunction with, or in place of, the onboard network adapter. Please contact the
respective vendors for drivers and necessary software for adapters not provided with
this development kit.
You must supply appropriate network cables to utilize the LAN connector or any other
installed network cards.
Power Supply: The development board has the option to be powered from two
different power sources: an ATX power supply or AC to DC adapter. The development
board contains all of the voltage regulators necessary to power the system.
There are two main supported power supply configurations, Desktop and Mobile. The
Desktop solution consists of only using the ATX power supply. The Mobile solution
consists of only using the AC to DC adapter.
Warning: The power supply cord is the main disconnect device to mains (AC power). The socket
outlet shall be installed near the equipment and shall be readily accessible.
Note: Desktop peripherals, including add-in cards, will not work in mobile power mode. If
desktop peripherals are used, the development board must be powered using desktop
power mode.
If using an ATX power supply, select a power supply that complies with the "ATX12V"
1.1 specification. For more information, refer to http://www.formfactors.org
.
Note: If the power button on the ATX power supply is used to shut down the system, wait at
least five seconds before turning the system on again to avoid damaging the system.
Getting Started
20 316704-001 / Development Kit User’s Manual
Other Devices and Adapters: The development board functions much like a
standard desktop computer motherboard. Most PC-compatible peripherals can be
attached and configured to work with the development board.
2.5 Setting Up the Development Board
Once the necessary hardware (described in Section 2.4) has been gathered, follow the
steps below to set up the development board.
Note: To locate items discussed in the procedure below, please refer to Chapter
4.
1. Create a safe work environment.
Ensure a static-free work environment before removing any components from
their anti-static packaging. The development board is susceptible to
electrostatic discharge (ESD) damage, and such damage may cause product
failure or unpredictable operation. A flame retardant work surface must also
be used.
Caution: It is recommended that an ESD wrist strap be used when handling the
development board.
2. Inspect the contents of your kit.
Check for damage that may have occurred during shipment. Contact your
sales representative if any items are missing or damaged.
Caution: Since the development board is not in a protective chassis, use caution
when connecting cables to this product.
Caution: Standby voltage is constantly applied to the development board. Remove
power before any hardware (peripherals, keyboards, mice, monitors,
accessories, add-in cards, etc) is added or removed from the board.
Note: The development board is a standard ATX form factor. An ATX chassis may
be used if a protected environment is desired. If a chassis is not used,
standoffs must be used to elevate the development board off the working
surface to protect the memory and board components from any
accidental contact to metal objects.
3. Check the jumper default position setting. Refer to Figure 7
for jumper location.
Jumper J5H2 is used to clear the CMOS memory. Make sure this jumper is set to
1-x for normal operation.
4. Be sure to populate the following hardware on your development board:
• One Intel
®
Core
TM
2 Duo processor
• One processor thermal solution
• One 256 MByte DDR2 667 SODIMM (200-pin) into connector J5P1.
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