Transcend TS32MLS72V6D Datasheet

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168PIN PC133 Unbuffered DIMM

256MB With 16Mx8 CL3

Description

The TS32MLS72V6D is a 32M x 72bits Synchronous

Dynamic RAM high-density for PC-133. The

TS32MLS72V6D consists of 18pcs CMOS 16Mx8 bits

Synchronous DRAMs in TSOP-II 400mil packages and a

2048 bits serial EEPROM on a 168-pin printed circuit

board. The TS32MLS72V6D is a Dual In-Line Memory

Module and is intended for mounting into 168-pin edge

connector sockets.

Synchronous design allows precise cycle control with the

use of system clock. I/O transactions are possible on

every clock cycle. Range of operation frequencies,

programmable latencies allow the same device to be

useful for a variety of high bandwidth, high performance

memory system applications.

Features

• Performance Range : PC-133 CL3

• Conformed to JEDEC Standard Spec.

• Burst Mode Operation.

• Auto and Self Refresh.

• CKE Power Down Mode.

• DQM Byte Masking (Read/Write)

• Serial Presence Detect (SPD) with serial EEPROM

• LVTTL compatible inputs and outputs.

• Single 3.3V ± 0.3V power supply.

• MRS cycle with address key programs.

Latency (Access from column address)

Burst Length (1,2,4,8 & Full Page)

Data Sequence (Sequential & Interleave)

• All inputs are sampled at the positive going edge of

the system clock.

Placement

E

H

G

F

E

D

C

B

A

I

PCB :09-7149

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168PIN PC133 Unbuffered DIMM

256MB With 16Mx8 CL3

Dimensions

Clock Input.

Side Millimeters

CKE0, CKE1

Clock Enable Input.

Inches

A

/CS0~/CS3

133.35±0.40 5.250±0.016

B

Chip Select Input.

65.67000 2.585000

/RAS

Row Address Strobe

C 23.49000 0.925000

/CAS

D 8.89000 0.350000

Column Address Strobe

E 3.00000

/WE

Write Enable

0.118000

F

DQM0~DQM7

31.75±0.2000 1.250±0.0080

G

Data (DQ) Mask

19.8000 0.780000

SA0~SA2

Address in EEPROM

H 15.80

SCL

0.622

I 1.27±0.10 0.050±0.004

Serial PD Clock

(Refer Placement)

Pin Identification

SDA

Serial PD Add/Data input/output

Symbol Function

Vcc

A0~A11, BA0, BA1

+5.0 Voltage Power Supply

Address input

DQ0~DQ63,

Vss

Ground

C0~C7

Data Input / Output.

NC

CLK0~CLK3

No Connection

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168PIN PC133 Unbuffered DIMM

256MB With 16Mx8 CL3

Pinouts:

DQM7

06

Vss

13

NC

20 DQ15

Vss

27 /WE

DQ61

34 A2

SA1

41 Vcc

No

Name

Vcc 48 NC 90

DQ9 55 DQ16 97

62 *Vref 104

69 DQ24 111

76 DQ30 118

83 SCL 125

No

Vcc 132 *A13

DQ41 139 DQ48

DQ47 146 *Vref

/CAS 153 DQ56

A3 160 DQ62

*CLK1 167 SA2

Name

No

07 DQ4

14 DQ10

21 *C0

28 DQM0 70

35 A4 77

42 CLK0 84

Name

No

49 Vcc 91 DQ36

56 DQ17 98 DQ42

63 *CKE1 105 *C4

DQ25 112 DQM4

DQ31 119 A5

Vcc 126 *A12

Name

133 Vcc

140 DQ49

147 *REGE

154 DQ57

161 DQ63

168 Vcc

01 Vss 43

08 DQ5 50

15 DQ11 57

22 *C1 64

29 DQM1 71 DQ26

36 A6 78 Vss

* Please refer Block Diagram

Vss 85 Vss 127

NC 92 DQ37 134

DQ18 99 DQ43 141

Vss 106 *C5 148

113 DQM5 155

120 A7 162

Vss

02

NC

09

DQ50

16

Vss

23

DQ58

30

Vss

37

DQ0 44 NC

DQ6 51 NC

DQ12 58 DQ19

Vss 65 DQ21

/CS0 72 DQ27

A8 79 *CLK2 121

86 DQ32 128 CKE0

93 DQ38 135 NC

100 DQ44 142 DQ51

107 Vss 149 DQ53

114 */CS1 156 DQ59

A9 163 *CLK3

03 DQ1

10 DQ7

17 DQ13

24 NC

31 NC

38 A10/AP

45 /CS2

52 *C2 94

59 Vcc 101

66 DQ22 108

73 Vcc 115

80 NC 122

87 DQ33 129 */CS3

136 *C6

04 DQ2

11 DQ8

18 Vcc

NC

46 DQM2 88 DQ34

53 *C3 95 DQ40

60 DQ20 102 Vcc

67 DQ23 109 NC

DQ28 116 Vss

A11

130 DQM6

137 *C7

12

144 DQ52

19

151 DQ55

26

158 DQ60

33

165 SA0

40

05 DQ3 47

Vss 54

DQ14 61

Vcc 68

A0 75

Vcc 82

DQM3 89 DQ35 131

Vss 96 Vss 138

NC 103 DQ46 145

Vss 110 Vcc 152

DQ29 117 A1 159

SDA 124 Vcc 166

DQ39

DQ45 143 Vcc

NC 150 DQ54

/RAS 157 Vcc

BA0 164 NC

25

32 Vss 74

39 BA1 81 NC 123

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168PIN PC133 Unbuffered DIMM

256MB With 16Mx8 CL3

Block Diagram

SCL SDA

SCL

SDA

Serial EEPROM

A0 A1 A2

SA0 SA1 SA2

A0~A11,

BA0,BA1

DQ0~DQ7

/RAS

/CAS

/WE

/CS

CKE

CLK

DQM

DQM0

A0~A11,

BA0,BA1

DQ0~DQ7

/RAS

/CAS

/WE

/CS

CKE

CLK

DQM

DQM3

A0~A11,

BA0,BA1

DQ0~DQ7

/RAS

/CAS

/WE

/CS

CKE

CLK

DQM

DQM2

A0~A11,

BA0,BA1

DQ0~DQ7

/RAS

/CAS

/WE

/CS

CKE

CLK

DQM

DQM1

A0~A11,

BA0,BA1

DQ0~DQ7

/RAS

/CAS

/WE

/CS

CKE

CLK

DQM

DQM4

A0~A11,

BA0,BA1

DQ0~DQ7

/RAS

/CAS

/WE

/CS

CKE

CLK

DQM

DQM5

A0~A11,

BA0,BA1

DQ0~DQ7

/RAS

/CAS

/WE

/CS

CKE

CLK

DQM

DQM6

A0~A11,

BA0,BA1

DQ0~DQ7

/RAS

/CAS

/WE

/CS

CKE

CLK

DQM

DQM7

A0~A11,

BA0,BA1

DQ0~DQ7

/RAS

/CAS

/WE

/CS

CKE

CLK

DQM

DQM0

A0~A11,

BA0,BA1

DQ0~DQ7

/RAS

/CAS

/WE

/CS

CKE

CLK

DQM

DQM3

A0~A11,

BA0,BA1

DQ0~DQ7

/RAS

/CAS

/WE

/CS

CKE

CLK

DQM

DQM2

A0~A11,

BA0,BA1

DQ0~DQ7

/RAS

/CAS

/WE

/CS

CKE

CLK

DQM

DQM1

A0~A11,

BA0,BA1

DQ0~DQ7

/RAS

/CAS

/WE

/CS

CKE

CLK

DQM

DQM4

A0~A11,

BA0,BA1

DQ0~DQ7

/RAS

/CAS

/WE

/CS

CKE

CLK

DQM

DQM5

A0~A11,

BA0,BA1

DQ0~DQ7

/RAS

/CAS

/WE

/CS

CKE

CLK

DQM

DQM6

A0~A11,

BA0,BA1

DQ0~DQ7

/RAS

/CAS

/WE

/CS

CKE

CLK

DQM

DQM7

A0~A11,

BA0,BA1

DQ0~DQ63

/RAS

/CAS

/WE

/CS0

CKE0

/CS2

CLK0

CLK2

/CS1

CKE1

/CS3

CLK1

CLK3

A0~A11,

BA0,BA1

DQ0~DQ7

/RAS

/CAS

/WE

/CS

CKE

CLK

DQM

DQM1

C0~C7

A0~A11,

BA0,BA1

DQ0~DQ7

/RAS

/CAS

/WE

/CS

CKE

CLK

DQM

DQM5

C0~C7

16Mx8

SDRAM

16Mx8

SDRAM

16Mx8

SDRAM

16Mx8

SDRAM

16Mx8

SDRAM

16Mx8

SDRAM

16Mx8

SDRAM

16Mx8

SDRAM

16Mx8

SDRAM

16Mx8

SDRAM

16Mx8

SDRAM

16Mx8

SDRAM

16Mx8

SDRAM

16Mx8

SDRAM

16Mx8

SDRAM

16Mx8

SDRAM

16Mx8

SDRAM

16Mx8

SDRAM

This technical information is based on industry standard data and tests believed to be reliable. However, Transcend makes no warranties, either

expressed or implied, as to its accuracy and assumes no liability in connection with the use of this product. Transcend reserves the right to make

changes in specifications at any time without prior notice.

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168PIN PC133 Unbuffered DIMM

256MB With 16Mx8 CL3

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Value

Unit Note

Supply voltage

Parameter Symbol Min Max

Unit

Voltage on any pin relative to Vss

VDD 3.0 3.3

Unit

Address (A0 ~A11, BA0 ~BA1)

VIN, VOUT -1.0~4.6 V

3.6 V

/RAS, /CAS, /WE

CKE (CKE0 ~ CKE1)

Clock (CLK0 ~ CLK3)

Voltage on VDD supply to Vss VDD, VDDQ -1.0~4.6

Input high voltage VIH 2.0

/CS (/CS0 ~ /CS3)

DQM (DQM0 ~ DQM7)

DQ (DQ0 ~ DQ63)

CB (CB0 ~ CB7)

V

Storage temperature

3.0 VDD+0.3 V

C

ADD

C

IN

C

CKE

TSTG -55~+150 °C

1

Input low voltage

C

CLK

C

CS

C

DQM

Power dissipation PD 18

VIL -0.3 0 0.8

C

OUT1

COUT2

50

W

Short circuit current IOS 50

Output high voltage VOH

13

mA

Mean time between failure MTBF

2.4 - - V

13

95

50

50 year

Temperature Humidity Burning

IOH=-2mA

Output low voltage VOL

25

30

20

18

THB 85°C/85%, Static Stress °C-%

- - 0.4

18

pF

Temperature Cycling Test TC

V IOL=2mA

pF

0°C ~ 125°C Cycling °C

Note:

Input leakage current I

LI

-10 -

pF

Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.

10 uA 3

DC CHARACTERISTICS

Functional operation should be restricted to recommended operating condition.

Note:

1. VIH (max) = 5.6V AC .The overshoot voltage duration is ≤ 3ns.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS

2. VIL (min) = -2.0V AC .The undershoot voltage duration is ≤ 3ns.

Recommended operating conditions (Voltage referenced to Vss = 0V, TA = 0 to 70°C)

Parameter Symbol

3. Any input 0V ≤ VIN ≤ VDDQ.

Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.

Min Typ Max

CAPACITANCE

(VDD = 3.3V, TA = 23°C, f = 1MHz, VREF = 1.4V ± 200mV)

V 2

28

18

13

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168PIN PC133 Unbuffered DIMM

256MB With 16Mx8 CL3

(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)

Parameter Symbol

Active Standby Current

Test Condition Value Unit Note

ICC3N

CKE≥VIH(min), /CS≥VIH(min), tCC=10s

in non power-down mode

(One Bank Active)

AC OPERATING TEST CONDITIONS

(VDD = 3.3V±0.3V, TA = 0 to 70°C)

Operating Current

(One Bank Active)

Input signals are changed one time during 30ns

540

mA

I

CC1

Burst Length =1

t

RC≥tRC(min)

I

O=0mA

1,080 mA 1

I

CC3NS

CKE≥VIH(min), CLK≤VIL(max), tCC=∞

Input signals are stable

450

ICC2P

CKE≤V

IL(max), tCC=10ns 36

Operating Current

(Bust Mode)

ICC4

Precharge Standby Current

in power-down mode

I

CC2PS

CKE & CLK≤V

IL(max), tCC=∞

36

1,620

mA 1

mA

I

OL= 0 mA

Page Burst

4 Banks activated

tcc

D

= 2CLKs

ICC2N

CKE≥V

IH(min), /CS≥VIH(min), tCC=10ns

Precharge Standby Current

in non power-down mode

tRC≥tRC(min) 2,070 mA 2

Input signals are changed one time during 20ns

360

mA

Self Refresh Current ICC6

I

CC2NS

CKE≥V

IH(min), CLK≤VIL(max), tCC=∞

Input signals are stable

Note:

1. Measured with outputs open.

180

2. Refresh period is 64ms

CKE≤0.2V 36 mA

ICC3P

Active Standby Current

in power-down mode

3. Unless otherwise noted, input swing level is CMOS (VIH/VIL=VDDQ/VSSQ)

CKE≤V

IL(max), tCC=10ns 90

mA

I

CC3PS

CKE & CLK≤V

IL(max), tCC=∞

90

Refresh Current ICC5

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168PIN PC133 Unbuffered DIMM

256MB With 16Mx8 CL3

Parameter Value

Row cycle time

t

RC(min)

65

Unit

AC Input levels (VIH/VIL)

ns 1

2.4/0.4 V

Last data in to row precharge tRDL(min) 2

Input timing measurement reference level 1.4 V

CLK 2

Last data in to Active precharge

Input rise and fall time tr/tf=1/1 ns

tDAL(min) 2 CLK + 20ns -

Output timing measurement reference level 1.4

Last data in to new col. address delay

V

Output load condition See Fig. 2

tCDL(min) 1 CLK 2

Last data in to burst stop tBDL(min)

Output

(Fig. 1) DC Output Load Circuit

3.3V

1200 Ohm

50pF

870 Ohm

V

OH

(DC)=2.4V, I

OH

=-2mA

V

OL

(DC)=0.4V, I

OL

=2mA

Output

(Fig. 2) AC Output Load Circuit

Vtt=1.4V

50 Ohm

50pF

Z0=50 Ohm

OPERATING AC PARAMETER

(AC operating conditions unless otherwise noted)

Parameter Symbol

1 CLK 2

Value Unit Note

Col. address to col. address delay tCCD(min) 1

Row active to row active delay tRRD(min) 15

CLK 3

ns 1

CAS latency=3 2

Number of valid output data

/RAS to /CAS delay tRCD(min) 20 ns

ea 4

1

Row precharge time tRP(min) 20 ns

Note:

1

tRAS(min)

Row active time

1. The minimum number of clock cycles is determined by dividing the minimum time required with

clock cycle time, and then rounding off to the next higher integer.

45 ns 1

2. Minimum delay is required to complete write.

t

RAS(max)

3. All parts allow every cycle column address change.

100 us

4. In case of row precharge interrupt, auto precharge and read burst stop.

CAS latency=2 -

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168PIN PC133 Unbuffered DIMM

256MB With 16Mx8 CL3

AC CHARACTERISTICS

(AC operating conditions unless otherwise noted)

Refer to the individual component, not the whole module.

Parameter

ns 3

3. Assumed input rise and fall time (tr & tf)= 1ns.

Symbol Min Max

CLK low pulse width tCL 2.5

If tr & tf is longer than 1ns, transient time compensation should be considered,

Unit Note

CLK cycle time

- ns 3

i.e., [(tr + tf)/2-1]ns should be added to the parameter.

CAS latency=3 7.5

tCC

Input setup time tSS 1.5

CAS latency=2

Input hold time tSH 0.8

-

- ns 3

1000 ns 1

- ns 3

CAS latency=3

output delay

t

SAC

1 - ns

- 5.4

ns 1, 2

2

CLK to output

in Hi-Z

CLK to valid

CLK to output in Low-Z tSLZ

CAS latency=2

CAS latency=3 -

t

SHZ

- -

5.4

ns

CAS latency=3

hold time

t

OH

- -

3 -

ns

Output data

CAS latency=2

2

- -

CLK high pulse width tCH 2.5 -

2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.

Note:

1. Parameters depend on programmed CAS latency.

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168PIN PC133 Unbuffered DIMM

256MB With 16Mx8 CL3

SIMPLIFIED TRUTH TABLE

3

X X

X

H

COMMAND CKEn-1 CKEn

H

Both Banks

(V=Valid, X=Don’t Care, H=Logic High, L=Logic Low)

/CS /RAS /CAS /WE

H

4, 5

Write &

L H H

Note:

1. OP Code : Operand Code

DQM BA

0,1

A

10

/AP

X X X

Auto Precharge Disable

Column Address

H

X H

H

A

0

~A

11

, BA

0

~BA

1

: Program keys. (@MRS)

A

11

, A

0

~A

9

Note

3

X L H

2. MRS can be issued only at both banks precharge state.

Register Mode Register Set H X

Bank Active & Row Addr. H X

L L X V

Entry

H

Clock Suspend or

Active Power

Down

H

Exit

L H

A new command can be issued after 2 CLK cycles of MRS.

3. Auto refresh functions are as same as CBR refresh of DRAM.

L L L

L L H

L

Column

Address

H X

L

X X X

The automatically precharge without row precharge command is meant by “Auto”.

L X OP CODE

H X V

4

(A

0

~A

8

)

X X

X

Auto/self refresh can be issued only at both banks precharge state.

1,2

Auto Refresh

Refresh

Row Address

Auto Precharge Enable

X

4. BA

0

~BA

1

: Bank select address.

H

H L

L V

If both BA

0

and BA

1

are “Low” at read, write, row active and precharge, bank A is selected.

3

X X

H

4, 5

V

DQM

If both BA

0

is “High” and BA

1

is “Low” at read, write, row active and precharge, bank C is selected.

Entry L

Auto Precharge Disable

H X

H

L L H

L V V

V V

If both BA

0

is “Low” and BA

1

is “High” at read, write, row active and precharge, bank B is selected.

3

L

H X V

6

Bank Selection

Precharge

X

H X X X

New row active of the associated bank can be issued at tRP after the end of burst.

L H H H

Auto Precharge Enable

V L

X X

X X X

X

L H H

but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)

Self

Refresh

Exit

L H

4

L H L

H

H L

7. DQM sampled at positive going edged of a CLK masks the data-in at the very CLK (Write DQM latency is 0),

Read &

Column Address

Burst Stop H X

Exit

H X V

If both BA

0

and BA

1

are “High” at read, write, row active and precharge, bank D is selected.

L H L

L X X

X X

Column

Address

(A

0

~A

8

)

H X L

Entry

Precharge Power

Down Mode

X X

6. Burst stop command is valid at every burst length.

L H

X

X 7

If A

10

/AP is “High” at row precharge, BA

0

and BA

1

are ignored and both banks are selected.

X

No Operation Command

H X

5. During burst read or write with auto precharge, new read/write command cannot be issued.

Another bank read/write command can be issued after the end of burst.

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168PIN PC133 Unbuffered DIMM

256MB With 16Mx8 CL3

Serial Presence Detect Specification

Serial Presence Detect

11 DIMM configuration type ECC

A0

24

Superset Information - 00

Byte No. Function Described Standard Specification

02

12 Refresh Rate Type

SDRAM Access Time from Clock @CAS Latency of 2 6ns 60

Vendor Part

0 Number of Bytes Written into Serial Memory

15.625us/Self Refresh 80

25 SDRAM Cycle Time @CAS Latency of 1 -

128bytes 80

13 Primary SDRAM Width X8

00

26

1 Total # of Bytes of S.P.D Memory 256bytes

08

14

SDRAM Access Time from Clock @CAS Latency of 1 - 00

08

2 Fundamental Memory Type

Error Checking SDRAM Width X8 08

27 Minimum Row Precharge Time (=t RP) 20ns

SDRAM 04

15 Min Clock Delay for Back to Back Random Address tCCD=1CLK

14

28

3 Number of Row Addresses on this Assembly 12

01

16

Minimum Row Active to Row Activate (=t RRD) 15ns 0F

0C

4 Number of Column Addresses on this Assembly

SDRAM Device Attributes: Burst Lengths Supported 1,2,4,8 & Full page 8F

29 Minimum RAS to CAS Delay (=t RCD) 20ns

10 0A

17 SDRAM Device Attributes: # of banks on SDRAM device 4 bank

14

30

5 Number of Module Rows on this Assembly 2 rows

04

18

Minimum Activate Precharge Time (=t RAS) 45ns 2D

02

6 Data Width of this Assembly

SDRAM Device Attributes: CAS Latency 2,3 06

31 Module Row Density 2 rows of 128MB

72bits 48

19 SDRAM Device Attributes: CS Latency 0 clock

20

32

7 Data Width of this Assembly -

01

20

Command and Address Signal input Setup Time 1.5ns 15

00

8 Voltage Interface Standard of this Assembly LVTTL 01

SDRAM Device Attributes: Write Latency 0 clock 01

21 SDRAM Module Attributes

Non-buffered,

non-registered &

redundant addressing

00

33 Command and Address Signal input Hold Time 0.8ns 08

34 Data Signal Setup Time 1.5ns 15

9 SDRAM Cycle Time @CAS latency of 3 7.5ns

22

75

10 SDRAM Access Time from Clock @CAS latency of 3

SDRAM Device Attributes: General

+/- 10% voltage

tolerance, Burst Read

Single bit Write

precharge all, auto

precharge

0E

35 Data Signal Hold Time 0.8ns

5.4ns 54

23 SDRAM Cycle Time @CAS Latency of 2 10ns

08

36-61

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168PIN PC133 Unbuffered DIMM

256MB With 16Mx8 CL3

62 SPD Data Revision Code JEDEC2

By Manufacturer Variable

99-125

02

63

Manufacturer Specific Data - 0

Checksum for Bytes 0-62 - B2

126 Intel Specification Frequency

64-71 Manufacturers JEDEC ID Code per JEP-108E Transcend

- 64

127

7F, 4F

72

Intel Specification CAS# Latency/Clock Signal Support CL=2, 3 Clock 0 F6

Manufacturing Location T 54

128~ Unused Storage Locations

54 53 33

32 4D 4C

53 37 32 56 36 44

73-90 Manufacturers Part Number TS32MLS72V6D

Open FF

20 20 20 20 20 20

91-92 Revision Code - 0

93-94 Manufacturing Date By Manufacturer Variable

95-98 Assembly Serial Number

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