Motorola DragonBall MC68328 User manual

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MOTOROLA, 1995

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TM

MC68328 (DragonBall)

Integrated Processor

User’s Manual

MOTOROLA

MC68328 DRAGONBALL PROCESSOR USER’S MANUAL

iii

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iv

MC68328 DRAGONBALL PROCESSOR USER’S MANUAL

MOTOROLA

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MOTOROLA

MC68328 DRAGONBALL PROCESSOR USER’S MANUAL

v

PREFACE

The

MC68328 Integrated Portable System Processor User's Manual

describes the program-

ming, capabilities, and operation of the M68328; the

MC68000 Family Programmer’s Refer-

ence Manual

provides instruction details for the EC000 core; and the

Integrated Portable

System Process: DragonBall Product Brief

provides an overview of the M68328.

The organization of this manual is as follows:

Section 1 Overview

Section 2 System Integration Module

Section 3 Phase-Locked Loop and Power Control

Section 4 LCD Controller Module

Section 5 Real-Time Clock Module

Section 6 Timer Module

Section 7 Parallel Ports

Section 8 Universal Asynchronous Receiver Transmitter (UART) Module

Section 9 Serial Peripheral Interfact—Slave (SPIS)

Section 10 Serial Peripheral Interface—Master (SPIM)

Section 11 Pulse-Width Modulator

Section 12 Pin Assignment

Section 13 Electrical Characteristics

Index

TRADEMARKS

All trademarks reside with their respective owners.

vi MC68328 DRAGONBALL PROCESSOR USER’S MANUAL MOTOROLA

MOTOROLA

MC68328 DRAGONBALL PROCESSOR USER’S MANUAL

vii

TABLE OF CONTENTS

Section 1

MC68328 Processor Overview

1.1 Key Features................................................................................................ 1-1

1.1.1 Organization .............................................................................................. 1-3

1.1.2 Advantages................................................................................................ 1-3

1.2 MC68328 Architecture................................................................................. 1-4

1.2.1 EC000 Static Core..................................................................................... 1-4

1.2.1.1 EC000 Core Programming Model ........................................................... 1-4

1.2.1.2 Data Types and Address Modes ............................................................. 1-4

1.2.1.3 Instruction Set Overview.......................................................................... 1-6

1.2.2 System Integration Module........................................................................ 1-8

1.2.2.1 System Configuration .............................................................................. 1-8

1.2.2.2 VCO/PLL Clock Synthesizer.................................................................... 1-8

1.2.2.3 Chip-Select Logic .................................................................................... 1-8

1.2.2.4 External Bus Interface ............................................................................. 1-8

1.2.2.5 Interrupt Controller................................................................................... 1-8

1.2.2.6 Parallel General-Purpose I/O Ports......................................................... 1-9

1.2.2.7 Software Watchdog ................................................................................. 1-9

1.2.2.8 Low Power Stop Logic............................................................................. 1-9

1.2.3 LCD Controller........................................................................................... 1-9

1.2.4 UART and Infrared Communication Support............................................. 1-9

1.2.5 Real-Time Clock........................................................................................ 1-9

1.2.6 JTAG Test Access Port ........................................................................... 1-10

1.2.7 SIM28 Programming Model..................................................................... 1-10

Section 2

System Integration Module

2.1 Module Operation ........................................................................................ 2-1

2.1.1 MC68328 Processor System Configuration............................................... 2-1

2.1.1.1 System Control Register Functions......................................................... 2-1

2.1.1.2 System Protection Functions................................................................... 2-2

2.1.2 Chip-Select and Wait-State Logic.............................................................. 2-2

2.1.2.1 Programmable Data-Bus Size................................................................. 2-3

2.1.2.2 Overlap in Chip-Select Ranges ............................................................... 2-5

2.2 Programming Model..................................................................................... 2-5

2.2.1 System Control Register (SCR)................................................................. 2-5

2.3 Interrupt Controller Block............................................................................. 2-6

2.3.1 Interrupt Controller Overview..................................................................... 2-6

2.3.2 Programmer’s Model ................................................................................. 2-8

2.3.2.1 Interrupt Vector Register (IVR)................................................................ 2-8

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2.3.2.2 Vector Generator..................................................................................... 2-8

2.3.2.3 Interrupt Control Register (ICR)............................................................... 2-9

2.3.2.4 Interrupt Mask Register (IMR)............................................................... 2-10

2.3.2.5 Interrupt WakeUp-enable Register (IWR).............................................. 2-13

2.3.2.6 Interrupt Status Register (ISR).............................................................. 2-13

2.3.2.7 Interrupt-Pending Register (IPR)........................................................... 2-16

2.4 Keyboard Interrupt I/O............................................................................... 2-16

2.5 Chip-Select Registers................................................................................ 2-16

2.5.1 Group-Base Address Registers (GBR0-GBR3)........................................2-16

2.5.2 Group-Base Address Mask Registers..................................................... 2-17

2.5.3 Chip-Select Registers.............................................................................. 2-17

2.6 PCMCIA 1.0 Support................................................................................. 2-19

2.6.1 Block Diagram Overview......................................................................... 2-19

Section 3

Phase-Locked Loop and Power Control

3.1 Overview...................................................................................................... 3-1

3.2 Programmer’s Model ................................................................................... 3-1

3.2.1 PLL Control Register................................................................................. 3-2

3.2.2 Frequency Select Register........................................................................ 3-2

3.3 PLL Operation.............................................................................................. 3-3

3.3.1 Initial Powerup........................................................................................... 3-3

3.3.2 Divider ....................................................................................................... 3-3

3.3.3 Normal Startup .......................................................................................... 3-4

3.3.4 Change of Frequency................................................................................ 3-4

3.3.5 PLL Shutdown........................................................................................... 3-4

3.4 Power Control Module Overview................................................................. 3-5

3.4.1 Description................................................................................................. 3-5

3.4.2 MPU Interface............................................................................................ 3-7

3.4.3 Operation................................................................................................... 3-8

3.4.3.1 Normal Operation.................................................................................... 3-8

3.4.3.2 Doze Operation ....................................................................................... 3-8

3.4.3.3 Sleep Operation ...................................................................................... 3-8

Section 4

LCD Controller Module

4.1 LCDC System Overview.............................................................................. 4-1

4.1.1 MPU Interface............................................................................................ 4-1

4.1.2 Direct Memory Access (DMA) ................................................................... 4-1

4.1.3 Line Buffer................................................................................................. 4-2

4.1.4 Cursor Control Logic.................................................................................. 4-2

4.1.5 Frame Rate Control (FRC) ........................................................................ 4-2

4.1.6 LCD Interface ............................................................................................ 4-3

4.2 Interfacing LCDC with LCD Panel ............................................................... 4-3

4.3 Panel I/F Timing........................................................................................... 4-4

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4.4 Operation Overview..................................................................................... 4-7

4.5 Display Control............................................................................................. 4-7

4.5.1 LCD Screen Format................................................................................... 4-7

4.5.2 Cursor Control Logic.................................................................................. 4-8

4.5.3 Display Data Mapping................................................................................ 4-8

4.5.4 Gray Scale Generation.............................................................................. 4-8

4.5.5 Gray Palette Mapping................................................................................ 4-8

4.5.6 FRC Offset Control .................................................................................. 4-10

4.5.7 Cursor and Blinking Rate Control............................................................ 4-10

4.5.8 Low-Power Mode..................................................................................... 4-10

4.6 DMA Controller Overview .......................................................................... 4-11

4.6.1 Basic Operation....................................................................................... 4-11

4.7 Register Descriptions................................................................................. 4-13

4.7.1 System Memory Control Registers.......................................................... 4-13

4.7.1.1 Screen Starting Address Register (SSA)............................................... 4-13

4.7.1.2 Virtual Page Width Register (VPW)....................................................... 4-13

4.7.2 Screen Format Registers......................................................................... 4-13

4.7.2.1 Screen Width Register (XMAX)............................................................. 4-13

4.7.2.2 Screen Height Register (YMAX)............................................................ 4-14

4.7.3 Cursor Control Registers ......................................................................... 4-14

4.7.3.1 Cursor X Position Register (CXP).......................................................... 4-14

4.7.3.2 Cursor Y Position Register (CYP).......................................................... 4-14

4.7.3.3 Cursor Width & Height Register (CWCH).............................................. 4-15

4.7.3.4 Blink Control Register (BLKC)............................................................... 4-15

4.7.4 LCD Panel Interface Registers................................................................ 4-15

4.7.4.1 Panel Interface Configuration Register (PICF)...................................... 4-15

4.7.4.2 Polarity Configuration Register (POLCF)............................................... 4-16

4.7.4.3 LACD (M) Rate Control Register (ACDRC)........................................... 4-17

4.7.5 Line Buffer Control Registers................................................................... 4-17

4.7.5.1 Pixel Clock Divider Register (pxcd) ....................................................... 4-17

4.7.5.2 Clocking Control Register (CKCON)...................................................... 4-17

4.7.5.3 Last Buffer Address Register (LBAR).................................................... 4-18

4.7.5.4 Octet Terminal Count Register(OTCR).................................................. 4-18

4.7.5.5 Panning Offset Register (POSR)........................................................... 4-19

4.7.6 Gray-Scale Control Registers.................................................................. 4-19

4.7.6.1 Frame-Rate Modulation Control Register (FRCM)................................ 4-19

4.7.6.2 Gray Palette Mapping Register (GPMR) ............................................... 4-19

4.8 Bandwidth Calculation and Saving ............................................................ 4-20

4.8.1 Bus Overhead Considerations................................................................. 4-20

Section 5

Real-Time Clock Module

5.1 Operating Characteristics ............................................................................ 5-1

5.1.1 Prescaler and Counter............................................................................... 5-1

5.1.2 Alarm ......................................................................................................... 5-1

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5.1.3 Minute Stopwatch...................................................................................... 5-1

5.1.4 Registers ................................................................................................... 5-2

5.1.4.1 RTC Hours-Minutes-Seconds Register (RTCHMS) ................................ 5-2

5.1.4.2 Alarm Register (RTCALRM).................................................................... 5-3

5.1.4.3 RTC Control Register (RTCCTL)............................................................. 5-3

5.1.4.4 Interrupt Status Register (RTCISR) .........................................................5-4

5.1.4.5 Interrupt-Enable Register (RTCIENR)..................................................... 5-5

5.1.4.6 Stopwatch Register (STPWTCH)............................................................ 5-6

Section 6

Timer

6.1 General Purpose Timers.............................................................................. 6-2

6.2 Software Watchdog Timer........................................................................... 6-3

6.3 Signal Descriptions...................................................................................... 6-3

6.4 Programmer’s Model ................................................................................... 6-3

6.4.1 General Purpose Timer............................................................................. 6-4

6.4.1.1 Counter Register .....................................................................................6-4

6.4.1.2 Timer Control Registers........................................................................... 6-4

6.4.1.3 Timer Prescaler Register......................................................................... 6-5

6.4.1.4 Timer-Compare Register......................................................................... 6-5

6.4.1.5 Timer-Capture Register........................................................................... 6-6

6.4.1.6 Timer-Status Register ............................................................................. 6-6

6.4.2 Software Watchdog Timer......................................................................... 6-7

6.4.2.1 Watchdog-Compare Register.................................................................. 6-7

6.4.2.2 Watchdog Counter Register.................................................................... 6-7

6.4.2.3 Watchdog-Control/Status Register (WCR).............................................. 6-7

Section 7

Parallel Ports

7.1 I/O Ports Module.......................................................................................... 7-1

7.1.1 Port Operation........................................................................................... 7-1

7.1.1.1 Basic Port................................................................................................ 7-1

7.1.1.2 Pullup Port............................................................................................... 7-2

7.1.1.3 Interrupt Port ........................................................................................... 7-2

7.1.2 Port A......................................................................................................... 7-3

7.1.3 Port B......................................................................................................... 7-4

7.1.4 Port C .........................................................................................................7-5

7.1.5 Port D ........................................................................................................ 7-6

7.1.6 Port E......................................................................................................... 7-8

7.1.7 Port F......................................................................................................... 7-9

7.1.8 Port G...................................................................................................... 7-10

7.1.9 Port J....................................................................................................... 7-11

7.1.10 Port K....................................................................................................... 7-12

7.1.11 Port M...................................................................................................... 7-14

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MC68328 DRAGONBALL PROCESSOR USER’S MANUAL

xi

Section 8

Universal Asynchronous Receiver/ Transmitter (UART)

8.1 Serial Interface Signals................................................................................ 8-1

8.2 Sub-Block Description.................................................................................. 8-3

8.2.1 Transmitter................................................................................................. 8-3

8.2.2 Receiver..................................................................................................... 8-4

8.2.3 Baud Rate Generator................................................................................. 8-4

8.2.4 MPU Interface............................................................................................ 8-4

8.2.5 UART Control Register.............................................................................. 8-5

8.2.6 Baud Control Register ............................................................................... 8-7

8.2.7 Receiver Register ...................................................................................... 8-9

8.2.8 Transmitter Register ................................................................................ 8-10

8.2.9 Miscellaneous Register............................................................................ 8-12

Section 9

Serial Peripheral Interface— SLAVE (SPIS)

9.1 Overview...................................................................................................... 9-1

9.2 Operation..................................................................................................... 9-1

9.3 Signal Descriptions...................................................................................... 9-2

9.4 SPIS Register .............................................................................................. 9-2

9.4.1 SPI Slave Register..................................................................................... 9-3

Section 10

Serial Peripheral Interface— Master (SPIM)

10.1 Overview.................................................................................................... 10-1

10.2 Operation................................................................................................... 10-1

10.2.1 Operation within SPIM Module................................................................ 10-1

10.2.2 Phase/Polarity Configurations ................................................................. 10-2

10.3 Signal Descriptions.................................................................................... 10-2

10.4 SPIM Registers.......................................................................................... 10-3

10.4.1 SPIM Control/Status Register.................................................................. 10-3

10.4.2 SPIM Data Register................................................................................. 10-5

Section 11

Pulse-Width Modulator

11.1 Overview.................................................................................................... 11-1

11.2 Programmer’s Model.................................................................................. 11-2

11.2.1 PWM Control Register............................................................................. 11-2

11.2.2 Period Register........................................................................................ 11-4

11.2.3 Width Register......................................................................................... 11-4

11.2.4 Counter.................................................................................................... 11-4

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Section 12

Pin Assignment

Section 13

Electrical Characteristics

13.1 Maximum Ratings...................................................................................... 13-1

13.2 Power Consumption .................................................................................. 13-1

13.3 AC Electrical Specification Definitions....................................................... 13-1

13.4 AC Electrical Specifications—Read and Write Cycles............................... 13-1

MOTOROLA

MC68328 DRAGONBALL PROCESSOR USER’S MANUAL

1-1

SECTION 1

MC68328 PROCESSOR OVERVIEW

As the consumer market for portable devices expands, system requirements have become

more demanding. Minimum number of components, smaller board space, lower power con-

sumption, and lower system cost are a few of the criteria necessary for a successful product.

In response to these consumer needs, Motorola has designed a new processor. The

MC68328 DragonBall

TM

integrated portable system processor provides a 3.3V, fully static

operation in an efficient package. The MC68328 processor delivers cost-effective perfor-

mance to satisfy the extensive requirements of today’s consumer market for portable

devices.

The MC68328 processor provides key features that are suitable for many portable applica-

tions. Modules like a real-time clock (RTC), an LCD controller, pulse-width modulator

(PWM), timers, master and slave serial peripheral interface (SPI), universal asynchronous

receiver/transmitter (UART), and the system integration module (SIM28) give the system

engineer more flexibility and resources to design efficient and innovative products.

1.1 KEY FEATURES

The primary features of the MC68328 processor, illustrated in Figure 1, are as follows:

• MC68EC000 Static Core Processor

• 100% Compatibility with MC68000 And MC68EC000 Processors

—24-Bit External and 32-Bit Internal Address Bus

—Optional A31-A24 Capable of 4 Gbytes of Address Space

—16-Bit On-Chip Data Bus for MC68EC000 Bus Operations

—Static Design Allows Processor Clock to Be Stopped for Power Savings

—2.7 MIPS Performance at 16.67-MHz Processor Clock

• Dynamic Bus Sizing Support for Connections to 8-Bit and 16-Bit Devices

• System Integration Module (SIM28) Supporting Glueless System Design:

—System Configuration, Programmable Address Mapping

—Memory Interface for SRAM, EPROM and FLASH Memory

—16 Programmable Peripheral Chip-Selects with Wait-State Generation Logic

—Interrupt Controller with 13 Flexible Inputs

—Programmable Interrupt Vector Generator

—Hardware Watchdog Timer

—Software Watchdog Timer

—Low-Power Mode Control

—Up to 77 Individually Programmable Parallel Port Signals

—PCMCIA 1.0 Support

Overview

1-2

MC68328 DRAGONBALL PROCESSOR USER’S MANUAL

MOTOROLA

• UART

—Supports IrDA-Compliant Physical-Layer Protocol

—8-Byte FIFOs for Rx and Tx

• Two Separate Serial Peripheral Interface Ports (Master and Slave)

—Support For External POCSAG Decoder (Slave)

—Support for Digitizer For A/D Input or EEPROM (Master)

• Dual Channel 16-Bit General-Purpose Counter/Timer

—Multimode Operation, Independent Capture/Compare Registers

—Automatic Interrupt Generation

—240ns Resolution at 16.67-MHz System Clock

—Each Timer Has an Input and an Output Pin for Capture and Compare

• Pulse-Width Modulation Output for Sound Generation

—Programmable Frame Rate

—16-Bit Programmable

—Supports Motor Control

• Real-Time Clock

—24-Hour Time

—1 Programmable Alarm

Figure 1. MC68328 Block Diagram

DUAL

16-BIT

TIMER

MODULE

PWM

MODULE

MC68EC000 HCMOS

STATIC

CORE

UART

WITH

INFRA-RED

SUPPORT

SLAVE

SPI

MASTER

SPI

LCD

CONTROL

MODULE

SYSTEM

INTEGRATION

MODULE

(SIM28)

RTC

INTERRUPT

CONTROLLER

PROCESSOR

CONTROL

PCMCIA 1.0

SUPPORT

CLOCK

SYNTHESIZER

AND

POWER

CONTROL

DYNAMIC BUS SIZING EXTENSION

MC68EC000 INTERNAL BUS

8-/16-Bit

68000 BUS

INTERFACE

PARALLEL I/O PORTS

Overview

MOTOROLA

MC68328 DRAGONBALL PROCESSOR USER’S MANUAL

1-3

• Power Management

—3.3 V Operation

—Fully Static HCMOS Technology

—Programmable Clock Synthesizer for Full Frequency Control

—Low Power Stop Capabilities

—Individual Module Shut Down Capability

—Lowest Power-Mode Control (Shut Down CPU and Peripherals)

• LCD Control Module

—Software Programmable Screen Size to Support Single (Non-Split) Monochrome/

STN Panels

—Direct Drive Capability of Common LCD Drivers/Modules from Motorola and Other

LCD Drive Manufacturers

—Support as Many as 4 Grey Levels

—Use System Memory as Display Memory

• IEEE 1149.1 Boundary Scan Test Access Port (JTAG)

• Operation From DC To 16.67 MHz (Processor Clock)

• Operating Voltage of 3.3V

±

0.3V

• Compact 144-Lead Thin-Quad-Flat-Pack (TQFP) Package

1.1.1 ORGANIZATION

The M68300 family of integrated processors and controllers is built on an M68000 core pro-

cessor and a selection of intelligent peripherals appropriate for a set of applications. Com-

mon system glue logic such as address decoding, wait-state insertion, interrupt

prioritization, and watchdog timing is also included.

Each member of the M68300 family is distinguished from the others by its selection of on-

chip peripherals. Peripherals are chosen to address specific applications but are often use-

ful in a variety of applications. The peripherals may be highly sophisticated timing or protocol

engines that have their own processors, or they may be more traditional peripheral functions

such as UARTs and timers.

1.1.2 ADVANTAGES

The many features incorporated into a single M68300 Family chip help system designers

realize significant savings in design time, power consumption, cost, board space, pin count,

and programming. The equivalent functionality can easily require 20 separate components.

Each component might have 16–64 pins, totalling over 350 connections. Most of these con-

nections require interconnects or are duplications. Each connection: (1) is a candidate for a

bad solder joint or misrouted trace, (2) is another part to qualify, purchase, inventory, and

maintain. Each component (1) requires a share of the printed circuit board, (2) draws power,

which often drives large buffers to get the signal to another chip. The cumulative power con-

sumption of all the components must be available from the power supply. The signals

between the central processor unit (CPU) and a peripheral might not be compatible nor run

from the same clock, which could require time delays or other special design considerations.

In an M68300 family component, the major functions and glue logic are all properly con-

nected internally, timed with the same clock, fully tested, and uniformly documented. Only

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MC68328 DRAGONBALL PROCESSOR USER’S MANUAL

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essential signals are brought out to pins. The primary package is the surface-mount plastic

QFP for the smallest possible footprint.

1.2 MC68328 ARCHITECTURE

To improve total system throughput and reduce component count, board size, and cost of

system implementation, the MC68328 processor integrates a powerful MC68EC000 proces-

sor, intelligent peripheral modules, and typical system interface logic. These functions

include the system integration module (SIM28), timers, LCD controller, and more.

1.2.1 EC000 STATIC CORE

The EC000 core is a core implementation of the M68000 32-bit microprocessor architecture.

The features of the EC000 core processor include:

• Low power, static HCMOS implementation

• 32-bit address bus, 16-bit data bus

• Seventeen 32-bit data and address registers

• 56 powerful instruction types that support high-level development languages

• 14 addressing modes and 5 main data types

• 7 priority levels for interrupt control

The EC000 core is completely upward user code-compatible with all other members of the

M68000 microprocessor families and thus has access to a broad base of established real-

time kernels, operating systems, languages, applications, and development tools.

1.2.1.1 EC000 CORE PROGRAMMING MODEL.

The EC000 core offers sixteen 32-bit

registers and a 32-bit program counter (see Figure 1-1). The first 8 registers (D7–D0) serve

as data registers for byte (8-bit), word (16-bit) and long-word (32-bit) operations. Because

using data registers will affect the condition-code register (which indicates negative number,

carry, and overflow conditions), they (the data registers) are used primarily for data manip-

ulation. The second set of 7 registers (A6–A0) and the user stack pointer (USP) may func-

tion as software stack pointers and base-address registers. These registers can be used for

word and long-word operations and do not affect the condition-code register. All of the reg-

isters (D7–D0 and A6–A0) may serve as index registers.

In supervisor mode, the upper byte of the status register (SR) and the supervisor stack

pointer (SSP) are also available to programmers. These registers are shown in Figure 1-3.

The SR (refer to Figure 1-3) contains the interrupt mask (7 levels available) as well as these

condition codes: extend (X), negative (N), zero (Z), overflow (V), and carry (C). Additional

status bits indicate whether the processor is in trace mode (T-bit) or in supervisor/ user state

(S-bit).

1.2.1.2 DATA TYPES AND ADDRESS MODES.

Five basic data types are supported:

1. Bits

2. Binary-coded decimal (BCD) digits (4 bits)

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3. Bytes (8 bits)

4. Words (16 bits)

5. Long words (32 bits)

In addition, operations on other data types such as memory addresses, status word data,

etc. are provided in the instruction set.

The 14 address modes listed in Table 1-1 include six basic types:

1. Register direct

2. Register indirect

3. Absolute

4. Program counter relative

Figure 1-1. User Programming Model

Figure 1-2. Supervisor Programmer’s Model Supplement

DATA REGISTERS

ADDRESS REGISTERS

31 16 15

8

7

0

USER STACK POINTERA7 (USP)

D0

D1

D2

D3

D4

D5

D6

D7

A0

A1

A2

A3

A4

A5

A6

0151631

31 16 15 0

31 0

0

PC PROGRAM COUNTER

STATUS REGISTERCCR

7

SUPERVISOR STACKA7 (SSP)

31 16 15 0

POINTER

15

0

7

8

SR STATUS REGISTER

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5. Immediate

6. Implied

The register-indirect address modes can perform post-increment, pre-decrement, offset,

and index operations. The program-counter relative mode can be modified through index

and offset operations.

1.2.1.3 INSTRUCTION SET OVERVIEW.

Table 1-2 lists the EC000 core instruction set.

The instruction set supports high-level languages that facilitate programming. Each instruc-

tion, with few exceptions, operates on bytes, words, and long-words, and most instructions

can use any of the 14 address modes. A combination of instruction types, data types, and

address modes provides over 1000 useful instructions. These instructions include signed

and unsigned, multiply and divide, quick arithmetic operations, BCD arithmetic, and

expanded operations (through traps).

1.2.2 SYSTEM INTEGRATION MODULE

The MC68328 SIM28 consists of several functions that control the system startup, initializa-

tion, configuration, and the external bus with a minimum of external devices. The memory

Table 1-1. Address Modes

Address modes Syntax

Register direct address

Data register direct

Address register direct

Dn

An

Absolute data address

Absolute short

Absolute long

xxx.W

xxx.L

Program counter relative address

Relative with offset

Relative with index offset

d

16

(PC)

d

8

(PC, Xn)

Register indirect address register

Register indirect

Postincrement register indirect

Predecrement register indirect

Register indirect with offset

Indexed register indirect with offset

(An)

(An)+

–(An)

d

16

(An)

d

8

(An, Xn)

Immediate data address

Immediate

Quick immediate

#xxx

#1–#8

Implied address

Implied register SR/USP/SP/PC

Legend:

Dn = Data Register

An = Address Register

Xn = Address or Data Register Used as Index Register

SR = Status Register

PC = Program Counter

SP = Stack Pointer

USP = User Stack Pointer

<> = Effective Address

d

8

= 8-Bit Offset (Displacement)

d

16

= 16-Bit Offset (Displacement)

#xxx = Immediate Data

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MC68328 DRAGONBALL PROCESSOR USER’S MANUAL

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interface lets users connect gluelessly with the popular SRAM, EPROM as well as PCMCIA

1.0 memory cards. With the assistance of chip-select logic, wait states can be programma-

ble. The hardware and software watchdog timers help users perform system protections.

The interrupt controller accepts and resolves the priority from internal modules and exter-

Table 1-2. Instruction Set

Mnemonic Description Mnemonic Description

ABCD Add decimal with extend MOVEM Move multiple registers

ADD Add MOVEP Move peripheral data

ADDA Add address MOVEQ Move quick

ADDQ Add quick MOVE from SR Move from status register

ADDI Add immediate MOVE to SR Move to status register

ADDX Add with extend MOVE to CCR Move to condition codes

AND Logical AND MOVE USP Move user stack pointer

ANDI AND immediate MULS Signed multiply

ANDI to CCR AND immediate to condition codes MULU Unsigned multiply

ANDI to SR AND immediate to status register NBCD Negate decimal with extend

ASL Arithmetic shift left NEG Negate

ASR Arithmetic shift right NEGX Negate with extend

Bcc Branch conditionally NOP No operation

BCHG Bit test and change NOT Ones complement

BCLR Bit test and clear OR Logical OR

BRA Branch always ORI OR immediate

BSET Bit test and set ORI to CCR OR immediate to condition codes

BSR Branch to subroutine ORI to SR OR immediate to status register

BTST Bit test PEA Push effective address

CHK Check register against bounds RESET Reset external devices

CLR Clear operand ROL Rotate left without extend

CMP Compare ROR Rotate right without extend

CMPA Compare address ROXL Rotate left with extend

CMPM Compare memory ROXR Rotate right with extend

CMPI Compare immediate RTE Return from exception

DBcc Test cond, decrement and branch RTR Return and restore

DIVS Signed divide RTS Return from subroutine

DIVU Unsigned divide SBCD Subtract decimal with extend

EOR Exclusive OR Scc Set conditional

EORI Exclusive OR immediate STOP Stop

EORI to CCR Exclusive OR immediate to condition codes SUB Subtract

EORI to SR Exclusive OR immediate to status register SUBA Subtract address

EXG Exchange registers SUBI Subtract immediate

EXT Sign extend SUBQ Subtract quick

JMP Jump SUBX Subtract with extend

JSR Jump to subroutine SWAP Swap data register halves

LEA Load effective address TAS Test and set operand

LINK Link stack TRAP Trap

LSL Logical shift left TRAPV Trap on overflow

LSR Logical shift right TST Test

MOVE Move UNLK Unlink

MOVEA Move address — —

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nally generated interrupts and also handles the mask and wake-up selection control for

power control. The low-power logic can control the CPU power dissipation by a frequency

change or stopping it altogether. The SIM28 can also configure the pin to let users select

either dedicated I/O or parallel I/O. This feature helps increase the number of available I/O

ports by reclamation when the dedicated function is not in use.

1.2.2.1 SYSTEM CONFIGURATION.

The MC68328 processor system configuration logic

consists of a system control register (SCR) that lets users configure these major function

operations:

• System status and control logic

• Register double mapping

• Bus error generation control

• Module control registers protection from access by user programs

1.2.2.2 VCO/PLL CLOCK SYNTHESIZER.

The clock synthesizer can operate with either

an external crystal or an external oscillator for reference, using the internal phase-locked

loop (PLL). The other option is for an external clock to directly drive the clock signal at the

operational frequency.

1.2.2.3 CHIP-SELECT LOGIC.

The MC68328 processor provides 16 programmable, gen-

eral-purpose, chip-select signals. For a given chip-select block, users may choose: (1)

whether the chip-select allows read-only or both read and write accesses, (2) whether a

DTACK

is automatically generated for this chip-select, and (3) the number of wait states

(from zero to six) until the DTACK

will be generated.

1.2.2.4 EXTERNAL BUS INTERFACE.

The external bus interface handles the transfer of

information between the internal MC68EC000 core and the memory, peripherals, or other

processing elements in the external address space. It consists of a 16-bit 68000 data bus

interface for internal-only devices and a programmable 8-bit or 16-bit data bus interface to

external devices.

1.2.2.5 INTERRUPT CONTROLLER.

The interrupt controller accepts and prioritizes both

internal and external interrupt requests and generates a vector number during the CPU

interrupt-acknowledge cycle. Interrupt nesting is also provided so that an interrupt service

routine of a lower priority interrupt may be suspended by a higher priority interrupt request.

The on-chip interrupt controller has these major features:

• Prioritized interrupt sources (internal and external)

• Fully nested interrupt environment

• Programmable vector generation

• Unique vector number generated for each interrupt level

• Interrupt masking

• Wakeup interrupt masking

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MC68328 DRAGONBALL PROCESSOR USER’S MANUAL

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1.2.2.6 PARALLEL GENERAL-PURPOSE I/O PORTS.

The MC68328 processor supports

up to 77 bit general-purpose I/O ports that can be configured as general-purpose I/O pins or

as dedicated peripheral-interface pins of the on-chip modules.

Each port pin can be independently programmed as a general-purpose I/O pin even when

other pins related to that on-chip peripheral are used as dedicated pins. If all the pins for a

particular peripheral are configured as general-purpose I/O, the peripheral will still operate

normally, although this is useful only with the RTC and timer modules.

1.2.2.7 SOFTWARE WATCHDOG.

A software watchdog timer protects against system fail-

ures by providing a means of escape from unexpected input conditions, external events, or

programming errors. Once started, the software watchdog timer must be cleared by soft-

ware on a regular basis so that it never reaches its time-out value. When it reaches the time-

out value, the watchdog timer assumes that a system failure has occurred, and the software

watchdog logic resets or interrupts the MC68EC000 core.

1.2.2.8 LOW POWER STOP LOGIC.

Various power-save options are available: turn off

unused peripherals, reduce processor clock speed, disable the processor altogether, or a

combination of these.

A wake-up-from-low-power mode can be achieved by an interrupt at the interrupt controller

logic that runs throughout the period of processor low-power. Programmable interrupt

sources can serve as events to wake up the EC000 core.

The on-chip peripherals can initiate a wake-up; for example, the timer can be set to wake-

up after a certain elapsed time or number of external events.

1.2.3 LCD Controller

• Interfaces with monochrome STN LCD modules

• Up to 4 levels of gray scale through frame rate control

• Use system RAM for display memory

• Screen refresh through DMA

1.2.4 UART and Infrared Communication Support

The UART supports standard asynchronous serial communications at normal baud rates

and is compatible with IrDA Physical Communication Protocol

1.2.5 Real-Time Clock

A 32.76kHz or 38.4kHz crystal (the same as the clock synthesizer clock source) drives the

real-time clock in the MC68328 processor and provides an alarm interrupt.

1.2.6 JTAG Test Access Port

To assist in system diagnostics, the MC68328 processor includes dedicated user-accessi-

ble test logic that is fully compliant with the IEEE 1149.1 standard for boundary-scan test-

ability, often referred to as JTAG (Joint Test Action Group).

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Motorola DragonBall MC68328 User manual

Motorola DragonBall MC68328 User manual

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