NXP MC68328 Reference guide

10/23/98 MC68328 Timing Amendment

MOTOROLA MC68328 Timing Amendment -1

DragonBall LCD Controller Timing

NUM CHARACTERISTIC

3.3V

UNIT

MINIMUM MAXIMUM

1 Line Pulse to Frame Signal 20 —ns

2 Line Pulse Width 300 — ns

3 LCD Data Setup 20 — ns

4 LCD Data Hold 20 — ns

5 Shift Clock to Line Pulse 50 — ns

NOTE: This table contains the assumed active high logic for LFLM, LLP, and LCLK. The active edge is

alternated if the polarity of the corresponding signal is modified.

LFLM

LD[3:0]

LCLK

LLP

Freescale Semiconductor, I

Freescale Semiconductor, Inc.

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ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2005