Motorola MB68k-100 User manual

Brand: Motorola

Model: MB68k-100

Type: User manual

Rev. A

Grant K.

68000 Motherboard User’s Manual Rev. A

Page 2 of 54

TABLE OF CONTENTS

1 INTRODUCTION .......................................................... 4

2 DESIGN MOTIVATION .................................................. 4

3 DESIGN INSPIRATION ................................................. 4

4 WHAT IS A COMPUTER? ............................................... 7

5 THE MB68K-100 COMPUTER ....................................... 13

5.1 MB68k-100 Specification ........................................................13

5.2 What’s What and Where Is It ..................................................15

6 ARCHITECTURAL OVERVIEW ........................................ 15

6.1 Basic Block Level Description .................................................16

6.2 Glimpse of th e 68000..............................................................18

6.3 Bus Architecture of the 68000 ................................................18

6.4 Bus Control Signal Timing .......................................................19

6.4.1 Regular Bus Cycle Termination .............................................19

6.4.2 Bus Termination into a 6800 Bus Cycle .................................22

7 CIRCUIT DESCRIPTION ............................................... 22

7.1 Po wer Input ...........................................................................22

7.1.1 Voltage Regulation ..............................................................23

7.1.2 Active Reversed Connection Protection ...............................23

7.1.3 Discrete Voltage Supervisor ................................................23

7.2 The 68000 Micropro cessor ......................................................24

7.3 The ‘Pintercept’ Headers ........................................................24

7.4 Indica tors ..............................................................................24

7.5 The Sy ste m Clock ....................................................................25

7.6 External Run C ontrol ..............................................................27

7.7 Reset P ulse Generator ............................................................27

7.8 The Start Ve ctor Selector (SVS) ...............................................28

7.9 Address Space Ma pping ..........................................................29

7.10 Data Strobed Flow Logic .......................................................30

7.11 Bus Cycle Termination ..........................................................30

7.11.1 Bus Termination with Auto /DTACK .....................................31

7.11.2 Bus Termination with /VPA .................................................31

7.11.3 Bus Termination with /BERR ...............................................31

7.11.4 Wait State Generator .........................................................32

7.12 On-Board Periphera ls ...........................................................32

7.12.1 Interrupt Enable Register ..................................................33

7.12.2 The Clock Synchronization Re gister ...................................33

7.12.2.1 On-Board Interrupt Logic Level ..................................................... 34

7.12.2.2 The Hardware Entropy Generator .................................................. 34

7.12.2.3 On-Board Digital Input Interface .................................................. 36

68000 Motherboard User’s Manual Rev. A

Page 3 of 54

7.12.3 On-Board Output Latch .......................................................37

7.13 Interrupt Logic .....................................................................37

7.14 On-Board Memory Banks 0/1 ................................................38

7.15 Stack Interface ....................................................................39

7.15.1 Sta ck Interface Connectors ...............................................39

7.15.2 Mounting Holes ..................................................................41

7.16 Quick Jumper Reference .......................................................43

8 THE SOFTER SIDE ...................................................... 46

8.1 Software Development Tools ..................................................46

8.1.1 m6 8k-elf .............................................................................46

8.1.2 EASy68K ..............................................................................47

8.2 MB68k-100 Software Examples ..............................................47

8.3 Software Notes on the MB68k-100 .........................................50

9 GETTING STARTED ...................................................... 51

10 TROUBLESHOOTING .................................................. 52

11 DESIGN ERRATA AND COMMENTARY ............................ 52

12 PROJECT DOCUMENT COMPENDIUM ............................ 54

13 DOCUMENT REVISION HISTORY .................................. 54

68000 Motherboard User’s Manual Rev. A

Page 4 of 54

1 Introduction

This project was born of no less than a childhood dream. Granted this dream had long

been somewhat vague, abstract and surviving well below the threshold of any actual

attention. But the robust desire to develop a 68000 based computer had maintained an

ever-present persistence within my hobbyist heart. And finally events have coalesced

into its fruition.

The MB68k-100 single board computer offers a platform of approachable

experimentation around Motorola’s famed 68000 microprocessor. Whether inspired by

the straightforward elegance of this particular processor at its core or by a more general

interest in computer architecture overall, the MB68k-100’s design philosophy is one to

emphasize clear understanding of the system at every level. With its discrete circuit

design, commented assembly language software examples and rich engineering and

process documentation, the project is intended to offer more than direct utility as an

embedded computer. It is meant as a launching pad, bringing to fruition future

technophile dreams.

2 Design Motivation

As microprocessor technology has advanced over the past decades, an evolving spectrum

of processors has emerged into the marketplace. Examples from the early days of the

technology were stiflingly simple and fraught with debilitating resource limitations and

programming bottlenecks. In contrast, the more contemporary end of this spectrum

presents the highly integrated and massively sophisticated architectures of more recent

years, where the designer grapples with hundreds of pages of product documentation and

hundreds of tiny pins to connect. But along this gradient of microprocessor technology

stands Motorola’s 68000. With an architecture that captures the straightforward

computer designs of its past, this processor is accessible to circuitry that is easily

imagined and built. Yet the 68000 is also a pioneering design in its space, offering a

clear demonstration of the future elegance of orthogonal architecture and spacious

hardware resources. The 68000 is a link, carrying the best features of both old and new

eras of processor technology.

3 Design Inspiration

In an environment of routine obsolesce, the 68000’s continuing 30 year production life

span speaks to the strength of its design. Its portfolio has ranged from advancing the

state-of-the-art upon its 1979 marketplace introduction through to its present day legacy

applications. Its reign includes a generation of top-of-the-line computers and

workstations of the early 1980’s. From there, it evolved to a commanding presence in the

embedded domain of the late 80’s though to the mid 1990’s. Beyond that, its sales

continue today, buried amongst the existing infrastructure of the modern world. And its

68000 Motherboard User’s Manual Rev. A

Page 5 of 54

contemporary incarnations, including the ColdFire and CPU32 families, maintain the

bloodline with a sustaining market share into the future.

Through its life, the 68000 has enjoyed many notable design wins. Among computers, it

was the processor of the original Macintosh systems, the Atari ST and the Commodore

Amiga, among others. Its presence was also known among UNIX workstations,

including the original Sun Microsystems and SGI systems. And it was also the heart of

renowned game consoles, such as the Sega Genesis and Neo Geo systems, as well as

many stand-alone arcade games. It found a home in an array of computer peripherals,

networking equipment and other high-end gadgetry. My own childhood laser printer

succumbed to the screwdriver, yielding a traditional 64-pin PDIP Motorola 68000 at its

core. This processor defined a generation of computing in each market it touched.

From its original design philosophy born

within Motorola of the mid to late 1970’s,

this processor was crafted with an eye

toward the future. The processor design

was conceived under no burden of

confining software backward compatibility.

This forward-looking mindset enabled the

design engineers to “break away from the

past,” as the processor’s User’s Manual

cover art asserts. The first generation

sports a 32-bit architecture, masquerading

in 16-bit hardware. Although later

descendants expanded to true 32-bit form,

the 68000’s 32-bit data and address

registers are siphoned to the outside world

through a 16-bit data bus and 24-bit address

bus. These copious data and address

registers, provide a spacious backdrop to

efficient and elegant software development.

To further this elegance, the instruction set

of the 68000 was designed to be orthogonal, with a highly regular structure. The

instructions had nearly identical access to all addressing modes, moving beyond the

dedicated use of specific registers for specific functions. The 68000 internally features

two parallel 16-bit Arithmetic Logic Units for the fast calculation of addresses. From this

emerges the brilliant selection of available addressing modes, including the pre-

decrement and post-increment capabilities. The dazzling number of address modes takes

getting used to, when approaching with a background either in the primitive 8-bit devices

preceding the 68000 or the frugal RISC designs of today.

The generous selection of 14 addressing modes and impressive count of 56 instruction

types owes thanks to the 68000’s 16-bit data bus. This bus width enables a base op code

of 16-bits, rendering wide flexibility in defining the instruction’s operation. Processor

68000 Motherboard User’s Manual Rev. A

Page 6 of 54

instructions could include additional 16-bit data fetches beyond that to further extend the

operation. For speed, the 68000 employs a Prefetch Queue, where future memory reads

are anticipated and read while the bus would otherwise be idle. This improves

performance in that data may already be available in the processor when the advancing

program operation needs it. And code execution departs from typical technology of the

day in the 68000. It executes code in one of two modes: User or Supervisor. Supervisor

mode allows access to additional operations that are prohibited in User mode. This

enforces a greater degree of security in the code execution, and also maintains separate

User and Supervisor stacks to keep the stacks from having to bare each other’s weight.

Seven levels of interrupts are recognized by the processor, where only higher levels of

priority are permitted to capture current execution. And showing true chivalry for its

power, the 68000 also offers bus arbitration, relinquishing bus mastership to share the

system with other devices upon request.

The 68000’s sophisticated design was born of its advanced implementation in silicon. A

relatively late arrival to the 16-bit processor field, Motorola’s 68000 design was able to

leverage an increased level of integration on silicon. Constructed in superior HMOS

(High Density, Short Channel MOS) technology, the pull-up device in each gate’s output

stage is a heavily doped depletion-mode field effect transistor (FET). This FET initially

operates largely as a current source rather than a simple resistor, allowing for a faster 0-

to-1 transition. This capability in turn translates to faster overall operation. And this

technology, with its 3.5µm feature size, also allowed a higher number of transistors to be

incorporated into the design.

Within its rumored 68,000 transistors, the 68000’s architecture receives additional benefit

from the in-depth analysis by Motorola engineering to tailor an instruction set for

optimum utility. The processor was designed with software in mind. Studying not only

the occurrence of instructions listed within software code but the frequency that they

occur in actual code execution, Motorola engineers included single instructions that fully

embody frequent functionality. An example of this is the Test Condition, Decrement and

Branch family of instructions that tests a condition, and only when false decrements a

counter. Then, only if that counter is not counted down to -1, execution takes the

specified branch. This convoluted function is useful in implementing conditional

software loops where the number of iterations is to be limited. Another example of this

highly-integrated function is the ability within the addressing mode to advance an address

need within software operations on a range of memory to include a separate instruction to

advance that pointer.

68000 Motherboard User’s Manual Rev. A

Page 7 of 54

Many earlier microprocessor

designs implemented their

instructions as sequences

defined directly in digital logic.

The 68000 offers a much richer

functionality within its

instructions through the use of

microcoding. Microcoding

defines the internal sequence to

carry out the instructions. It

does this through the use of

low-level programming

operating within the

microprocessor logic. Like the

drum pegs scrolling through a

music box, this microcoded

program controls the timing

and sequencing of various

parts of the internal

microprocessor logic to

execute the instruction. And

this idea extends further into

the use of nanocoding since

many instructions share

common functions.

Nanocoding implements a

deeper level of execution for

common sequences that appear

within the encoding of different instructions. A picture of the processor die is broken

down in Figure 1, indicating the function of each circuit section. Among the sections are

microcode and nanocode ROMs, control logic and, situated along the bottom, the data

Arithmetic Logic Unit and two address Arithmetic Logic Units.

The power and grace of the 68000 leaves a deep impression on the evolution of computer

and microprocessor technology. And in doing so, it leaves an impression on those with

interest in detailed hardware and software design. As both a historical milestone and a

strong example of approachable modern computing, the 68000 drives continued authority

decades after its inception.

4 What is a computer?

Computers are programmable data processing devices. Central to their function is their

ability to move data internally, and much of the computer’s design is dedicated to this

purpose. Data in a digital computer is represented by binary digits, abbreviated as “bits.”

These bits can possess two possible states, either 0 or 1. This differs from the familiar,

base 10 numeral system, where each digit may be one of ten possibilities. The binary

Figure 1: 68000 Die Function Blocks

Source- BYTE Publications Inc.,

Design Philosophy Behind Motorola’s MC68000,

April 1983

68000 Motherboard User’s Manual Rev. A

Page 8 of 54

numeral system is base 2, meaning that only these two digits are available. In base 2 the

significance of each digit’s place along a binary number differs by a factor of 2. When

written, binary numbers are expressed with a trailing subscript 2. Like in the base 10

system, the number 1

in binary represents a one. This is the ones place in the number,

. But binary 10

represents 2 or 2

, whereas in base 10 system 10

represents the

number ten or 10

. Binary 100

represents 4 or 2

. And 111

is a 7, 2

Another useful numeral system is base 16, known as hexadecimal. Hexadecimal simply

offers the advantage of grouping multiple binary digits together. Since the sixteen

possible combinations of four binary digits may be more concisely represented as a single

hexadecimal digit, hexadecimal is the preferred numeral system for its compactness.

Each hexadecimal digit represents four binary digits, and therefore two hexadecimal

digits represent a single 8-bit byte.

Table 1: Numeral Systems

Base

(Dec)

(Bin)

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01111

10000

(Hex)

As this relates to the computer, these binary digits physically correspond to the voltages

present on the signals within the computer. The digit 1 is typically represented by a high

voltage, while 0 is a low voltage. A succession of numbers over time in a digital system

appears as a signal waveform on the wire, with a separate parallel wire for each digit’s

place.

All data stored and processed in a computer can be thought of as numbers, encoded

through these voltage states. Whatever medium the data represents, it is a number

defined by parallel binary states to the computer. An image, for example, is defined

numerically as an array of values specifying how much red, green and blue to display at

each pixel location. Sound data numerically represents the amount to deflect a speaker

over time, which in turn creates corresponding sound waves. Text is defined numerically

by mapping the alphabet of possible characters to numerical codes. The message text

data is then broken into a string of characters, and the character at each position in that

string is defined by its numerical code. Using the ASCII coding standard as an example,

if 1 is added to the text data for the letter ‘A,’ it becomes a ‘B.’ If 32 is added to ‘A,’ it

becomes ‘a.’ To a computer, the world resolves to nothing more than numbers. These

numbers, though, have different meanings depending on which input or output device

they are associated. But within the computer, the numbers are simply electrical states of

the circuitry, carrying digital information.

68000 Motherboard User’s Manual Rev. A

Page 9 of 54

Table 2: Extended ASCII Code Table

Table 3: ASCII Code Example

Character

ASCII Code

(Hexadecimal)

The hardware in the computer design is responsible for the routing of the digital

information to perform the computer’s operation. For example, the computer may be

controlling multiple elements of a digital light bar output according to the states set on a

series of digital inputs. Each light would be lit according to the pattern provided on the

digital input. In this case the processor reads the input and temporarily stores the

corresponding number. It then writes that number from the temporary storage to the

output circuit. In effect, the computer receives the number presented at the input and

transfers it to the driver circuit for the output.

In this light bar example, shown in Figure 2 below, the read operation consists of the

microprocessor first specifying that it wants to communicate with the digital input circuit.

It does this through its address bus. The address bus is a group of separate parallel wires

that carry the binary digits of the address. And as the name suggests, the address is a

number that uniquely specifies the device with which the processor requests to

communicate. Each device available to the processor has its own unique address. The

processor also sets the Read/Write, R/W ! , signal. The state of this signal indicates

whether the operation being prepared is to be a Read or a Write. These terms are defined

in the sense of the processor: the Read reads data from the addressed device into the

processor, and conversely the Write writes data from the processor to the addressed

device. With the digital input circuit addressed and direction specified as Read, the

processor next issues the Address Strobe. This signal indicates to the system’s external

logic that the processor has finished setting up the signals for the operation, and the logic

may now begin serving the processor’s request. The system’s external decoding logic

then processes the request and signals to the addressed device that it is selected. That

device then recognizes in a Read cycle that it must report its data to the processor. The

processor and addressable device share another group of parallel connections for this

purpose, the Data Bus. After the data is established on the Data Bus by the device being

read, the external logic finally informs the microprocessor that its data is ready by

sending an acknowledgment signal to the processor. The processor then reads the data

from the Data Bus and moves on to the next operation.

68000 Motherboard User’s Manual Rev. A

Page 10 of 54

Figure 2: Data Flow Diagrams, Read

The mechanics of the Write operation, shown in Figure 3 below, closely follow the Read.

The target device is specified by its address. But the Read/Write line here indicates a

Write operation is to be executed. The Data Bus this time is driven by the processor with

the data to be written to target. The target device is selected by the decoding logic based

on its address, and it reads the data from the processor. The cycle is then closed with the

processor receiving the acknowledge signal that the Write operation is complete. In this

example, the light bar output driver is updated by the processor. Through these steps, the

input data is transferred to the light bar output.

Figure 3: Data Flow Diagrams, Write

The devices within the computer are organized under the control of the microprocessor.

The processor addresses the device required for the current operation, completes the data

transaction with that device and then continues to the next operation. The sequence of

operations that the microprocessor follows is the software program. The program is

comprised of a series of steps that coordinate the computer’s operation. These steps are

selected from among the set of basic functions that are directly executed by the processor.

Examples of these fundamental operations include reading data from memory or an input

device, doing arithmetic operations on data, making decisions on which part of the

program to execute next, and writing data to memory or output devices, to name a few.

68000 Motherboard User’s Manual Rev. A

Page 11 of 54

These basic functions are the microprocessor instructions. Microprocessor instructions

are the most fundamental building blocks of any program. Any program is composed of

these individual steps that are carried out directly in the computer hardware. The specific

vocabulary of these primitive program operations is defined by the particular

microprocessor in use. This vocabulary is referred to as the instruction set of the

processor. Although largely comparable in the suite of available functions, each

processor architecture’s instruction set is unique. Frequently encountered instructions

include arithmetic operations, like ADD, SUB or Boolean logic operations like AND, OR

and NOT. Program flow is controlled with conditional branch instructions that choose

the program’s next step based on data comparisons, such as ‘Branch if EQual,’ BEQ,

which only redirects program execution to the specified branch location if data compared

in a previous instruction has signaled a match. Data may be transferred between the

processor, memory and peripheral devices with the wide range of MOVE instructions.

Each processor has its own flavor of these basic functions.

Other aspects of the processor’s design are unique to its architecture. Another example

of this is the processor’s registers. Registers function as the short-term memory of the

processor, operating very fast and being directly accessible by the majority of processor

instructions. While the computer’s expansive RAM memory may be used for storing

large amounts of data being operated on, the registers keep immediate track of the

algorithm being executed. A register may be thought of as memory for a single, general-

purpose variable held within the processor. In practice, many microprocessor

instructions that make up a typical program involve performing arithmetic and

comparison operations on register data, as well as moving data between those registers

and devices of the Data Bus, such as system memory or peripheral devices.

The program snippet in Table 4 below provides an assembly language example of

microprocessor instruction coding. Assembly language is a convenient means of writing

the program’s processor instructions in an easily readable form, since the actual program

instructions exist as numerical codes. Assembly language coding is made up of the

individual instructions of the program. Each instruction defines the basic operation at

that step in the program to perform. The type of basic operation is indicated by the

instruction mnemonic, such as whether the step is to transfer data, perform an arithmetic

operation or redirect the sequence of program execution. The instruction may also

include operands to indicate on what to operate. Operands may include registers or

memory locations to be used in the operation, or numeric data to be incorporated into the

operation. The actual numerical codes interpreted by the microprocessor are referred to

as Op Codes. This snippet demonstrates some initialization functions typical at the start

of a program.

Note that labels are used in place of numerical data in some places in the assembly code

listing, such as references to ONBD_BANK0 for the starting address of on-board RAM

or ONBD_BANK0_SZ for the size of that on-board RAM. These labels allow a

symbolic representation of a number for improved readability.

68000 Motherboard User’s Manual Rev. A

Page 12 of 54

Table 4: Initialization Example with Assembly Language

+Offset

Op Code

Instruction

Mnemonic

Source Operand

Destination

Operand

Comment

…

+00

2E7C

00004000

MOVEA.L

#(ONBD_BANK0+

ONBD_BANK0_SZ),

;

supervisor

stack at

top of on-

board

SRAM

+06

207C

00003C00

MOVEA.L

#(ONBD_BANK0+

ONBD_BANK0_SZ-

ONBD_SUPSTCK_SZ),

+0C

4E60

MOVE.L

A0,

USP

; user

stack next

in on-

board

SRAM

+0E

46FC

0000

MOVE.W

#$0000,

; enter

user mode

and set up

interrupt

mask for

level 0

+12

13FC

00FE

000A0000

MOVE.B

#$FE,

ONBD_INTEN

; enable

interrupts

hardware

…

68000 Motherboard User’s Manual Rev. A

Page 13 of 54

5 The MB68k-100 Computer

The MB68k-100 is a single board computer based on the Motorola 68000

microprocessor. It offers many on-board features and is highly configurable via its

multitude of jumpers and circuit access points. It also includes expansion capabilities

through its stackable daughter board interface.

5.1

MB68k-100 Specification

Table 5: MB68k-100 Specification Table

Applications:

• Real-time Embedded Control

• Education and Training

• Retro design support

• Nostalgia

• Satiation of Fervent Hobbyist

Impulse

Features:

! Full User’s Documentation seen here

! Full Process Documentation

! Extensive Access to Design Information

! Rich Example Software with Commenting

! Versatile On-Board Configurability

! Facilities for Signal Interception and Test Points

! Power Conditioning

! Supply Voltage Supervisory Function

! Indicators for Halt, Reset, Run and Power

! Multiple, Selectable Clock Sources

! Run Control with External, Power-Up and Push-Button Resets

! Selectable Reset Vector Address

! Configurable Address Decoding

! Bus Cycle Management

! Bus Error Detection

! 6800 Peripheral Compatibility

! Wait State Generation

! Hardware Entropy Generation for Random Data

! Digital Inputs

! Digital Outputs with Light Bar

! Interrupt Logic with Autovectoring

! Memory Expansion Sockets

! Stack Connectors for Expandability

! Flexible Mounting Options

68000 Motherboard User’s Manual Rev. A

Page 14 of 54

Table 6: Recommended and Absolute Ratings Guidelines*

Rating

Condition

Value

Unit

System Clock, maximum

as tested

MHz

Supply Current, typ

CLK

= 10MHz

< 450

Voltage Regulation bypassed

+5.12

VDC

Voltage Regulation,

VR120 installed with 7805

7.2

VDC

Supply Voltage, minimum

Voltage Regulation,

VR120 installed with PT5101

9.2

VDC

Voltage Regulation bypassed

5.3

VDC

Voltage Regulation,

7805 power limit

~12

VDC

Supply Voltage, maximum

Voltage Regulation,

PT5101 Input Voltage Limit

VDC

Operating Temperature

Lower limit by ICs,

Upper limit by Power Input

Circuitry Temperature

0 - 30

°C

Footprint

12” x 10”

in.

* all limits listed here are subject to engineering review per application for additional flexibility.

68000 Motherboard User’s Manual Rev. A

Page 15 of 54

5.2

What’s What and Where

Is It

The overlay below maps some basic circuit sections of the MB68k-100 board.

Figure 4: MB68k-100 Block Overlay

6 Architectural Overview

Much of the machinery of the computer design focuses on the movement of data – the

lifeblood of the computer’s operation. The computer’s microprocessor, being the

coordinator of this operation, takes part in much of this information flow. And the

arteries of this flow are the computer’s networks of buses, all managed by its control

logic.

The complex design of a computer system naturally breaks down into a collection of

modules, each serving a straightforward and simple function. Here that breakdown is

explored.

SVS

Stack Connector

'Pintercept'

68000

Glue

Logic

Strobe Logic

Wait State

Stack Connector

Reset Pulse

Auto

DTACK

On-Board

Block

Bank 0

Bank 1

Bus Error

Indicators

Block

Address

Decoder

On-Board Decode

Output Latch

Clock Sync

Interrupt Logic

Power Input

Reverse Prot

Osc Modules

Symmetry

Freq Div

Discrete

Osc

Clock Cfg

Voltage Supervisor

Voltage Reg

Entropy Gen

68000 Motherboard User’s Manual Rev. A

Page 16 of 54

6.1

Basic Block Level Description

The computer’s basic framework builds around common electrical pathways called

buses. These are groups of parallel wires that serve to convey bits of information in

parallel throughout the computer system. Devices within the computer cooperate to share

these common pathways in order to communicate with each other. The two central

pathways are the Data and Address Buses. The Data Bus is a multiplexed medium to

carry data between devices within the computer. This data might be input from or output

to interfaces of the computer. Or it may be values accessed in the computer’s RAM or

program instruction codes that define the operation of the system from ROM.

Meanwhile, the Address Bus performs the crucial task of specifying which device is

involved in the data transfer that is taking place on the Data Bus. These transfers are

controlled by another group of signals, collectively known as the Control Bus. Though

not parallel in function, like the groups of lines in the Data and Address Buses, these

individual control signals coordinate the timing and sequencing of the data transfer that is

taking place over the course of the bus cycle. Collectively, these signals indicate the

current state of the data transfer sequence.

Figure 5 below depicts a greatly simplified (and willfully incomplete) block diagram of

the MB68k-100 motherboard’s architecture. The interrupt logic, for example, is

completely neglected. But the purpose is to give a superficial primer of the basic system

operation.

68000 Motherboard User’s Manual Rev. A

Page 17 of 54

Figure 5: Rudimentary Architecture Block Diagram

In brief, the following conceptually outlines the basic mechanics of a bus cycle:

1. The microprocessor sets up the Address Bus, Read/Write data direction and, for a

Write operation, the Data Bus.

2. The microprocessor issues the Address Strobe signal, indicating that its outputs

are established for the bus transaction.

3. The Block Address Decoder and other Decode Logic issue the appropriate

signaling to enable the selected device.

4. Also in parallel, the Data Strobed Flow Logic issues the appropriate Read and

Write enable signals for the devices on the data bus according to the direction of

required data flow.

5. The selected device responds to participate in the bus transaction. For a Read

operation, the device places the requested data onto the Data Bus. For a Write

operation, the device receives the data that has been placed on the bus by the

microprocessor.

6. The Timing Logic, in parallel, provides sufficient time for the selected device to

respond in step 5. It then issues the acknowledgement that the transaction is

complete to the microprocessor.

68000 Motherboard User’s Manual Rev. A

Page 18 of 54

6.2

Glimpse of the 68000

With greater detail coming into focus, refer to Figure 6 showing the signals of the 68000

microprocessor. The pin diagram of the DIP chip is also given in Figure 7 for reference.

The Data and Address buses are shown, as well as the various control signaling. The

functions and interactions of these signals are discussed in subsequent sections. For

deeper detail, refer to the Motorola M68000 8-/16-/32-bit Microprocessors User’s

Manual.

Figure 6: 68000 Input and Output

Signals

Figure 7: 68000 DIP Pin Diagram

6.3

Bus Architecture of the 68000

The 16-bit 68000 data bus is comprised of two conjoined 8-bit data buses. They are

referred to as the upper and lower data buses, or informally the ‘hi’ and ‘lo.’ The upper

bus carries the most significant byte data (D8-15), and the lower carries the least

significant byte (D0-D7). Since the 68000 uses a big-endian byte ordering convention,

lower addresses are associated with bytes of higher significance. That is, the high bytes

reside in the ‘hi’ device, and occupy the lower memory address. The low bytes reside in

the ‘lo’ device, and occur in the higher memory address.

Table 7: 68000 Byte Ordering Convention, Big-Endian

Address

Even

Odd

Significance

MSB

LSB

Data Lines

D15-D8

D7-D0

Control Line

/UDS

/LDS

Device

‘Hi’

‘Lo’

68000 Motherboard User’s Manual Rev. A

Page 19 of 54

The 68000 specifies the device to target for the bus transfer through its 24-bit addressing

scheme. The direction of the bus transfer, being either a Read of data into the processor

or a Write from the processor, is indicated through the Read/Write signal. The state of

this signal specifies whether the bus cycle is read or write, as defined relative to the

processor. With these signals established, the Address Strobe signal, /AS, is asserted.

This signals the target device and associated bus logic that address decoding may begin.

The address bus consists only of address bits A1-A23. It carries no A0 bit to distinguish

between the odd and even byte addresses that pair to make up the 16-bit data word. The

distinction between these is made though control signals /UDS and /LDS, the upper and

lower data strobes. The /UDS signal is asserted to include the most significant byte

(MSB) at the lower address, and /LDS is asserted to include the least significant byte

(LSB) at the next adjacent address. When the operation is 16-bit, both are asserted

together. This addressing mechanism is well suited to 16-bit buses that are typically

implemented as paired 8-bit devices.

6.4

Bus Control Signal Timing

Timing is everything. When negotiating the complex flow of data traffic, careful

management of the computer’s many interconnected devices is crucial.

6.4.1

Regular Bus Cycle Termination

Many microprocessors of the 1970’s operated more slowly than the peripheral and

memory devices with which they typically interfaced, so these processors simply initiated

a read or write operation at one phase in the bus cycle and unconditionally completed that

operation at a later phase in the cycle. This imposed an external limit on the processor

speed, in that the bus device must have completed its operation before the bus cycle

unconditionally closed along with the advancing system clock. The 68000, however, is

designed to decouple its clock speed from the speed of devices on the bus. It does this

through use of an acknowledge signal returned from the external logic that indicates to

the processor the completion of the bus operation. This handshaking signal is called the

Data Transfer Acknowledge. It uses negative logic and is abbreviated as /DTACK.

Motorola’s microprocessor literature refers to this means of bus control as asynchronous.

Read cycles require that the data has arrived and stabilized on the data bus before the

/DTACK signal is asserted. The requirement, therefore, is that the delay in generating

the /DTACK signal be greater than the delay in establishing the valid Read data on the

bus. This way, the processor is signaled that the data is available for it to proceed only

after the data signals are in fact available. But one exception arises here. Since /DTACK

is only examined on falling edges of the processor clock, this strict requirement is relaxed

if the two events do not straddle a falling clock edge. That is, if the data bus and

/DTACK signals are guaranteed to occur within the same clock period, with no falling

68000 Motherboard User’s Manual Rev. A

Page 20 of 54

clock edge between them, then no sequencing order is required. Put simply, data on the

data bus must be established for the first falling clock edge once /DTACK is asserted.

Write cycles require that the data on the bus be maintained by the processor for long

enough to meet the hold time write requirement of the target device. As with the Read

cycle, the processor examines /DTACK on the falling edge of the clock to close the Write

cycle. /DTACK control logic must therefore provide sufficient delay for the memory

device’s write operation to complete after the bus control signals from the processor are

issued. Unlike the one and a half clock periods available in the Read cycle before the

/DTACK signal is first checked, the Write cycle provides only one half of a clock cycle

before first examination of /DTACK to end the bus cycle. However, the write data and

control signals remain present for one clock cycle after termination of the bus cycle,

providing a total of one and a half clock periods for the memory device to complete its

internal write operation. The total time available for the target device, therefore, is again

one and a half clock periods.

Since memory devices tend to be slow, care must be taken that the /DTACK signal does

not prematurely close the bus cycle. On a Read cycle, the processor first checks

/DTACK’s state one and a half clock cycles after the processor has set up the control

signals. This allows that much time for the addressed device to present its valid data onto

the bus, before special timing control is needed for /DTACK. On a Write cycle, only one

half of a clock cycle elapses before /DTACK is tested to close the cycle. However,

because the write data and control signals remain valid for a clock cycle after termination

of the bus cycle, the time available to the bus device without special /DTACK timing

provisions is also one and a half clock cycle periods.

Because the 68000 bus architecture uses the /DTACK termination signal to close the bus

cycle, the speed of the devices on the bus places no constraint on the maximum processor

clock frequency. However, the bus throughput is optimized with a bus design that

minimizes the need for processor wait states. Wait states are inserted by the processor

while interfacing with the memory device when the /DTACK signal is not asserted upon

the falling edge of the processor clock. To incur no wait states, Read and Write cycles

must complete within one and a half clock cycles. This period starts from the set up of

all bus control signals and ends upon assertion of the /DTACK signal.

Delving deeper into bus cycle timing details, the processor state over the bus cycle

changes on each phase of the clock signal. In a Read cycle, as seen in Figure 8 below,

the address lines (A1-A23) are established at the falling edge starting state S1. The

remaining control signals (/AS, /UDS, /LDS & R/W ! ) are established at the rising edge

starting processor state S2. External bus circuitry may now complete the cycle. The

cycle termination signals are next checked by the processor at the falling edge at the end

of state S4. This provides a window of one and a half clock periods to complete the cycle

without requiring wait states. In a Write cycle, shown in Figure 9 below, A1-A23 are set

up at the start of S1, /AS and R/W ! are set up in S2, and then /UDS and /LDS are set up

on the rising edge starting state S4. As with the Read cycle, termination is next checked

at the falling edge closing state S4. This provides a window of only half of a clock

Page is loading ...

Motorola MB68k-100 User manual

Motorola MB68k-100 User manual

Motorola MB68k-100 User manual

Related papers

Other documents