Silicon Labs EFM32WG Reference guide

EFM32WG Reference Manual

The EFM32 Wonder Gecko MCUs are the world’s most energy-

friendly microcontrollers.

The EFM32WG offers unmatched performance and ultra low power consumption in both

active and sleep modes. EFM32WG devices consume as little as 0.65 μA in Stop mode

and 225 μA/MHz in Run mode. It also features autonomous peripherals, high overall chip

and analog integration, and the performance of the industry standard 32-bit ARM Cortex-

M4 processor, making it perfect for battery-powered systems and systems with high-per-

formance, low-energy requirements.

EFM32WG applications include the following:

KEY FEATURES

• ARM Cortex-M4 at 48 MHz

• Ultra low power operation

• 0.65 μA current in Stop (EM3), with

CRYOTIMER and RAM retention

• 63 μA/MHz in EM1

• 225 μA/MHz in Run mode (EM0)

• Fast wake-up time of 2 us

• Hardware cryptography (AES)

• Up to 256 kB of Flash and 32 kB of RAM

• Smart metering

• Water metering

• Gas metering

• Industrial and home automation

• Alarm and security systems

• Health and fitness applications

32-bit bus

Lowest power mode with peripheral operational:

EM2 – Deep Sleep

EM1 - Sleep EM4S - Shutoff

EM0 - Active

EM3 - Stop

Core / Memory

Flash Program

Memory

RAM Memory

ARM Cortex

TM

M4 processor

with FPU and

MPU

Debug Interface

with ETM

DMA Controller

Memory

Protection Unit

Other

Hardware AES

Energy Management

Brown-Out

Detector

Voltage

Regulator

Voltage

Comparator

Power-On Reset

Clock Management

High Frequency

RC Oscillator

Ultra Low Freq.

RC Oscillator

Low Frequency

Crystal Oscillator

Low Frequency

RC Oscillator

Auxiliary High

Freq. RC Osc.

High Frequency

Crystal Oscillator

Analog Interfaces

LCD Controller

Operational

Amplifier

ADC

DAC

Analog

Comparator

Backup Domain

Peripheral Reflex System

Serial Interfaces

UART

I

2

C

USB

I/O Ports Timers and Triggers

LESENSE

Timer/Counter

Low Energy Timer

Watchdog Timer

Back-Up RTC

External

Interrupts

Pin Reset

External Bus

Interface

General

Purpose I/O

Pin Wakeup

TFT Driver

Pulse Counter

Real Time Counter

USART

Low Energy

UART

TM

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Table of Contents

1. Energy Friendly Microcontrollers .......................24

1.1 Typical Applications ............................24

1.2 EFM32WG Development ..........................24

2. About This Document ...........................25

2.1 Conventions ..............................25

2.2 Related Documentation ..........................26

3. System Overview .............................27

3.1 Introduction...............................27

3.2 Features................................28

3.3 Block Diagram..............................30

3.4 Energy Modes..............................30

3.5 Product Overview ............................32

3.6 Device Revision .............................35

4. System Processor ............................36

4.1 Introduction...............................36

4.2 Features................................37

4.3 Functional Description ...........................37

4.3.1 Interrupt Operation ..........................38

5. Memory and Bus System ..........................40

5.1 Introduction...............................41

5.2 Functional Description ...........................42

5.2.1 Bit-Banding.............................43

5.2.2 Peripherals .............................45

5.2.3 Bus Matrix .............................47

5.2.4 Access to Low Energy Peripherals (Asynchronous Registers)............48

5.2.5 Flash ...............................50

5.2.6 SRAM ..............................51

5.2.7 Device Information (DI) Page.......................52

6. DBG - Debug Interface ...........................54

6.1 Introduction...............................54

6.2 Features................................54

6.3 Functional Description ...........................54

6.3.1 Debug Pins.............................55

6.3.2 Embedded Trace Macrocell v3.5 (ETM) ...................55

6.3.3 Debug and EM2/EM3 .........................55

6.3.4 Debug Lock and Device Erase ......................56

6.4 Register Map ..............................57

6.5 Register Description ............................58

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6.5.1 AAP_CMD - Command Register .....................58

6.5.2 AAP_CMDKEY - Command Key Register ..................58

6.5.3 AAP_STATUS - Status Register .....................59

6.5.4 AAP_IDR - AAP Identification Register ...................59

7. MSC - Memory System Controller....................... 60

7.1 Introduction...............................60

7.2 Features................................61

7.3 Functional Description ...........................61

7.3.1 User Data (UD) Page Description .....................62

7.3.2 Lock Bits (LB) Page Description......................62

7.3.3 Device Information (DI) Page.......................62

7.3.4 Post-Reset Behavior .........................62

7.3.5 Erase and Write Operations .......................65

7.4 Register Map ..............................66

7.5 Register Description ............................67

7.5.1 MSC_CTRL - Memory System Control Register ................67

7.5.2 MSC_READCTRL - Read Control Register .................68

7.5.3 MSC_WRITECTRL - Write Control Register .................69

7.5.4 MSC_WRITECMD - Write Command Register ................70

7.5.5 MSC_ADDRB - Page Erase/Write Address Buffer ...............71

7.5.6 MSC_WDATA - Write Data Register ....................71

7.5.7 MSC_STATUS - Status Register .....................72

7.5.8 MSC_IF - Interrupt Flag Register .....................73

7.5.9 MSC_IFS - Interrupt Flag Set Register ...................73

7.5.10 MSC_IFC - Interrupt Flag Clear Register ..................74

7.5.11 MSC_IEN - Interrupt Enable Register ...................74

7.5.12 MSC_LOCK - Configuration Lock Register .................75

7.5.13 MSC_CMD - Command Register ....................76

7.5.14 MSC_CACHEHITS - Cache Hits Performance Counter .............76

7.5.15 MSC_CACHEMISSES - Cache Misses Performance Counter ...........77

7.5.16 MSC_TIMEBASE - Flash Write and Erase Timebase ..............77

7.5.17 MSC_MASSLOCK - Mass Erase Lock Register ...............78

8. DMA - DMA Controller ...........................79

8.1 Introduction...............................79

8.2 Features................................80

8.3 Block Diagram..............................81

8.4 Functional Description ...........................82

8.4.1 Channel Select Configuration ......................82

8.4.2 DMA Control ............................83

8.4.3 Channel Control Data Structure ......................96

8.4.4 Looped Transfers .........................106

8.4.5 2D Copy.............................107

8.4.6 Interaction with the EMU .......................107

8.4.7 Interrupts ............................108

8.4.8 Examples ............................108

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8.5 Register Map .............................109

8.6 Register Description ...........................110

8.6.1 DMA_STATUS - DMA Status Registers ..................110

8.6.2 DMA_CONFIG - DMA Configuration Register ................111

8.6.3 DMA_CTRLBASE - Channel Control Data Base Pointer Register .........111

8.6.4 DMA_ALTCTRLBASE - Channel Alternate Control Data Base Pointer Register ....112

8.6.5 DMA_CHWAITSTATUS - Channel Wait on Request Status Register ........113

8.6.6 DMA_CHSWREQ - Channel Software Request Register ............114

8.6.7 DMA_CHUSEBURSTS - Channel Useburst Set Register ............115

8.6.8 DMA_CHUSEBURSTC - Channel Useburst Clear Register ...........117

8.6.9 DMA_CHREQMASKS - Channel Request Mask Set Register ..........118

8.6.10 DMA_CHREQMASKC - Channel Request Mask Clear Register .........119

8.6.11 DMA_CHENS - Channel Enable Set Register ...............120

8.6.12 DMA_CHENC - Channel Enable Clear Register ..............121

8.6.13 DMA_CHALTS - Channel Alternate Set Register ..............122

8.6.14 DMA_CHALTC - Channel Alternate Clear Register .............123

8.6.15 DMA_CHPRIS - Channel Priority Set Register ...............124

8.6.16 DMA_CHPRIC - Channel Priority Clear Register ..............125

8.6.17 DMA_ERRORC - Bus Error Clear Register ................126

8.6.18 DMA_CHREQSTATUS - Channel Request Status ..............127

8.6.19 DMA_CHSREQSTATUS - Channel Single Request Status ...........129

8.6.20 DMA_IF - Interrupt Flag Register ...................131

8.6.21 DMA_IFS - Interrupt Flag Set Register ..................133

8.6.22 DMA_IFC - Interrupt Flag Clear Register .................134

8.6.23 DMA_IEN - Interrupt Enable register ..................135

8.6.24 DMA_CTRL - DMA Control Register ..................136

8.6.25 DMA_RDS - DMA Retain Descriptor State ................137

8.6.26 DMA_LOOP0 - Channel 0 Loop Register .................138

8.6.27 DMA_LOOP1 - Channel 1 Loop Register .................139

8.6.28 DMA_RECT0 - Channel 0 Rectangle Register ...............139

8.6.29 DMA_CHx_CTRL - Channel Control Register ...............140

9. RMU - Reset Management Unit ........................144

9.1 Introduction..............................144

9.2 Features...............................144

9.3 Functional Description ..........................145

9.3.1 RMU_RSTCAUSE Register ......................146

9.3.2 Power-On Reset (POR) .......................147

9.3.3 Brown-Out Detector Reset (BOD) ....................147

9.3.4 RESETn Pin Reset .........................147

9.3.5 Watchdog Reset ..........................148

9.3.6 Lockup Reset ...........................148

9.3.7 System Reset Request ........................148

9.3.8 EM4 Reset ............................148

9.3.9 EM4 Wakeup Reset .........................148

9.4 Register Map .............................148

9.5 Register Description ...........................149

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9.5.1 RMU_CTRL - Control Register .....................149

9.5.2 RMU_RSTCAUSE - Reset Cause Register ................150

9.5.3 RMU_CMD - Command Register ....................151

10. EMU - Energy Management Unit .......................152

10.1 Introduction .............................152

10.2 Features ..............................152

10.3 Functional Description .........................153

10.3.1 Energy Modes ..........................154

10.3.2 Entering a Low Energy Mode .....................157

10.3.3 Leaving a Low Energy Mode .....................158

10.3.4 Backup Power Domain .......................159

10.4 Register Map.............................163

10.5 Register Description ..........................164

10.5.1 EMU_CTRL - Control Register ....................164

10.5.2 EMU_LOCK - Configuration Lock Register ................165

10.5.3 EMU_AUXCTRL - Auxiliary Control Register ...............165

10.5.4 EMU_EM4CONF - Energy Mode 4 Configuration Register ...........166

10.5.5 EMU_BUCTRL - Backup Power configuration register ............167

10.5.6 EMU_PWRCONF - Power Connection Configuration Register ..........168

10.5.7 EMU_BUINACT - Backup Mode Inactive Configuration Register .........169

10.5.8 EMU_BUACT - Backup mode active configuration register ...........170

10.5.9 EMU_STATUS - Status register ....................171

10.5.10 EMU_ROUTE - I/O Routing Register ..................171

10.5.11 EMU_IF - Interrupt Flag Register ...................172

10.5.12 EMU_IFS - Interrupt Flag Set Register .................172

10.5.13 EMU_IFC - Interrupt Flag Clear Register ................173

10.5.14 EMU_IEN - Interrupt Enable Register .................173

10.5.15 EMU_BUBODBUVINCAL - BU_VIN Backup BOD calibration ..........174

10.5.16 EMU_BUBODUNREGCAL - Unregulated power Backup BOD calibration .....174

11. CMU - Clock Management Unit .......................175

11.1 Introduction .............................175

11.2 Features ..............................175

11.3 Functional Description .........................176

11.3.1 System Clocks ..........................177

11.3.2 Oscillator Selection ........................179

11.3.3 Oscillator Configuration .......................181

11.3.4 Configuration For Operating Frequencies .................185

11.3.5 Output Clock on a Pin ........................185

11.3.6 Protection ............................185

11.4 Register Map.............................186

11.5 Register Description ..........................187

11.5.1 CMU_CTRL - CMU Control Register ..................187

11.5.2 CMU_HFCORECLKDIV - High Frequency Core Clock Division Register ......190

11.5.3 CMU_HFPERCLKDIV - High Frequency Peripheral Clock Division Register .....191

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11.5.4 CMU_HFRCOCTRL - HFRCO Control Register ..............192

11.5.5 CMU_LFRCOCTRL - LFRCO Control Register ...............193

11.5.6 CMU_AUXHFRCOCTRL - AUXHFRCO Control Register ...........194

11.5.7 CMU_CALCTRL - Calibration Control Register ...............195

11.5.8 CMU_CALCNT - Calibration Counter Register ...............196

11.5.9 CMU_OSCENCMD - Oscillator Enable/Disable Command Register ........197

11.5.10 CMU_CMD - Command Register ...................198

11.5.11 CMU_LFCLKSEL - Low Frequency Clock Select Register ...........199

11.5.12 CMU_STATUS - Status Register ...................201

11.5.13 CMU_IF - Interrupt Flag Register ...................203

11.5.14 CMU_IFS - Interrupt Flag Set Register .................204

11.5.15 CMU_IFC - Interrupt Flag Clear Register ................205

11.5.16 CMU_IEN - Interrupt Enable Register .................206

11.5.17 CMU_HFCORECLKEN0 - High Frequency Core Clock Enable Register 0 .....207

11.5.18 CMU_HFPERCLKEN0 - High Frequency Peripheral Clock Enable Register 0 ....208

11.5.19 CMU_SYNCBUSY - Synchronization Busy Register .............210

11.5.20 CMU_FREEZE - Freeze Register ...................211

11.5.21 CMU_LFACLKEN0 - Low Frequency A Clock Enable Register 0 (Async Reg) ....212

11.5.22 CMU_LFBCLKEN0 - Low Frequency B Clock Enable Register 0 (Async Reg) ....212

11.5.23 CMU_LFAPRESC0 - Low Frequency A Prescaler Register 0 (Async Reg) .....213

11.5.24 CMU_LFBPRESC0 - Low Frequency B Prescaler Register 0 (Async Reg) .....215

11.5.25 CMU_PCNTCTRL - PCNT Control Register ...............216

11.5.26 CMU_LCDCTRL - LCD Control Register ................217

11.5.27 CMU_ROUTE - I/O Routing Register ..................218

11.5.28 CMU_LOCK - Configuration Lock Register ................219

12. WDOG - Watchdog Timer .........................220

12.1 Introduction .............................220

12.2 Features ..............................220

12.3 Functional Description .........................220

12.3.1 Clock Source ..........................221

12.3.2 Debug Functionality ........................221

12.3.3 Energy Mode Handling .......................221

12.3.4 Register Access..........................221

12.4 Register Map.............................221

12.5 Register Description ..........................222

12.5.1 WDOG_CTRL - Control Register (Async Reg) ...............222

12.5.2 WDOG_CMD - Command Register (Async Reg) ..............224

12.5.3 WDOG_SYNCBUSY - Synchronization Busy Register ............225

13. PRS - Peripheral Reflex System .......................226

13.1 Introduction .............................226

13.2 Features ..............................226

13.3 Functional Description .........................226

13.3.1 Asynchronous Mode ........................227

13.3.2 Channel Functions .........................227

13.3.3 Producers ............................228

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13.3.4 Consumers ...........................230

13.3.5 Example ............................231

13.4 Register Map.............................231

13.5 Register Description ..........................232

13.5.1 PRS_SWPULSE - Software Pulse Register ................232

13.5.2 PRS_SWLEVEL - Software Level Register ................233

13.5.3 PRS_ROUTE - I/O Routing Register ..................234

13.5.4 PRS_CHx_CTRL - Channel Control Register ...............235

14. EBI - External Bus Interface ........................240

14.1 Introduction .............................240

14.2 Features ..............................240

14.3 Functional Description .........................241

14.3.1 Non-Multiplexed 8-Bit Data, 8-Bit Address Mode ...............243

14.3.2 Multiplexed 16-bit Data, 16-bit Address Mode ................244

14.3.3 Multiplexed 8-Bit Data, 24-Bit Address Mode ................245

14.3.4 Non-Multiplexed 16-Bit Data, N-Bit Address Mode ..............246

14.3.5 Page Mode Read Operation .....................247

14.3.6 Extended Addressing ........................250

14.3.7 Prefetch Unit and Write Buffer .....................251

14.3.8 Strobe Length ..........................252

14.3.9 Bus Turn-Around and Idle Cycles ....................253

14.3.10 Timing ............................254

14.3.11 Data Access Width ........................255

14.3.12 Bank Access ..........................256

14.3.13 WAIT/ARDY ..........................257

14.3.14 NAND Flash Support .......................258

14.3.15 Error Correction Code .......................264

14.3.16 TFT Direct Drive .........................267

14.3.17 Alpha Blending and Masking .....................271

14.3.18 Direct Drive Timing ........................274

14.3.19 Control Signal Polarity .......................276

14.3.20 Pin Configuration .........................276

14.3.21 Interrupts ...........................277

14.3.22 DMA Request ..........................277

14.4 Register Map.............................278

14.5 Register Description ..........................280

14.5.1 EBI_CTRL - Control Register .....................280

14.5.2 EBI_ADDRTIMING - Address Timing Register ...............283

14.5.3 EBI_RDTIMING - Read Timing Register .................284

14.5.4 EBI_WRTIMING - Write Timing Register .................285

14.5.5 EBI_POLARITY - Polarity Register ...................286

14.5.6 EBI_ROUTE - I/O Routing Register ...................288

14.5.7 EBI_ADDRTIMING1 - Address Timing Register 1 ..............290

14.5.8 EBI_RDTIMING1 - Read Timing Register 1 ................291

14.5.9 EBI_WRTIMING1 - Write Timing Register 1 ................292

14.5.10 EBI_POLARITY1 - Polarity Register 1 .................293

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14.5.11 EBI_ADDRTIMING2 - Address Timing Register 2 .............294

14.5.12 EBI_RDTIMING2 - Read Timing Register 2 ...............295

14.5.13 EBI_WRTIMING2 - Write Timing Register 2 ...............296

14.5.14 EBI_POLARITY2 - Polarity Register 2 .................297

14.5.15 EBI_ADDRTIMING3 - Address Timing Register 3 .............298

14.5.16 EBI_RDTIMING3 - Read Timing Register 3 ...............299

14.5.17 EBI_WRTIMING3 - Write Timing Register 3 ...............300

14.5.18 EBI_POLARITY3 - Polarity Register 3 .................301

14.5.19 EBI_PAGECTRL - Page Control Register ................303

14.5.20 EBI_NANDCTRL - NAND Control Register ................304

14.5.21 EBI_CMD - Command Register ...................305

14.5.22 EBI_STATUS - Status Register ....................306

14.5.23 EBI_ECCPARITY - ECC Parity register .................307

14.5.24 EBI_TFTCTRL - TFT Control Register .................308

14.5.25 EBI_TFTSTATUS - TFT Status Register ................310

14.5.26 EBI_TFTFRAMEBASE - TFT Frame Base Register .............310

14.5.27 EBI_TFTSTRIDE - TFT Stride Register .................311

14.5.28 EBI_TFTSIZE - TFT Size Register ..................311

14.5.29 EBI_TFTHPORCH - TFT Horizontal Porch Register .............312

14.5.30 EBI_TFTVPORCH - TFT Vertical Porch Register ..............313

14.5.31 EBI_TFTTIMING - TFT Timing Register .................314

14.5.32 EBI_TFTPOLARITY - TFT Polarity Register ...............315

14.5.33 EBI_TFTDD - TFT Direct Drive Data Register ...............316

14.5.34 EBI_TFTALPHA - TFT Alpha Blending Register ..............316

14.5.35 EBI_TFTPIXEL0 - TFT Pixel 0 Register .................317

14.5.36 EBI_TFTPIXEL1 - TFT Pixel 1 Register .................317

14.5.37 EBI_TFTPIXEL - TFT Alpha Blending Result Pixel Register ..........318

14.5.38 EBI_TFTMASK - TFT Masking Register .................318

14.5.39 EBI_IF - Interrupt Flag Register ...................319

14.5.40 EBI_IFS - Interrupt Flag Set Register ..................320

14.5.41 EBI_IFC - Interrupt Flag Clear Register .................321

14.5.42 EBI_IEN - Interrupt Enable Register ..................322

15. USB - Universal Serial Bus Controller.....................323

15.1 Introduction .............................323

15.2 Features ..............................324

15.3 USB System Description .........................325

15.3.1 USB Initialization .........................325

15.3.2 Configurations ..........................326

15.3.3 PHY..............................331

15.3.4 Voltage Regulator .........................331

15.3.5 Interrupts and PRS.........................331

15.3.6 USB in EM2 ...........................331

15.4 USB Core Description ..........................332

15.4.1 Overview: Programming the Core ....................332

15.4.2 Modes of Operation ........................336

15.4.3 Host Programming Model ......................340

15.4.4 Device Programming Model......................372

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15.4.5 OTG Revision 1.3 Programming Model ..................410

15.4.6 OTG Revision 2.0 Programming Model ..................413

15.4.7 FIFO RAM Allocation ........................420

15.4.8 Suspend/Resume and SRP ......................429

15.4.9 Register Usage ..........................438

15.5 Register Map.............................439

15.6 Register Description ..........................443

15.6.1 USB_CTRL - System Control Register ..................443

15.6.2 USB_STATUS - System Status Register .................444

15.6.3 USB_IF - Interrupt Flag Register ....................444

15.6.4 USB_IFS - Interrupt Flag Set Register ..................445

15.6.5 USB_IFC - Interrupt Flag Clear Register .................445

15.6.6 USB_IEN - Interrupt Enable Register ..................446

15.6.7 USB_ROUTE - I/O Routing Register ..................446

15.6.8 USB_GOTGCTL - OTG Control and Status Register .............447

15.6.9 USB_GOTGINT - OTG Interrupt Register .................449

15.6.10 USB_GAHBCFG - AHB Configuration Register ..............451

15.6.11 USB_GUSBCFG - USB Configuration Register ..............453

15.6.12 USB_GRSTCTL - Reset Register ...................455

15.6.13 USB_GINTSTS - Interrupt Register ..................457

15.6.14 USB_GINTMSK - Interrupt Mask Register ................461

15.6.15 USB_GRXSTSR - Receive Status Debug Read Register ...........463

15.6.16 USB_GRXSTSP - Receive Status Read and Pop Register ..........465

15.6.17 USB_GRXFSIZ - Receive FIFO Size Register ...............467

15.6.18 USB_GNPTXFSIZ - Non-periodic Transmit FIFO Size Register .........467

15.6.19 USB_GNPTXSTS - Non-periodic Transmit FIFO/Queue Status Register ......468

15.6.20 USB_GDFIFOCFG - Global DFIFO Configuration Register ..........469

15.6.21 USB_HPTXFSIZ - Host Periodic Transmit FIFO Size Register .........469

15.6.22 USB_DIEPTXF1 - Device IN Endpoint Transmit FIFO 1 Size Register ......470

15.6.23 USB_DIEPTXF2 - Device IN Endpoint Transmit FIFO 2 Size Register ......471

15.6.24 USB_DIEPTXF3 - Device IN Endpoint Transmit FIFO 3 Size Register ......472

15.6.25 USB_DIEPTXF4 - Device IN Endpoint Transmit FIFO 4 Size Register ......473

15.6.26 USB_DIEPTXF5 - Device IN Endpoint Transmit FIFO 5 Size Register ......474

15.6.27 USB_DIEPTXF6 - Device IN Endpoint Transmit FIFO 6 Size Register ......475

15.6.28 USB_HCFG - Host Configuration Register ................476

15.6.29 USB_HFIR - Host Frame Interval Register ................477

15.6.30 USB_HFNUM - Host Frame Number/Frame Time Remaining Register ......478

15.6.31 USB_HPTXSTS - Host Periodic Transmit FIFO/Queue Status Register ......479

15.6.32 USB_HAINT - Host All Channels Interrupt Register .............480

15.6.33 USB_HAINTMSK - Host All Channels Interrupt Mask Register .........480

15.6.34 USB_HPRT - Host Port Control and Status Register ............481

15.6.35 USB_HCx_CHAR - Host Channel x Characteristics Register ..........484

15.6.36 USB_HCx_INT - Host Channel x Interrupt Register .............486

15.6.37 USB_HCx_INTMSK - Host Channel x Interrupt Mask Register .........488

15.6.38 USB_HCx_TSIZ - Host Channel x Transfer Size Register ...........489

15.6.39 USB_HCx_DMAADDR - Host Channel x DMA Address Register ........490

15.6.40 USB_DCFG - Device Configuration Register ...............491

15.6.41 USB_DCTL - Device Control Register .................493

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15.6.42 USB_DSTS - Device Status Register ..................495

15.6.43 USB_DIEPMSK - Device IN Endpoint Common Interrupt Mask Register ......496

15.6.44 USB_DOEPMSK - Device OUT Endpoint Common Interrupt Mask Register ....497

15.6.45 USB_DAINT - Device All Endpoints Interrupt Register ............498

15.6.46 USB_DAINTMSK - Device All Endpoints Interrupt Mask Register ........500

15.6.47 USB_DVBUSDIS - Device VBUS Discharge Time Register ..........501

15.6.48 USB_DVBUSPULSE - Device VBUS Pulsing Time Register ..........502

15.6.49 USB_DIEPEMPMSK - Device IN Endpoint FIFO Empty Interrupt Mask Register ...502

15.6.50 USB_DIEP0CTL - Device IN Endpoint 0 Control Register ...........503

15.6.51 USB_DIEP0INT - Device IN Endpoint 0 Interrupt Register ...........505

15.6.52 USB_DIEP0TSIZ - Device IN Endpoint 0 Transfer Size Register ........507

15.6.53 USB_DIEP0DMAADDR - Device IN Endpoint 0 DMA Address Register ......508

15.6.54 USB_DIEP0TXFSTS - Device IN Endpoint 0 Transmit FIFO Status Register ....508

15.6.55 USB_DIEPx_CTL - Device IN Endpoint x+1 Control Register .........509

15.6.56 USB_DIEPx_INT - Device IN Endpoint x+1 Interrupt Register .........511

15.6.57 USB_DIEPx_TSIZ - Device IN Endpoint x+1 Transfer Size Register .......513

15.6.58 USB_DIEPx_DMAADDR - Device IN Endpoint x+1 DMA Address Register .....514

15.6.59 USB_DIEPx_TXFSTS - Device IN Endpoint x+1 Transmit FIFO Status Register ...514

15.6.60 USB_DOEP0CTL - Device OUT Endpoint 0 Control Register .........515

15.6.61 USB_DOEP0INT - Device OUT Endpoint 0 Interrupt Register .........517

15.6.62 USB_DOEP0TSIZ - Device OUT Endpoint 0 Transfer Size Register .......519

15.6.63 USB_DOEP0DMAADDR - Device OUT Endpoint 0 DMA Address Register .....520

15.6.64 USB_DOEPx_CTL - Device OUT Endpoint x+1 Control Register ........521

15.6.65 USB_DOEPx_INT - Device OUT Endpoint x+1 Interrupt Register ........523

15.6.66 USB_DOEPx_TSIZ - Device OUT Endpoint x+1 Transfer Size Register ......525

15.6.67 USB_DOEPx_DMAADDR - Device OUT Endpoint x+1 DMA Address Register ...526

15.6.68 USB_PCGCCTL - Power and Clock Gating Control Register ..........527

15.6.69 USB_FIFO0Dx - Device EP 0/Host Channel 0 FIFO .............528

15.6.70 USB_FIFO1Dx - Device EP 1/Host Channel 1 FIFO .............528

15.6.71 USB_FIFO2Dx - Device EP 2/Host Channel 2 FIFO .............529

15.6.72 USB_FIFO3Dx - Device EP 3/Host Channel 3 FIFO .............529

15.6.73 USB_FIFO4Dx - Device EP 4/Host Channel 4 FIFO .............530

15.6.74 USB_FIFO5Dx - Device EP 5/Host Channel 5 FIFO .............530

15.6.75 USB_FIFO6Dx - Device EP 6/Host Channel 6 FIFO .............531

15.6.76 USB_FIFO7Dx - Host Channel 7 FIFO .................531

15.6.77 USB_FIFO8Dx - Host Channel 8 FIFO .................532

15.6.78 USB_FIFO9Dx - Host Channel 9 FIFO .................532

15.6.79 USB_FIFO10Dx - Host Channel 10 FIFO ................533

15.6.80 USB_FIFO11Dx - Host Channel 11 FIFO ................533

15.6.81 USB_FIFO12Dx - Host Channel 12 FIFO ................534

15.6.82 USB_FIFO13Dx - Host Channel 13 FIFO ................534

15.6.83 USB_FIFORAMx - Direct Access to Data FIFO RAM for Debugging (2 KB) .....535

16. I

2

C - Inter-Integrated Circuit Interface .....................536

16.1 Introduction .............................536

16.2 Features ..............................536

16.3 Functional Description .........................537

16.3.1 I

2

C-Bus Overview .........................538

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16.3.2 Enable and Reset .........................542

16.3.3 Safely Disabling and Changing Slave Configuration..............542

16.3.4 Clock Generation .........................543

16.3.5 Arbitration ............................544

16.3.6 Buffers .............................545

16.3.7 Master Operation .........................545

16.3.8 Bus States ...........................553

16.3.9 Slave Operation ..........................553

16.3.10 Transfer Automation ........................557

16.3.11 Using 10-Bit Addresses .......................558

16.3.12 Error Handling ..........................558

16.3.13 DMA Support ..........................560

16.3.14 Interrupts ...........................560

16.3.15 Wake-Up ...........................560

16.4 Register Map.............................560

16.5 Register Description ..........................561

16.5.1 I2Cn_CTRL - Control Register ....................561

16.5.2 I2Cn_CMD - Command Register ...................564

16.5.3 I2Cn_STATE - State Register .....................565

16.5.4 I2Cn_STATUS - Status Register ....................566

16.5.5 I2Cn_CLKDIV - Clock Division Register .................567

16.5.6 I2Cn_SADDR - Slave Address Register .................567

16.5.7 I2Cn_SADDRMASK - Slave Address Mask Register .............568

16.5.8 I2Cn_RXDATA - Receive Buffer Data Register (Actionable Reads) ........568

16.5.9 I2Cn_RXDATAP - Receive Buffer Data Peek Register ............569

16.5.10 I2Cn_TXDATA - Transmit Buffer Data Register ..............569

16.5.11 I2Cn_IF - Interrupt Flag Register ...................570

16.5.12 I2Cn_IFS - Interrupt Flag Set Register .................572

16.5.13 I2Cn_IFC - Interrupt Flag Clear Register ................574

16.5.14 I2Cn_IEN - Interrupt Enable Register ..................576

16.5.15 I2Cn_ROUTE - I/O Routing Register ..................577

17. USART - Universal Synchronous Asynchronous Receiver/Transmitter ........578

17.1 Introduction .............................578

17.2 Features ..............................579

17.3 Functional Description .........................580

17.3.1 Modes of Operation ........................581

17.3.2 Asynchronous Operation .......................582

17.3.3 Synchronous Operation .......................597

17.3.4 PRS-Triggered Transmissions .....................603

17.3.5 PRS RX Input ..........................604

17.3.6 DMA Support ..........................604

17.3.7 Transmission Delay ........................604

17.3.8 Interrupts ............................605

17.3.9 IrDA Modulator/Demodulator .....................606

17.4 Register Map.............................607

17.5 Register Description ..........................608

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17.5.1 USARTn_CTRL - Control Register ...................608

17.5.2 USARTn_FRAME - USART Frame Format Register .............613

17.5.3 USARTn_TRIGCTRL - USART Trigger Control register ............615

17.5.4 USARTn_CMD - Command Register ..................616

17.5.5 USARTn_STATUS - USART Status Register ...............617

17.5.6 USARTn_CLKDIV - Clock Control Register ................618

17.5.7 USARTn_RXDATAX - RX Buffer Data Extended Register (Actionable Reads) ....619

17.5.8 USARTn_RXDATA - RX Buffer Data Register (Actionable Reads) ........619

17.5.9 USARTn_RXDOUBLEX - RX Buffer Double Data Extended Register (Actionable Reads) 620

17.5.10 USARTn_RXDOUBLE - RX FIFO Double Data Register (Actionable Reads) ....621

17.5.11 USARTn_RXDATAXP - RX Buffer Data Extended Peek Register ........621

17.5.12 USARTn_RXDOUBLEXP - RX Buffer Double Data Extended Peek Register ....622

17.5.13 USARTn_TXDATAX - TX Buffer Data Extended Register ...........623

17.5.14 USARTn_TXDATA - TX Buffer Data Register ...............624

17.5.15 USARTn_TXDOUBLEX - TX Buffer Double Data Extended Register .......625

17.5.16 USARTn_TXDOUBLE - TX Buffer Double Data Register ...........626

17.5.17 USARTn_IF - Interrupt Flag Register ..................627

17.5.18 USARTn_IFS - Interrupt Flag Set Register ................628

17.5.19 USARTn_IFC - Interrupt Flag Clear Register ...............629

17.5.20 USARTn_IEN - Interrupt Enable Register ................630

17.5.21 USARTn_IRCTRL - IrDA Control Register ................631

17.5.22 USARTn_ROUTE - I/O Routing Register ................633

17.5.23 USARTn_INPUT - USART Input Register ................634

17.5.24 USARTn_I2SCTRL - I2S Control Register ................635

18. UART - Universal Asynchronous Receiver/ Transmitter ..............637

18.1 Introduction .............................637

18.2 Features ..............................638

18.3 Functional Description .........................638

18.4 Register Description ..........................638

18.5 Register Map.............................638

19. LEUART - Low Energy Universal Asynchronous Receiver/Transmitter ........639

19.1 Introduction .............................639

19.2 Features ..............................640

19.3 Functional Description .........................641

19.3.1 Frame Format ..........................642

19.3.2 Clock Source ..........................642

19.3.3 Clock Generation .........................643

19.3.4 Data Transmission .........................643

19.3.5 Data Reception ..........................645

19.3.6 Loopback ............................648

19.3.7 Half Duplex Communication .....................648

19.3.8 Transmission Delay ........................649

19.3.9 PRS RX Input ..........................649

19.3.10 DMA Support ..........................649

19.3.11 Pulse Generator / Pulse Extender ...................650

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19.3.12 Register Access .........................650

19.4 Register Map.............................651

19.5 Register Description ..........................652

19.5.1 LEUARTn_CTRL - Control Register (Async Reg) ..............652

19.5.2 LEUARTn_CMD - Command Register (Async Reg) .............655

19.5.3 LEUARTn_STATUS - Status Register ..................656

19.5.4 LEUARTn_CLKDIV - Clock Control Register (Async Reg) ...........657

19.5.5 LEUARTn_STARTFRAME - Start Frame Register (Async Reg) .........657

19.5.6 LEUARTn_SIGFRAME - Signal Frame Register (Async Reg) ..........658

19.5.7 LEUARTn_RXDATAX - Receive Buffer Data Extended Register (Actionable Reads) ..658

19.5.8 LEUARTn_RXDATA - Receive Buffer Data Register (Actionable Reads) ......659

19.5.9 LEUARTn_RXDATAXP - Receive Buffer Data Extended Peek Register ......659

19.5.10 LEUARTn_TXDATAX - Transmit Buffer Data Extended Register (Async Reg) ....660

19.5.11 LEUARTn_TXDATA - Transmit Buffer Data Register (Async Reg) ........661

19.5.12 LEUARTn_IF - Interrupt Flag Register .................662

19.5.13 LEUARTn_IFS - Interrupt Flag Set Register ...............663

19.5.14 LEUARTn_IFC - Interrupt Flag Clear Register ...............664

19.5.15 LEUARTn_IEN - Interrupt Enable Register ................665

19.5.16 LEUARTn_PULSECTRL - Pulse Control Register (Async Reg) .........666

19.5.17 LEUARTn_FREEZE - Freeze Register .................667

19.5.18 LEUARTn_SYNCBUSY - Synchronization Busy Register ...........668

19.5.19 LEUARTn_ROUTE - I/O Routing Register ................669

19.5.20 LEUARTn_INPUT - LEUART Input Register ...............670

20. TIMER - Timer/Counter ..........................671

20.1 Introduction .............................671

20.2 Features ..............................672

20.3 Functional Description .........................673

20.3.1 Counter Modes ..........................673

20.3.2 Compare/Capture Channels .....................679

20.3.3 Dead-Time Insertion Unit (TIMER0 only) .................687

20.3.4 Debug Mode ...........................690

20.3.5 Interrupts, DMA and PRS Output ....................691

20.3.6 GPIO Input/Output .........................691

20.4 Register Map.............................692

20.5 Register Description ..........................693

20.5.1 TIMERn_CTRL - Control Register ...................693

20.5.2 TIMERn_CMD - Command Register ..................695

20.5.3 TIMERn_STATUS - Status Register ..................696

20.5.4 TIMERn_IEN - Interrupt Enable Register .................699

20.5.5 TIMERn_IF - Interrupt Flag Register ..................700

20.5.6 TIMERn_IFS - Interrupt Flag Set Register ................701

20.5.7 TIMERn_IFC - Interrupt Flag Clear Register ................702

20.5.8 TIMERn_TOP - Counter Top Value Register ...............703

20.5.9 TIMERn_TOPB - Counter Top Value Buffer Register .............703

20.5.10 TIMERn_CNT - Counter Value Register .................704

20.5.11 TIMERn_ROUTE - I/O Routing Register .................705

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20.5.12 TIMERn_CCx_CTRL - CC Channel Control Register ............706

20.5.13 TIMERn_CCx_CCV - CC Channel Value Register .............709

20.5.14 TIMERn_CCx_CCVP - CC Channel Value Peek Register ...........709

20.5.15 TIMERn_CCx_CCVB - CC Channel Buffer Register .............710

20.5.16 TIMERn_DTCTRL - DTI Control Register ................711

20.5.17 TIMERn_DTTIME - DTI Time Control Register ..............713

20.5.18 TIMERn_DTFC - DTI Fault Configuration Register .............715

20.5.19 TIMERn_DTOGEN - DTI Output Generation Enable Register .........717

20.5.20 TIMERn_DTFAULT - DTI Fault Register ................718

20.5.21 TIMERn_DTFAULTC - DTI Fault Clear Register ..............719

20.5.22 TIMERn_DTLOCK - DTI Configuration Lock Register ............720

21. RTC - Real Time Counter .........................721

21.1 Introduction .............................721

21.2 Features ..............................721

21.3 Functional Description .........................722

21.3.1 Counter ............................722

21.3.2 Compare Channels ........................723

21.3.3 Interrupts ............................724

21.3.4 DEBUGRUN ...........................724

21.3.5 Using the RTC in EM3 .......................724

21.3.6 Register Access..........................724

21.4 Register Map.............................724

21.5 Register Description ..........................725

21.5.1 RTC_CTRL - Control Register (Async Reg) ................725

21.5.2 RTC_CNT - Counter Value Register ..................726

21.5.3 RTC_COMP0 - Compare Value Register 0 (Async Reg) ............726

21.5.4 RTC_COMP1 - Compare Value Register 1 (Async Reg) ............727

21.5.5 RTC_IF - Interrupt Flag Register ....................727

21.5.6 RTC_IFS - Interrupt Flag Set Register ..................728

21.5.7 RTC_IFC - Interrupt Flag Clear Register .................728

21.5.8 RTC_IEN - Interrupt Enable Register ..................729

21.5.9 RTC_FREEZE - Freeze Register ...................729

21.5.10 RTC_SYNCBUSY - Synchronization Busy Register .............730

22. BURTC - Backup Real Time Counter .....................731

22.1 Introduction .............................731

22.2 Features ..............................731

22.3 Functional Description .........................732

22.3.1 Counter ............................732

22.3.2 Clock Source ..........................732

22.3.3 Compare Channel .........................732

22.3.4 PRS Sources ..........................732

22.3.5 Debug Run ...........................733

22.3.6 Low Power Mode .........................733

22.3.7 Retention Registers ........................733

22.3.8 Backup Operation .........................733

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22.3.9 Backup Mode Timestamp ......................734

22.3.10 LFXO Failure Detection .......................734

22.3.11 Register Access .........................734

22.4 Register Map.............................735

22.5 Register Description ..........................736

22.5.1 BURTC_CTRL - Control Register ...................736

22.5.2 BURTC_LPMODE - Low power mode configuration (Async Reg) .........738

22.5.3 BURTC_CNT - Counter Value Register .................738

22.5.4 BURTC_COMP0 - Counter Compare Value (Async Reg) ...........739

22.5.5 BURTC_TIMESTAMP - Backup mode timestamp ..............739

22.5.6 BURTC_LFXOFDET - LFXO .....................740

22.5.7 BURTC_STATUS - Status Register ...................741

22.5.8 BURTC_CMD - Command Register ..................741

22.5.9 BURTC_POWERDOWN - Retention RAM power-down Register .........742

22.5.10 BURTC_LOCK - Configuration Lock Register ...............742

22.5.11 BURTC_IF - Interrupt Flag Register ..................743

22.5.12 BURTC_IFS - Interrupt Flag Set Register ................743

22.5.13 BURTC_IFC - Interrupt Flag Clear Register ...............744

22.5.14 BURTC_IEN - Interrupt Enable Register .................744

22.5.15 BURTC_FREEZE - Freeze Register ..................745

22.5.16 BURTC_SYNCBUSY - Synchronization Busy Register ............745

22.5.17 RETx_REG - Retention Register ...................746

23. LETIMER - Low Energy Timer ........................747

23.1 Introduction .............................747

23.2 Features ..............................747

23.3 Functional Description .........................748

23.3.1 Timer .............................748

23.3.2 Compare Registers ........................748

23.3.3 Top Value ............................748

23.3.4 Underflow Output Action .......................754

23.3.5 PRS Output ...........................756

23.3.6 Examples ............................756

23.3.7 Using the LETIMER in EM3 ......................758

23.3.8 Register Access..........................758

23.4 Register Map.............................759

23.5 Register Description ..........................760

23.5.1 LETIMERn_CTRL - Control Register (Async Reg) ..............760

23.5.2 LETIMERn_CMD - Command Register .................762

23.5.3 LETIMERn_STATUS - Status Register .................762

23.5.4 LETIMERn_CNT - Counter Value Register ................763

23.5.5 LETIMERn_COMP0 - Compare Value Register 0 (Async Reg) .........763

23.5.6 LETIMERn_COMP1 - Compare Value Register 1 (Async Reg) .........764

23.5.7 LETIMERn_REP0 - Repeat Counter Register 0 (Async Reg) ..........764

23.5.8 LETIMERn_REP1 - Repeat Counter Register 1 (Async Reg) ..........765

23.5.9 LETIMERn_IF - Interrupt Flag Register .................765

23.5.10 LETIMERn_IFS - Interrupt Flag Set Register ...............766

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23.5.11 LETIMERn_IFC - Interrupt Flag Clear Register ..............767

23.5.12 LETIMERn_IEN - Interrupt Enable Register ...............768

23.5.13 LETIMERn_FREEZE - Freeze Register .................769

23.5.14 LETIMERn_SYNCBUSY - Synchronization Busy Register ..........770

23.5.15 LETIMERn_ROUTE - I/O Routing Register ................771

24. PCNT - Pulse Counter ..........................772

24.1 Introduction .............................772

24.2 Features ..............................772

24.3 Functional Description .........................773

24.3.1 Pulse Counter Modes ........................773

24.3.2 Hysteresis ...........................775

24.3.3 Auxiliary Counter .........................775

24.3.4 Register Access..........................776

24.3.5 Clock Sources ..........................776

24.3.6 Input Filter ...........................776

24.3.7 Edge Polarity ..........................776

24.3.8 PRS S0IN and S1IN Input ......................776

24.3.9 Interrupts ............................776

24.4 Register Map.............................778

24.5 Register Description ..........................779

24.5.1 PCNTn_CTRL - Control Register (Async Reg) ...............779

24.5.2 PCNTn_CMD - Command Register (Async Reg) ..............781

24.5.3 PCNTn_STATUS - Status Register ...................781

24.5.4 PCNTn_CNT - Counter Value Register .................782

24.5.5 PCNTn_TOP - Top Value Register ...................782

24.5.6 PCNTn_TOPB - Top Value Buffer Register (Async Reg) ...........783

24.5.7 PCNTn_IF - Interrupt Flag Register ...................783

24.5.8 PCNTn_IFS - Interrupt Flag Set Register .................784

24.5.9 PCNTn_IFC - Interrupt Flag Clear Register ................785

24.5.10 PCNTn_IEN - Interrupt Enable Register .................786

24.5.11 PCNTn_ROUTE - I/O Routing Register .................787

24.5.12 PCNTn_FREEZE - Freeze Register ..................788

24.5.13 PCNTn_SYNCBUSY - Synchronization Busy Register ............788

24.5.14 PCNTn_AUXCNT - Auxiliary Counter Value Register ............789

24.5.15 PCNTn_INPUT - PCNT Input Register .................790

25. LESENSE - Low Energy Sensor Interface ...................792

25.1 Introduction .............................792

25.2 Features ..............................792

25.3 Functional Description .........................793

25.3.1 Channel Configuration .......................794

25.3.2 Scan Sequence ..........................795

25.3.3 Sensor Timing ..........................796

25.3.4 Sensor Interaction .........................797

25.3.5 Sensor Evaluation .........................799

25.3.6 Decoder ............................800

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25.3.7 Measurement Results ........................803

25.3.8 DAC Interface ..........................804

25.3.9 ACMP Interface ..........................804

25.3.10 ACMP and DAC Duty Cycling.....................804

25.3.11 DMA Requests .........................804

25.3.12 PRS Output...........................804

25.3.13 RAM .............................805

25.3.14 Application Examples .......................805

25.4 Register Map.............................810

25.5 Register Description ..........................812

25.5.1 LESENSE_CTRL - Control Register (Async Reg) ..............812

25.5.2 LESENSE_TIMCTRL - Timing Control Register (Async Reg) ..........815

25.5.3 LESENSE_PERCTRL - Peripheral Control Register (Async Reg) .........817

25.5.4 LESENSE_DECCTRL - Decoder control Register (Async Reg) .........820

25.5.5 LESENSE_BIASCTRL - Bias Control Register (Async Reg) ..........823

25.5.6 LESENSE_CMD - Command Register ..................824

25.5.7 LESENSE_CHEN - Channel enable Register (Async Reg) ...........824

25.5.8 LESENSE_SCANRES - Scan result register (Async Reg) ...........825

25.5.9 LESENSE_STATUS - Status Register (Async Reg) .............826

25.5.10 LESENSE_PTR - Result buffer pointers (Async Reg) ............827

25.5.11 LESENSE_BUFDATA - Result buffer data register (Async Reg) (Actionable Reads) ..827

25.5.12 LESENSE_CURCH - Current channel index (Async Reg) ...........828

25.5.13 LESENSE_DECSTATE - Current decoder state (Async Reg) .........828

25.5.14 LESENSE_SENSORSTATE - Decoder input register (Async Reg) ........829

25.5.15 LESENSE_IDLECONF - GPIO Idle phase configuration (Async Reg) .......830

25.5.16 LESENSE_ALTEXCONF - Alternative excite pin configuration (Async Reg) .....834

25.5.17 LESENSE_IF - Interrupt Flag Register .................837

25.5.18 LESENSE_IFC - Interrupt Flag Clear Register ...............839

25.5.19 LESENSE_IFS - Interrupt Flag Set Register ...............841

25.5.20 LESENSE_IEN - Interrupt Enable Register ................843

25.5.21 LESENSE_SYNCBUSY - Synchronization Busy Register ...........845

25.5.22 LESENSE_ROUTE - I/O Routing Register (Async Reg) ...........847

25.5.23 LESENSE_POWERDOWN - LESENSE RAM power-down register (Async Reg) ...848

25.5.24 LESENSE_STx_TCONFA - State transition configuration A (Async Reg) .....849

25.5.25 LESENSE_STx_TCONFB - State transition configuration B (Async Reg) .....851

25.5.26 LESENSE_BUFx_DATA - Scan results (Async Reg) ............852

25.5.27 LESENSE_CHx_TIMING - Scan configuration (Async Reg) ..........853

25.5.28 LESENSE_CHx_INTERACT - Scan configuration (Async Reg) .........854

25.5.29 LESENSE_CHx_EVAL - Scan configuration (Async Reg) ...........856

26. ACMP - Analog Comparator ........................857

26.1 Introduction .............................857

26.2 Features ..............................857

26.3 Functional Description .........................858

26.3.1 Warm-up Time ..........................858

26.3.2 Response Time ..........................859

26.3.3 Hysteresis ...........................860

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26.3.4 Input Selection ..........................860

26.3.5 Capacitive Sense Mode .......................861

26.3.6 Interrupts and PRS Output ......................861

26.3.7 Output to GPIO ..........................861

26.4 Register Map.............................862

26.5 Register Description ..........................863

26.5.1 ACMPn_CTRL - Control Register ...................863

26.5.2 ACMPn_INPUTSEL - Input Selection Register ...............865

26.5.3 ACMPn_STATUS - Status Register ...................867

26.5.4 ACMPn_IEN - Interrupt Enable Register .................867

26.5.5 ACMPn_IF - Interrupt Flag Register ..................868

26.5.6 ACMPn_IFS - Interrupt Flag Set Register .................868

26.5.7 ACMPn_IFC - Interrupt Flag Clear Register ................869

26.5.8 ACMPn_ROUTE - I/O Routing Register .................869

27. VCMP - Voltage Comparator ........................870

27.1 Introduction .............................870

27.2 Features ..............................870

27.3 Functional Description .........................871

27.3.1 Warm-Up Time ..........................871

27.3.2 Response Time ..........................872

27.3.3 Hysteresis ...........................873

27.3.4 Input Selection ..........................873

27.3.5 Interrupts and PRS Output ......................873

27.4 Register Map.............................874

27.5 Register Description ..........................875

27.5.1 VCMP_CTRL - Control Register ....................875

27.5.2 VCMP_INPUTSEL - Input Selection Register ...............876

27.5.3 VCMP_STATUS - Status Register ...................877

27.5.4 VCMP_IEN - Interrupt Enable Register .................877

27.5.5 VCMP_IF - Interrupt Flag Register ...................878

27.5.6 VCMP_IFS - Interrupt Flag Set Register .................878

27.5.7 VCMP_IFC - Interrupt Flag Clear Register ................879

28. ADC - Analog to Digital Converter ......................880

28.1 Introduction .............................880

28.2 Features ..............................881

28.3 Functional Description .........................882

28.3.1 Clock Selection ..........................882

28.3.2 Conversions ...........................883

28.3.3 Warm-Up Time ..........................884

28.3.4 Input Selection ..........................885

28.3.5 Reference Selection ........................886

28.3.6 Programming of Bias Current .....................886

28.3.7 ADC Modes ...........................886

28.3.8 Interrupts, PRS Output .......................890

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28.3.9 DMA Request ..........................890

28.3.10 Calibration ...........................891

28.4 Register Map.............................892

28.5 Register Description ..........................893

28.5.1 ADCn_CTRL - Control Register ....................893

28.5.2 ADCn_CMD - Command Register ...................895

28.5.3 ADCn_STATUS - Status Register ...................896

28.5.4 ADCn_SINGLECTRL - Single Sample Control Register ............898

28.5.5 ADCn_SCANCTRL - Scan Control Register ................902

28.5.6 ADCn_IEN - Interrupt Enable Register ..................905

28.5.7 ADCn_IF - Interrupt Flag Register ...................906

28.5.8 ADCn_IFS - Interrupt Flag Set Register .................907

28.5.9 ADCn_IFC - Interrupt Flag Clear Register ................908

28.5.10 ADCn_SINGLEDATA - Single Conversion Result Data (Actionable Reads) .....908

28.5.11 ADCn_SCANDATA - Scan Conversion Result Data (Actionable Reads) ......909

28.5.12 ADCn_SINGLEDATAP - Single Conversion Result Data Peek Register ......909

28.5.13 ADCn_SCANDATAP - Scan Sequence Result Data Peek Register .......910

28.5.14 ADCn_CAL - Calibration Register ...................911

28.5.15 ADCn_BIASPROG - Bias Programming Register ..............912

29. DAC - Digital to Analog Converter ......................913

29.1 Introduction .............................913

29.2 Features ..............................913

29.3 Functional Description .........................914

29.3.1 Conversions ...........................914

29.3.2 Reference Selection ........................915

29.3.3 Programming of Bias Current .....................915

29.3.4 Mode .............................916

29.3.5 Sine Generation Mode .......................916

29.3.6 Interrupts and PRS Output ......................917

29.3.7 DMA Request ..........................917

29.3.8 Analog Output ..........................917

29.3.9 Calibration ...........................917

29.3.10 Opamps ............................917

29.4 Register Map.............................918

29.5 Register Description ..........................919

29.5.1 DACn_CTRL - Control Register ....................919

29.5.2 DACn_STATUS - Status Register ...................921

29.5.3 DACn_CH0CTRL - Channel 0 Control Register ...............922

29.5.4 DACn_CH1CTRL - Channel 1 Control Register ...............924

29.5.5 DACn_IEN - Interrupt Enable Register ..................925

29.5.6 DACn_IF - Interrupt Flag Register ...................926

29.5.7 DACn_IFS - Interrupt Flag Set Register .................927

29.5.8 DACn_IFC - Interrupt Flag Clear Register ................928

29.5.9 DACn_CH0DATA - Channel 0 Data Register ...............928

29.5.10 DACn_CH1DATA - Channel 1 Data Register ...............929

29.5.11 DACn_COMBDATA - Combined Data Register ..............929

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29.5.12 DACn_CAL - Calibration Register ...................930

29.5.13 DACn_BIASPROG - Bias Programming Register ..............931

29.5.14 DACn_OPACTRL - Operational Amplifier Control Register ..........932

29.5.15 DACn_OPAOFFSET - Operational Amplifier Offset Register ..........933

29.5.16 DACn_OPA0MUX - Operational Amplifier Mux Configuration Register ......934

29.5.17 DACn_OPA1MUX - Operational Amplifier Mux Configuration Register ......937

29.5.18 DACn_OPA2MUX - Operational Amplifier Mux Configuration Register ......940

30. OPAMP - Operational Amplifier .......................942

30.1 Introduction .............................942

30.2 Features ..............................942

30.3 Functional Description .........................943

30.3.1 Opamp Configuration ........................944

30.3.2 Opamp Modes ..........................946

30.3.3 Opamp DAC Combination ......................954

30.4 Register Description ..........................954

30.5 Register Map.............................954

31. AES - Advanced Encryption Standard Accelerator ................955

31.1 Introduction .............................955

31.2 Features ..............................955

31.3 Functional Description .........................956

31.3.1 Encryption/Decryption........................956

31.3.2 Data and Key Access ........................957

31.3.3 Interrupt Request .........................958

31.3.4 DMA Request ..........................958

31.3.5 Block Chaining Example .......................959

31.4 Register Map.............................959

31.5 Register Description ..........................960

31.5.1 AES_CTRL - Control Register ....................960

31.5.2 AES_CMD - Command Register ....................961

31.5.3 AES_STATUS - Status Register ....................961

31.5.4 AES_IEN - Interrupt Enable Register ..................962

31.5.5 AES_IF - Interrupt Flag Register ....................962

31.5.6 AES_IFS - Interrupt Flag Set Register ..................962

31.5.7 AES_IFC - Interrupt Flag Clear Register .................963

31.5.8 AES_DATA - DATA Register (Actionable Reads) ..............963

31.5.9 AES_XORDATA - XORDATA Register (Actionable Reads) ...........964

31.5.10 AES_KEYLA - KEY Low Register (Actionable Reads) ............964

31.5.11 AES_KEYLB - KEY Low Register (Actionable Reads) ............965

31.5.12 AES_KEYLC - KEY Low Register (Actionable Reads) ............965

31.5.13 AES_KEYLD - KEY Low Register (Actionable Reads) ............966

31.5.14 AES_KEYHA - KEY High Register (Actionable Reads) ............966

31.5.15 AES_KEYHB - KEY High Register (Actionable Reads) ............967

31.5.16 AES_KEYHC - KEY High Register (Actionable Reads) ............967

31.5.17 AES_KEYHD - KEY High Register (Actionable Reads) ............968

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