Steren 14017 Owner's manual

 Semiconductor Components Industries, LLC, 2000

March, 2000 – Rev. 3

1 Publication Order Number:

MC14017B/D

The MC14017B is a five–stage Johnson decade counter with

built–in code converter. High speed operation and spike–free outputs

are obtained by use of a Johnson decade counter design. The ten

decoded outputs are normally low, and go high only at their

appropriate decimal time period. The output changes occur on the

positive–going edge of the clock pulse. This part can be used in

frequency division applications as well as decade counter or decimal

decode display applications.

• Fully Static Operation

• DC Clock Input Circuit Allows Slow Rise Times

• Carry Out Output for Cascading

• Divide–by–N Counting

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• Capable of Driving Two Low–power TTL Loads or One Low–power

Schottky TTL Load Over the Rated Temperature Range

• Pin–for–Pin Replacement for CD4017B

• Triple Diode Protection on All Inputs

MAXIMUM RATINGS (Voltages Referenced to V

SS

) (Note 2.)

Symbol

Parameter Value Unit

V

DD

DC Supply Voltage Range –0.5 to +18.0 V

V

in

, V

out

Input or Output Voltage Range

(DC or Transient)

–0.5 to V

DD

+ 0.5 V

I

in

, I

out

Input or Output Current

(DC or Transient) per Pin

±10 mA

P

D

Power Dissipation,

per Package (Note 3.)

500 mW

T

A

Ambient Temperature Range –55 to +125 °C

T

stg

Storage Temperature Range –65 to +150 °C

T

L

Lead Temperature

(8–Second Soldering)

260 °C

2. Maximum Ratings are those values beyond which damage to the device

may occur.

3. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C

This device contains protection circuitry to guard against damage due to high

static voltages or electric fields. However, precautions must be taken to avoid

applications of any voltage higher than maximum rated voltages to this

high–impedance circuit. For proper operation, V

in

and V

out

should be constrained

to the range V

SS

(V

in

or V

out

) V

DD

.

Unused inputs must always be tied to an appropriate logic voltage level (e.g.,

either V

SS

or V

DD

). Unused outputs must be left open.

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A = Assembly Location

WL or L = Wafer Lot

YY or Y = Year

WW or W = Work Week

Device Package Shipping

ORDERING INFORMATION

MC14017BCP PDIP–16 2000/Box

MC14017BD SOIC–16 48/Rail

MC14017BDR2 SOIC–16 2500/Tape & Reel

1. For ordering information on the EIAJ version of the

SOIC packages, please contact your local ON

Semiconductor representative.

MARKING

DIAGRAMS

1

16

PDIP–16

P SUFFIX

CASE 648

MC14017BCP

AWLYYWW

SOIC–16

D SUFFIX

CASE 751B

1

16

14017B

AWLYWW

SOEIAJ–16

F SUFFIX

CASE 966

1

16

MC14017B

AWLYWW

MC14017BF SOEIAJ–16 See Note 1.

MC14017BFEL SOEIAJ–16 See Note 1.

MC14017B

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2

BLOCK DIAGRAMFUNCTIONAL TRUTH TABLE

(Positive Logic)

Clock Decode

Clock Enable

Reset Output=n

0X0 n

X10 n

XX1Q0

0 0 n+1

X0 n

X0n

1 0 n+1

X = Don’t Care. If n < 5 Carry = “1”,

Otherwise = “0”.

CLOCK

ENABLE

RESET

14

13

15 C

out

Q9

Q8

Q7

Q6

Q5

Q4

Q3

Q2

Q1

Q0 3

2

4

7

10

1

5

6

9

11

12

V

DD

= PIN 16

V

SS

= PIN 8

LOGIC DIAGRAM

CLOCK

ENABLE

CARRY

RESET

Q5 Q1 Q7 Q3 Q9

117621

12

Q0 Q6 Q2 Q3 Q4

354910

14

13

15

C

D

RR

Q

PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

C

out

CE

CLOCK

RESET

V

DD

Q8

Q4

Q9

Q2

Q0

Q1

Q5

V

SS

Q3

Q7

Q6

C

D

RR

Q

C

D

RR

Q

C

D

RR

Q

C

D

RR

Q

MC14017B

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3

ELECTRICAL CHARACTERISTICS (Voltages Referenced to V

SS

)

V

DD

– 55 C 25 C 125 C

Characteristic Symbol

V

DD

Vdc

Min Max Min Typ

(4.)

Max Min Max

Unit

Output Voltage “0” Level

V

in

= V

DD

or 0

V

OL

5.0

10

15

—

0.05

—

0

0.05

—

0.05

Vdc

“1” Level

V

in

= 0 or V

DD

V

OH

5.0

10

15

4.95

9.95

14.95

—

4.95

9.95

14.95

5.0

10

15

—

4.95

9.95

14.95

—

Vdc

Input Voltage “0” Level

(V

O

= 4.5 or 0.5 Vdc)

(V

O

= 9.0 or 1.0 Vdc)

(V

O

= 13.5 or 1.5 Vdc)

V

IL

5.0

10

15

—

1.5

3.0

4.0

—

2.25

4.50

6.75

1.5

3.0

4.0

—

1.5

3.0

4.0

Vdc

“1” Level

(V

O

= 0.5 or 4.5 Vdc)

(V

O

= 1.0 or 9.0 Vdc)

(V

O

= 1.5 or 13.5 Vdc)

V

IH

5.0

10

15

3.5

7.0

11

—

3.5

7.0

11

2.75

5.50

8.25

—

3.5

7.0

11

—

Vdc

Output Drive Current

(V

OH

= 2.5 Vdc) Source

(V

OH

= 4.6 Vdc)

(V

OH

= 9.5 Vdc)

(V

OH

= 13.5 Vdc)

I

OH

5.0

10

15

– 3.0

– 0.64

– 1.6

– 4.2

—

– 2.4

– 0.51

– 1.3

– 3.4

– 4.2

– 0.88

– 2.25

– 8.8

—

– 1.7

– 0.36

– 0.9

– 2.4

—

mAdc

(V

OL

= 0.4 Vdc) Sink

(V

OL

= 0.5 Vdc)

(V

OL

= 1.5 Vdc)

I

OL

5.0

10

15

0.64

1.6

4.2

—

0.51

1.3

3.4

0.88

2.25

8.8

—

0.36

0.9

2.4

—

mAdc

Input Current I

in

15 — ± 0.1 — ±0.00001 ± 0.1 — ± 1.0 µAdc

Input Capacitance

(V

in

= 0)

C

in

— — — — 5.0 7.5 — — pF

Quiescent Current

(Per Package)

I

DD

5.0

10

15

—

5.0

10

20

—

0.005

0.010

0.015

5.0

10

20

—

150

300

600

µAdc

Total Supply Current

(5.)

(6.)

(Dynamic plus Quiescent,

Per Package)

(C

L

= 50 pF on all outputs, all

buffers switching)

I

T

5.0

10

15

I

T

= (0.27 µA/kHz) f + I

DD

I

T

= (0.55 µA/kHz) f + I

DD

I

T

= (0.83 µA/kHz) f + I

DD

µAdc

4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

5. The formulas given are for the typical characteristics only at 25 C.

6. To calculate total supply current at loads other than 50 pF:

I

T

(C

L

) = I

T

(50 pF) + (C

L

– 50) Vfk

where: I

T

is in µA (per package), C

L

in pF, V = (V

DD

– V

SS

) in volts, f in kHz is input frequency, and k = 0.0011.

MC14017B

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4

SWITCHING CHARACTERISTICS

(7.)

(C

L

= 50 pF, T

A

= 25 C)

Characteristic Symbol

V

DD

Vdc

Min Typ

(8.)

Max Unit

Output Rise and Fall Time

t

TLH

, t

THL

= (1.5 ns/pF) C

L

+ 25 ns

t

TLH

, t

THL

= (0.75 ns/pF) C

L

+ 12.5 ns

t

TLH

, t

THL

= (0.55 ns/pF) C

L

+ 9.5 ns

t

TLH

,

t

THL

5.0

10

15

—

100

50

40

200

100

80

ns

Propagation Delay Time

Reset to Decode Output

t

PLH

, t

PHL

= (1.7 ns/pF) C

L

+ 415 ns

t

PLH

, t

PHL

= (0.66 ns/PF) C

L

+ 197 ns

t

PLH

, t

PHL

= (0.5 ns/pF) C

L

+ 150 ns

t

PLH

,

t

PHL

5.0

10

15

—

500

230

175

1000

460

350

ns

Propagation Delay Time

Clock to C

out

t

PLH

, t

PHL

= (1.7 ns/pF) C

L

+ 315 ns

t

PLH

, t

PHL

= (0.66 ns/pF) C

L

+ 142 ns

t

PLH

, t

PHL

= (0.5 ns/pF) C

L

+ 100 ns

t

PLH

,

t

PHL

5.0

10

15

—

400

175

125

800

350

250

ns

Propagation Delay Time

Clock to Decode Output

t

PLH

, t

PHL

= (1.7 ns/pF) C

L

+ 415 ns

t

PLH

, t

PHL

= (0.66 ns/pF) C

L

+ 197 ns

t

PLH

, t

PHL

= (0.5 ns/pF) C

L

+ 150 ns

t

PLH

,

t

PHL

5.0

10

15

—

500

230

175

1000

460

350

ns

Turn–Off Delay Time

Reset to C

out

t

PLH

= (1.7 ns/pF) C

L

+ 315 ns

t

PLH

= (0.66 ns/pF) C

L

+ 142 ns

t

PLH

= (0.5 ns/pF) C

L

+ 100 ns

t

PLH

5.0

10

15

—

400

175

125

800

350

250

ns

Clock Pulse Width t

w(H)

5.0

10

15

250

100

75

125

50

35

—

ns

Clock Frequency f

cl

5.0

10

15

—

5.0

12

16

2.0

5.0

6.7

MHz

Reset Pulse Width t

w(H)

5.0

10

15

500

250

190

250

125

95

—

ns

Reset Removal Time t

rem

5.0

10

15

750

275

210

375

135

105

—

ns

Clock Input Rise and Fall Time t

TLH

,

t

THL

5.0

10

15

No Limit

—

Clock Enable Setup Time t

su

5.0

10

15

350

150

115

175

75

52

—

ns

Clock Enable Removal Time t

rem

5.0

10

15

420

200

140

260

100

70

—

ns

7. The formulas given are for the typical characteristics only at 25 C.

8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

MC14017B

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5

Figure 1. Typical Output Source and Output Sink Characteristics Test Circuit

V

DD

V

out

V

SS

V

DD

V

SS

S1

A

B

V

SS

I

D

EXTERNAL

POWER

SUPPLY

CLOCK

ENABLE

RESET

CLOCK

C

out

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

Q8

Q9

Output

Sink Drive

Output

Source Drive

Decode

Outputs

Clock to

desired

outputs

(S1 to B)

(S1 to A)

Carry

Clock to 5

thru 9

(S1 to B)

S1 to A

V

GS

=– V

DD

V

DD

V

DS

=V

out

– V

DD

V

out

Figure 2. Typical Power Dissipation Test Circuit

V

DD

V

SS

I

D

CLOCK

ENABLE

RESET

CLOCK

C

out

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

Q8

Q9

500 µF

0.01 µF

CERAMIC

PULSE

GENERATOR

f

c

C

L

C

L

C

L

C

L

C

L

C

L

C

L

C

L

C

L

C

L

C

L

MC14017B

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6

APPLICATIONS INFORMATION

Figure 3 shows a technique for extending the number of decoded output states for the MC14017B. Decoded outputs are

sequential within each stage and from stage to stage, with no dead time (except propagation delay).

Figure 3. Counter Expansion

RESET

CLOCK

CE

MC14017B

Q0 Q1 Q8 Q9

•••

9 DECODED

OUTPUTS

CLOCK

FIRST STAGE INTERMEDIATE STAGES LAST STAGE

RESET

CLOCK

CE

MC14017B

Q0Q1 Q8 Q9

•••

RESET

CLOCK

CE

MC14017B

Q1 Q8 Q9

•••

8 DECODED

OUTPUTS

8 DECODED

OUTPUTS

Figure 4. AC Measurement Definition and Functional Waveforms

Pcp

Ncp

CLOCK

ENABLE

t

rem

RESET

20 ns

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

Q8

Q9

C

out

t

PHL

t

PHL

t

PLH

t

PLH

t

PLH

t

PLH

t

PLH

t

PLH

t

THL

t

THL

t

TLH

t

PLH

t

PLH

t

PLH

t

TLH

t

PLH

t

PHL

t

PHL

t

PHL

t

PHL

50%

t

PHL

t

PHL

90%

10%

t

THL

t

PHL

t

THL

t

PHL

t

THL

t

TLH

t

THL

t

PHL

t

rem

t

su

20 ns

20 ns20 ns

t

PLH

90%

10%

50%

t

TLH

t

TLH

t

TLH

t

TLH

t

TLH

t

THL

t

THL

t

THL

t

THL

t

PHL

t

THL

90%

50%

10%

20 ns

t

PLH

t

TLH

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

OH

V

OL

V

OH

V

OL

V

OH

V

OL

V

OH

V

OL

V

OH

V

OL

V

OH

V

OL

V

OH

V

OL

V

OH

V

OL

V

OH

V

OL

V

OH

V

OL

V

OH

V

OL

MC14017B

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7

PACKAGE DIMENSIONS

PDIP–16

P SUFFIX

PLASTIC DIP PACKAGE

CASE 648–08

ISSUE R

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN

FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

–A–

B

F

C

S

H

G

D

J

L

M

16 PL

SEATING

18

916

K

PLANE

–T–

M

A

M

0.25 (0.010) T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.740 0.770 18.80 19.55

B 0.250 0.270 6.35 6.85

C 0.145 0.175 3.69 4.44

D 0.015 0.021 0.39 0.53

F 0.040 0.70 1.02 1.77

G 0.100 BSC 2.54 BSC

H 0.050 BSC 1.27 BSC

J 0.008 0.015 0.21 0.38

K 0.110 0.130 2.80 3.30

L 0.295 0.305 7.50 7.74

M 0 10 0 10

S 0.020 0.040 0.51 1.01

SOIC–16

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751B–05

ISSUE J

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

18

16 9

SEATING

PLANE

F

J

M

R

X 45

G

8 PLP

–B–

–A–

M

0.25 (0.010) B

S

–T–

D

K

C

16 PL

S

B

M

0.25 (0.010) A

S

T

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 9.80 10.00 0.386 0.393

B 3.80 4.00 0.150 0.157

C 1.35 1.75 0.054 0.068

D 0.35 0.49 0.014 0.019

F 0.40 1.25 0.016 0.049

G 1.27 BSC 0.050 BSC

J 0.19 0.25 0.008 0.009

K 0.10 0.25 0.004 0.009

M 0 7 0 7

P 5.80 6.20 0.229 0.244

R 0.25 0.50 0.010 0.019

MC14017B

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8

PACKAGE DIMENSIONS

H

E

A

1

DIM MIN MAX MIN MAX

INCHES

––– 2.05 ––– 0.081

MILLIMETERS

0.05 0.20 0.002 0.008

0.35 0.50 0.014 0.020

0.18 0.27 0.007 0.011

9.90 10.50 0.390 0.413

5.10 5.45 0.201 0.215

1.27 BSC 0.050 BSC

7.40 8.20 0.291 0.323

0.50 0.85 0.020 0.033

1.10 1.50 0.043 0.059

0

0.70 0.90 0.028 0.035

––– 0.78 ––– 0.031

A

1

H

E

Q

1

L

E

10

0

10

L

E

Q

1

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS D AND E DO NOT INCLUDE

MOLD FLASH OR PROTRUSIONS AND ARE

MEASURED AT THE PARTING LINE. MOLD FLASH

OR PROTRUSIONS SHALL NOT EXCEED 0.15

(0.006) PER SIDE.

4. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

5. THE LEAD WIDTH DIMENSION (b) DOES NOT

INCLUDE DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08 (0.003)

TOTAL IN EXCESS OF THE LEAD WIDTH

DIMENSION AT MAXIMUM MATERIAL CONDITION.

DAMBAR CANNOT BE LOCATED ON THE LOWER

RADIUS OR THE FOOT. MINIMUM SPACE

BETWEEN PROTRUSIONS AND ADJACENT LEAD

TO BE 0.46 ( 0.018).

M

L

DETAIL P

VIEW P

c

A

b

e

M

0.13 (0.005)

0.10 (0.004)

1

16 9

8

D

Z

E

A

b

c

D

E

e

L

M

Z

SOEIAJ–16

F SUFFIX

PLASTIC EIAJ SOIC PACKAGE

CASE 966–01

ISSUE O

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without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular

purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,

including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or

specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be

validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.

SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or

death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold

SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable

attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim

alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.

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