Microchip Technology SAMA5D2-PTC-EK User manual

SAMA5D2-PTC-EK

SAMA5D2-PTC-EK User's Guide

Scope

This user's guide describes how to use the SAMA5D2 PTC Evaluation Kit (SAMA5D2-PTC-EK).

The SAMA5D2-PTC-EK is used to evaluate the capabilities of the Peripheral Touch Controller (PTC)

designed for the SAMA5D2 series of embedded MPUs. Refer to the Configuration Summary table in the

SAMA5D2 Series Datasheet for the list of MPUs featuring PTC.

DS50002709A-page

1

Table of Contents

Scope.............................................................................................................................. 1

1. Introduction................................................................................................................3

1.1. Document Layout......................................................................................................................... 3

1.2. Recommended Reading...............................................................................................................3

2. Product Overview...................................................................................................... 4

2.1. SAMA5D2-PTC-EK Features....................................................................................................... 4

2.2. SAMA5D2-PTC-EK Content.........................................................................................................5

2.3. Evaluation Kit Specifications........................................................................................................ 5

2.4. Power Sources............................................................................................................................. 5

3. Board Components....................................................................................................6

3.1. Board Overview............................................................................................................................6

3.2. Function Blocks............................................................................................................................ 9

3.3. External Interfaces..................................................................................................................... 31

3.4. Debugging Capabilities.............................................................................................................. 35

3.5. PIO Usage on Expansion Connectors........................................................................................40

4. Installation and Operation........................................................................................48

4.1. System and Configuration Requirements...................................................................................48

4.2. Board Setup............................................................................................................................... 48

5. Appendix A. Schematics and Layouts..................................................................... 49

6. Revision History.......................................................................................................62

6.1. Rev. A - 12/2017.........................................................................................................................62

The Microchip Web Site................................................................................................ 63

Customer Change Notification Service..........................................................................63

Customer Support......................................................................................................... 63

Microchip Devices Code Protection Feature................................................................. 63

Legal Notice...................................................................................................................64

Trademarks................................................................................................................... 64

Quality Management System Certified by DNV.............................................................65

Worldwide Sales and Service........................................................................................66

SAMA5D2-PTC-EK

DS50002709A-page

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1. Introduction

1.1 Document Layout

The document is organized as follows:

•

Chapter 1. "Introduction"

•

Chapter 2. "Product Overview" – Important information about the SAMA5D2-PTC-EK board

• Chapter 3. "Board Components" – Specifications of the SAMA5D2-PTC-EK and high-level

description of the major components and interfaces

• Chapter 4. "Installation and Operation" – Instructions on how to get started with the SAMA5D2-

PTC-EK

• Appendix A. "Schematics and Layouts" – SAMA5D2-PTC-EK schematics and layout diagrams

1.2 Recommended Reading

The following Microchip document is available and recommended as a supplemental reference resource:

• SAMA5D2 Series Datasheet. Lit. Number DS60001476

SAMA5D2-PTC-EK

Introduction

DS50002709A-page

3

2. Product Overview

2.1 SAMA5D2-PTC-EK Features

The SAMA5D2-PTC-EK follows the Microchip MPU strategy for low cost evaluation kits with maximum

reuse capability

, and is built on the SAMA5D2 Xplained Ultra (XUL

T) hardware and software ecosystem.

This board is mainly dedicated to evaluating the Peripheral Touch Controller capabilities.

Table 2-1. SAMA5D2-PTC-EK Features

Characteristics Specifications Components

Processor SAMA5D27-CU (289-ball BGA) 14x14mm

body, 0.8mm pitch

–

Clock speed

MPU: 24 MHz, 32.768 KHz

PHY: Crystal 25 MHz

–

Memory Two 16-bit, 2-Gbit DDR2

One 4-Gbit Nand Flash

One QSPI Flash

One Serial Data Flash (optional)

One EEPROM

Winbond W972GG6KB-25

Micron MT29F4G08

Microchip SST26VF064B

Microchip SST26VF032B

Microchip 24AA02E48

Display One LCD interface connector RGB, 18 bits

SD/MMC One standard SD card interface

One microSD card interface

With 3.3V/1.8V power switch

–

USB One USB host type A

One USB device type MicroAB

One USB HSIC

With 5V power switch

–

Connector not mounted

Ethernet One ETH PHY Micrel KSZ8081RN

Debug Port One JLINK-OB/ JLINK-CDC

One JTAG interface

Embedded JLINK-OB and JLINK-

CDC (ATSAM3U4C TFBGA100)

Board Monitor One RGB (Red, Green, Blue) LED

Four push button switches

–

DisableBoot, Reset, WakeUp, User

Free

Expansion One set of XPRO WINGS connectors

One ITO FLEX connector

One Port B connector

One PIOBU connector

One mikroBUS connector

Dedicated PTC QTouch

Optional

–

SAMA5D2-PTC-EK

Product Overview

DS50002709A-page

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Characteristics Specifications Components

Board Supply From USB A and USB JLINK-OB 5VDC

Backup Power Supply SuperCap ELNA DSK-3R3H204T614-H2L

2.2 SAMA5D2-PTC-EK Content

The SAMA5D2-PTC-EK evaluation kit includes the following:

•

The SAMA5D2-PTC-EK board

•

A USB cable

2.3 Evaluation Kit Specifications

Table 2-2. Evaluation Kit Specifications

Characteristic Specification

Board SAMA5D2-PTC-EK

Board supply voltage USB-powered

Temperature Operating: 0°C to +70°C

Storage: –40°C to +85°C

Relative humidity 0 to 90% (non-condensing)

Main board dimensions 135 × 90 × 20 mm

RoHS status Compliant

Board identification SAMA5D2 Peripheral Touch Controller Evaluation Kit

2.4 Power Sources

Several options are available to power up the SAMA5D2-PTC-EK board:

•

USB powering through the USB Micro-AB connector (J4 - default configuration)

•

Powering through the USB Micro-AB connector on the JLlink-OB Embedded Debugger interface

(J9)

Table 2-3. Electrical Characteristics

Electrical Parameter Value

Input voltage 5VCC

Maximum input voltage 6VCC

Maximum 3.3VDC current available 1.2A

I/O voltage 3.3V only

SAMA5D2-PTC-EK

Product Overview

DS50002709A-page

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3. Board Components

This section covers the specifications of the SAMA5D2-PTC-EK and provides a high-level description of

the board's major components and interfaces. This document is not intended to provide a detailed

documentation about the processor or about any other component used on the board. It is expected that

the user will refer to the appropriate documents of these devices to access detailed information.

3.1 Board Overview

The fully-featured SAMA5D2-PTC-EK board integrates multiple peripherals and interface connectors, as

shown in the figure below

.

3.1.1 Default Jumper Settings

The figure below shows the default jumper settings. Jumpers in red are configuration items and current

measurement points. Jumpers in blue are not populated.

SAMA5D2-PTC-EK

Board Components

DS50002709A-page

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Figure 3-1. Default Jumper Settings

The following table describes the functionality of the jumpers.

Table 3-1. SAMA5D2-PTC-EK Jumper Settings

Jumper Default Function

JP1 Closed VDD_MAIN_5V current measurement

JP2 Closed VDDOSC, VDDUTMII, VDDANA, VDDAUDIOPLL current measurement

JP3 Closed VDDISC + VDDIOP0/1/2 current measurement

JP4 Closed VDDIODDR_MPU current measurement

JP5 Closed VDDCORE current measurement

JP6 Closed VDDBU current measurement

JP7 Open PIOBU1, PIOBU7

JP8 Closed Disables NAND_CS (open=disable)

JP9 Open Enables JTAG-CDC (closed=disable)

JP10 Open Enables JTAG-OB (closed=disable)

JP11 Open Erases SAM3U Flash Code (closed = erase)

SAMA5D2-PTC-EK

Board Components

DS50002709A-page 7

Jumper Default Function

WARNING

Warning: This jumper is reserved for factory configuration and should

never be used by the end user.

JP12 Closed Powers mikroBUS extension (3.3V)

JP13 Open Disables QSPI

JP14 1-2 Enables 3.3V JLINK-OB, connected to shutdown circuitry

2-3 Enables 3.3V JLINK-OB, always ON

3.1.2 Connectors on Board

The following table describes the interface connectors on the SAMA5D2-PTC-EK.

Table 3-2. SAMA5D2-PTC-EK Board Interface Connectors

Connector Interfaces to

J1 PIOBU, tamper and analog comparator connector (not populated)

J2 JTAG, 10-pin IDC connector

J3 USB Host B. Supports USB host using a type A connector

J4 USB A Device. Supports USB device using a type Micro-AB connector

J5 USB-C HSIC header (not populated)

J6 Standard SDMMC connector

J7 microSD connector

J8 Ethernet 10/100 RJ45

J9 USB-A MicroAB, JLink-OB port

J10 PCB connector for factory-programming the JLINK-OB/SAM3U

J11, J12 Xplained Pro expansion connectors (PTC-dedicated add-on boards)

J13 PIOs PortB connector

J14 ITO connector

J15 A&B mikroBUS connector

J16 Expansion TFT LCD connector for display module

SAMA5D2-PTC-EK

Board Components

DS50002709A-page

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3.2 Function Blocks

Figure 3-2. SAMA5D2-PTC-EK Block Diagram

POWER

MONITOR

JLINK-OB

JTAG Interface

JLINK Power

5v/3v3

USB

Connector

Function Select

System Supplies

POWER

REGULATORS

SHDN

UART

MPU JTAG

Interface

JTAG

Switch

JTAG

LCD (18bits)

TWI/SPI

RJ45

USB A&B

SDHC0

SDHC1

SAMA5D2-PTC-EK

Push

Button

FPC Connector

DEBUG

Interface

Reset, Wkup

DisBoot, User

SD Card

Connector

uSD

Connector

3v3, 2v5,1v8, 1v2

VDDBU

GPIO

USB

Detection

ETH

PHY

PTC

QSPI

Flash

DDR2

SDRAM

DDR2

SDRAM

Power

Cap

Serial

EEprom

Nand

Flash

PIOBU Connector

MikroBUS

Interface

ITO Connector

XPRO (1&2)

PTC Interface

GPIO

PortB[0-7]

Power

Switch

VBUS

5v

USB-B

Connector

USB-A

Connector

SPI

Flash

Leds

JLINK-OB

JLINK-CDC

SAMA5D27

RGB

Leds

Tri

State

3.2.1 Processor

The SAMA5D2 Series is a high-performance, power-efficient embedded MPU based on the ARM

®

Cortex

®

-A5 processor.

Please refer to the SAMA5D2 Series datasheet for more information.

3.2.2 Power Supply T

opology and Power Distribution

3.2.2.1 Input Power Options

Two options are available to power the SAMA5D2-PTC-EK board. The USB-powered operation is the

default configuration and comes from the USB device ports (J4-J9) connected to a PC or a 5VDC supply.

Such USB power source is sufficient to supply the board in most applications. It is important to note that

when the USB-powered operation is used, the USB port down the way has a limited powering capability.

If the USB-B Host port (J3) is required to provide full powering capabilities to the target application, it is

recommended to use an external DC supply instead of a USB power source.

The following figure is a schematic of the power options.

SAMA5D2-PTC-EK

Board Components

DS50002709A-page 9

Figure 3-3. Input Powering

VDD_MAIN_5V

GND_POWER

VBUS_USBA

VBUS_JLINK

U1A

DMP2160UFD

1

2

6

7

C1

100nF

C0402

U4A

DMP2160UFD

1

2

6

7

R5 100K

R0402

R6 DNP

R0402

U1B

DMP2160UFD

4

5

3

8

JP1

Header 1X2

1

2

C12

100nF

C0402

R1

10K

R0402

U4B

DMP2160UFD

4

5

3

8

R2

100K

R0402

JPR1

Jumper

C2

100nF

C0402

Note: USB-powered operation eliminates additional wires and batteries. It is the preferred mode of

operation for any project that requires only a 5V source at up to 500 mA.

Jumper JP1 is used to perform MAIN_5V current measurements on the SAMA5D2-PTC-EK board.

3.2.2.2 Power Supply Requirements and Restrictions

Detailed information on the device power supplies is provided in tables “SAMA5D2 Power Supplies” and

“Power Supply Connections” in the SAMA5D2 Series datasheet.

3.2.2.3 Power-up and Power-down Considerations

Power-up and power-down considerations are described in section “Power Considerations” of the

SAMA5D2 Series datasheet.

CAUTION

Caution: The power-up and power-down sequences provided in the SAMA5D2 Series

datasheet must be respected for reliable operation of the device.

3.2.2.4 Power Management

The board power management uses three types of regulators:

• One dual synchronous step-down DC-DC regulator (U2 MIC2230) generates the 3.3V/800mA and

1.8V/800mA power lines and utilizes a high-ef

ficiency, fixed-frequency (2.5 MHz), current-mode

PWM control architecture that requires a minimum number of external components.

• One ultra low-dropout linear regulator (U3 MIC47053) generates the 1.25V/500mA from the 1.8V

source.

• One high-performance single 2.5V/150mA is used as a VDDFUSE generator (U5 MIC5366).

The main regulators are enabled through a Field Effect Transistor (FET) scheme. The processor can

assert SHDN (a VDDBU-powered I/O) to shut down the regulators to enter Backup mode. All regulators

on the board are also shut down by the action of the SHDN signal.

A 3.3V battery (supercap) is implemented to permanently maintain VDDBU voltage (note: jumper JP6

must be in place). The board can be woken up by action on the PB4 button, which drives the WKUP

signal (also a VDDBU-powered I/O).

The figure below shows the power management scheme.

SAMA5D2-PTC-EK

Board Components

DS50002709A-page

10

Figure 3-4. Board Power Management

EN_1

EN_VDD_1V25

STARTB

FPWM#

EN_1

EN_VDD_1V25

VDD_MAIN_5V

GND_POWER

VDD_3V3VDD_1V8

VDD_MAIN_5V

VDD_1V8

VDD_1V25

VDD_MAIN_5V

GND_POWER GND_POWER

GND_POWER

VDD_MAIN_5V

VDD_3V3

VDD_MAIN_5V

GND_POWER

VDD_3V3

GND_POWER

VDD_3V3

GND_POWER

GND_POWERGND_POWER

GND_POWER

SHDN

C4

10uF

C0603

U2

MIC2230-GSYML

MLF3x3mm

AVIN

3

EN1

11

FPWM#

7

SW1

8

OUT1

12

AGND

5

PGND

6

OUT2

1

SW2

4

PGOOD

10

EN2

2

VIN

9

EPAD

13

R249 4.7K

R0402

R13

39K

R0402

C6

10uF

C0603

R3

100K

R0402

R251

10K

R0402

R12

220K

R0402

C10 390pF

C0402

C7

100nF

C0402

L2 LQH43CN2R2M03L

L1812

C3

10uF

C0603

R248

20K

R0402

R10

DNP

R0402

R11

100K

R0402

C13

4.7nF

C0402

R250

3.3K

R0402

L1 LQH43CN2R2M03L

L1812

C5

1uF

C0603

Q1

BSS138

SOT23_123

1

3

2

R4

10K

R0402

C9

1uF

C0603

D1

PMEG6010CEGWX

sod123

Q2

BSS138

SOT23_123

1

3

2

C8

100nF

C0402

R9

100K

R0402

C11

10uF

C0603

Q3

BSS138

SOT23_123

1

3

2

U3

MIC47053YMT

BIAS

1

GND

2

IN1

3

IN2

4

ADJ

6

OUT

5

EPAD

9

PGOOD

7

EN

8

Q4

BC847C

SOT-23

1

32

R8 100K

R0402

C14

2.2uF

C0603

NRST

3.2.2.5 Supply Group Configuration

The main regulators provide all power supplies required by the SAMA5D2 device:

• 1.25V VDDCORE, VDDPLLA, VDDUTMIC, VDDHSIC

• 1.8V VDDIODDR, VDDSDHC1V8

• 2.5V VDDFUSE

• 3.3V VDDIOP0, VDDIOP1, VDDIOP2, VDDISC

• 3.3V VDDOSC, VDDUTMI, VDDANA, VDDAUDIOPLL

• 3.3V VDDBU

SAMA5D2-PTC-EK

Board Components

DS50002709A-page

11

Figure 3-5. Power Lines Distribution

For DDR2 For MPU

VDDHSIC

V

DD_3V3

VDD_1V25

VDDCORE

VDDIOP0

VDDIOP2

VDDIOP1

VDDPLLA

VDDUTMIC

VDDIODDR

VDDAUDIOPLL

VDDANA

VDDOSC

VDDUTMII

VDDISC

VDD_1V8 VDDSDHC1V8

L3

BLM18PG181SN1D

R0603

1 2

R16

2R2

R0603

R15

2R2

R0603

R17

0R

R0603

L7

MLZ1608N100L

L0603

L11

BLM18PG181SN1D

R0603

1 2

L10

BLM18PG181SN1D

R0603

1

2

JP5

Header 1X2

1

2

R18

0R

R0603

L4

BLM18PG181SN1D

R0603

1 2

L14

BLM18PG181SN1D

1

2

L9

MLZ1608N100L

L0603

JP4

Header 1X2

1

2

L13

BLM18PG181SN1D

R0603

1 2

L6

BLM18PG181SN1D

R0603

1

2

L8

MLZ1608N100L

L0603

R19

2R2

R0603

L5

BLM18PG181SN1D

R0603

1 2

L12

BLM18PG181SN1D

R0603

1 2

JP3

Header 1X2

1

2

JP2

Header 1X2

1

2

Figure 3-6. Processor Power Lines Supplies

(3V3)

(1V2)

(1V8)

(3V3)

)3

V3(

)3V3()3V3

(

)5

V

2(

)

2V1(

(3V3)

(1V8)

(1V2)

(2V5)

(3V3)

(1V2)

)3

V3(

)2V

1

(

(3V3)

(3V3 or 1V8)

VDDBU

VDDCORE

VDDPLLA

VDDIOP0

VDDIOP1

VDDIOP2

VDDHSIC

VDDUTMIC

VDDUTMII

VDDSDHC

VDDPLLA

VDDOSC

VDDISC

VDDFUSE

VDDAUDIOPLL

VDDBU

VDDIODDR

VDDANA

VDDIOP0

VDDIOP1

VDDIOP2

VDDHSIC

VDDFUSE

VDDUTMII

VDDSDHC

VDDOSC VDDISC

VDDUTMIC

VDDCORE

VDDIODDR

VDDAUDIOPLL

GND_POWER

VDDBU

GND_POWER

VDDCORE

GND_POWER

VDDIODDR

VDDANA

GND_POWER

VDDIOP0

GND_POWER

VDDIOP1

GND_POWER

VDDIOP2

GND_POWER

VDDHSIC

GND_POWER

VDDFUSE

GND_POWER

VDDUTMII

GND_POWER

VDDSDHC

GND_POWER

VDDPLLA

GND_POWER

VDDOSC

VDDISC

GND_POWER

VDDUTMIC

GND_POWER

GNDUTMII

GND_POWER

VDDAUDIOPLL

C35

100nF

C0402

C51

1nF

C0402

C54

4.7uF

C0805

C31

100nF

C0402

C25

4.7uF

C0805

C61

1nF

C0402

C56

100nF

C0402

C37

100nF

C0402

C59

1nF

C0402

C20

10uF

C0603

C19

10uF

C0603

C21

100nF

C0402

C42

100nF

C0402

C40

100nF

C0402

C52

1nF

C0402

C50

100nF

C0402

C48

100nF

C0402

C26

100nF

C0402

C53

100nF

C0402

C28

10uF

C0603

C30

100nF

C0402

C34

100nF

C0402

C60

1nF

C0402

C46

100nF

C0402

C41

4.7uF

C0805

C49

100nF

C0402

C27

10uF

C0603

C44

100nF

C0402

R20

1R-1%

R0603

C29

100nF

C0402

C36

100nF

C0402

R21

1R-1%

R0603

C24

4.7uF

C0805

C47

100nF

C0402

C32

100nF

C0402

ATSAMA5D27C-CN

U6G

bga289p8

GNDADC

K5

GNDANA

L3

GNDBU

N6

GNDCORE_1

E7

GNDCORE_2

E9

GNDCORE_3

H4

GNDCORE_4

K12

GNDCORE_5

M5

GNDCORE_6

M9

GNDDDR_1

D14

GNDDDR_2

E11

GNDDDR_3

E12

GNDDDR_4

E14

GNDDDR_5

H14

GNDDDR_6

J14

GNDDDR_7

L14

GNDDPLL

T5

GNDAUDIOPLL

T4

GNDIOP0_1

F6

GNDIOP0_2

G7

GNDIOP1_1

M13

GNDIOP1_2

P14

GNDIOP2

F9

GNDISC

G4

GNDOSC

T6

GNDPLLA

U5

GNDSDMMC

R11

GNDUTMII

P9

GNDUTMIC

R7

VDDADC

L5

VDDANA

K3

VDDBU

N7

VDDCORE_1

D7

VDDCORE_2

D9

VDDCORE_3

H3

VDDCORE_4

K13

VDDCORE_5

N5

VDDCORE_6

N9

VDDDDR_1

D11

VDDDDR_2

D12

VDDDDR_3

D15

VDDDDR_4

E15

VDDDDR_5

H15

VDDDDR_6

J15

VDDDDR_7

L15

VDDAUDIOPLL

T3

VDDFUSE

M12

VDDHSIC

R9

VDDIOP0_1

E6

VDDIOP0_2

F7

VDDIOP1_1

N13

VDDIOP1_2

R14

VDDIOP2

F10

VDDISC

F4

VDDOSC

T7

VDDPLLA

U4

VDDSDMMC

P11

VDDUTMII

P8

VDDUTMIC

P7

C55

100nF

C0402

C23

100nF

C0402

C43

100nF

C0402

C38

100nF

C0402

C58

1nF

C0402

C57

100nF

C0402

C33

100nF

C0402

C39

100nF

C0402

C45

100nF

C0402

C22

100nF

C0402

3.2.2.6 VDDFUSE

The SAMA5D2-PTC-EK board embeds a 2.5V regulator for fuse box programming.

SAMA5D2-PTC-EK

Board Components

DS50002709A-page

12

Figure 3-7. VDDFUSE Regulator

VDD_3V3

GND_POWER

VDDFUSE

EN_1 12

C16

1uF

C0603

U5

MIC5366-2.5YMT

MLF1x1mm

VIN

4

GND

2

VOUT

1

EN

3

EPAD

5

C15

1uF

C0603

3.2.2.7 Backup Power Supply

The SAMA5D2-PTC-EK board requires a power source in order to permanently power the backup part of

the SAMA5D2 device (refer to SAMA5D2 Series datasheet). The super capacitor C17 sustains such

permanent power to VDDBU when all system power sources are off.

Figure 3-8. VDDBU Powering Options

(Super)-Capacitor

energy storage

VDDBU

GND_POWER

VDD_3V3

C18

100nF

C0402

JP6

Header 1X2

1

2

+

C17

0.2F/3.3V

c117x68

D2

PMEG6010CEGWX

sod123

R14 100R-1%

R0402

D3

BAT54C

SOT23_123

3

1

2

3.2.3 Reset Circuitry

The reset sources for the SAMA5D2-PTC-EK board are:

• Power-on reset from the power management unit,

•

Push button reset BP3,

• JTAG or JLINK-OB reset from an in-circuit emulator.

Figure 3-9. Main Reset Control

STARTB

GND_POWER

VDD_MAIN_5V

VDD_3V3

NRST

R13

39K

R0402

R12

220K

R0402

R11

100K

R0402

D1

PMEG6010CEGWX

sod123

Q3

BSS138

SOT23_123

1

3

2

Q4

BC847C

SOT-23

1

32

C14

2.2uF

C0603

PowerGood VDD_1V25

3.2.4 Shutdown Circuitry

The SHDN signal, output of Shutdown Controller (SHDN), drives the shutdown request to the power

supply

. This output signal is supplied by VDDBU, which is present in Backup mode.

The Shutdown Controller manages the main power supply and is connected to the ENABLE input pin of

the DC/DC converter providing the main power supplies of the system.

SAMA5D2-PTC-EK

Board Components

DS50002709A-page

13

Figure 3-10. Shutdown Controller

STARTB

EN_1

VDD_MAIN_5V

GND_POWER GND_POWER

VDD_3V3

GND_POWER

SHDN

R3

100K

R0402

Q1

BSS138

SOT23_123

1

3

2

R4

10K

R0402

Q2

BSS138

SOT23_123

1

3

2

C8

100nF

C0402

3.2.5 Push Button Switches

The SAMA5D2-PTC-EK features four push buttons:

• One board reset push button (BP3). When pressed and released, it causes a power-on reset of the

board.

•

One wakeup push button (BP4) connected to the SAMA5D2 WKUP pin, used to exit the processor

from low-power mode.

• One disable boot push button (BP2) used to devalidate the boot memories (refer to CS Disable).

Figure 3-11. System Push Buttons

WAKE UP

RESET

DIS BOOT

GND_POWER

VDDBU

DISABLE_BOOT

NRST

WKUP

R146 100R-1%

r0402

BP3 Tact Switch

FSM2JSML

R147 100R-1%

r0402

R238 10K

R0402

BP2 Tact Switch

FSM2JSML

R145 100R-1%

r0402

BP4 Tact Switch

FSM2JSML

• One user push button (BP1) connected to PIO PB10.

Figure 3-12. User Push Button

USER BUTTON

PA10_USER_BT

R144 0R

R0402

BP1 Tact Switch

FSM2JSML

GND_POWER

3.2.6 Clock Circuitry

The embedded microcontroller generates its necessary clocks based on two crystal oscillators: one slow

clock (SLCK) oscillator running at 32.768 KHz and one main clock oscillator running at 24 MHz.

The SAMA5D2-PTC-EK board includes four clock sources:

• The two clocks mentioned above are alternatives for the SAMA5D2 processor (24 MHz, 32.768

kHz)

•

One crystal oscillator for the Ethernet RMII chip (25 MHz)

• One crystal oscillator for the JLink-OB microcontroller (12 MHz)

SAMA5D2-PTC-EK

Board Components

DS50002709A-page

14

Figure 3-13. MPU Clock Circuitry

XIN

XOUT

XOUT32

XIN32

GND_POWERGND_POWER

GND_POWER

R122

DNP

R0402

C98

20pF

C0402

C97

20pF

C0402

R123 DNP

R0402

C96

20pF

C0402

Y1

24MHz CL=10pF

x4s32x25

1 4

32

C99

20pF

C0402

Y2

32.768KHz CL=12.5pF

X4S70X15

1

23

4

3.2.7 Memory

3.2.7.1 Memory Organization

The SAMA5D2 features a DDR/SDR memory interface and an External Bus Interface (EBI) to enable

interfacing to a wide range of external memories and to almost any kind of parallel peripheral.

This section describes the memory devices mounted on the SAMA5D2-PTC-EK board:

• T

wo DDR2 SDRAMs

• One NAND Flash

• One QSPI Flash

• One SPI Flash (optional)

• One serial EEPROM

Additional memory can be added to the board by:

• Installing an SD or MMC card in the SD/MMC0 or SD/MMC1 slot,

• Using the USB-B port.

Support is dependent upon driver support in the OS.

3.2.7.2 DDR2/SDRAMs

Two DDR2/SDRAMs (W972GG6KB-25-2 Gbits = 16 Mbits x 16 x 8 banks) are used as main system

memory, totalling 4 Gbits of SDRAM on the board. The memory bus is 32 bits wide and operates with a

frequency of up to 166 MHz.

The figure below illustrates the implementation for the DDR2 memories.

SAMA5D2-PTC-EK

Board Components

DS50002709A-page

15

Figure 3-14. DDR2 SDRAMs

DDR_VREFDDR_VREF

DDR_DQM0

DDR_DQM1

DDR_DQM2

DDR_DQM3

DDR_DQS0-

DDR_DQS0+

DDR_DQS1+

DDR_DQS1-

DDR_DQS2+

DDR_DQS2-

DDR_DQS3+

DDR_DQS3-

DDR_BA1

DDR_BA0

DDR_BA1

DDR_BA0

DDR_WE DDR_WE

DDR_CSDDR_CS

DDR_CLK-

DDR_CLK+

DDR_CLK-

DDR_CLK+

DDR_CKE DDR_CKE

DDR_CAS

DDR_RAS

DDR_CAS

DDR_RAS

DDR_D16

DDR_D17

DDR_D18

DDR_D19

DDR_D20

DDR_D21

DDR_D22

DDR_D23

DDR_D24

DDR_D25

DDR_D26

DDR_D27

DDR_D28

DDR_D29

DDR_D30

DDR_D31

DDR_D0

DDR_D1

DDR_D2

DDR_D3

DDR_D4

DDR_D5

DDR_D6

DDR_D7

DDR_D8

DDR_D9

DDR_D10

DDR_D11

DDR_D12

DDR_D13

DDR_D14

DDR_D15

DDR_A0

DDR_A1

DDR_A2

DDR_A3

DDR_A4

DDR_A5

DDR_A6

DDR_A7

DDR_A8

DDR_A9

DDR_A10

DDR_A11

DDR_A12

DDR_A0

DDR_A1

DDR_A2

DDR_A3

DDR_A4

DDR_A5

DDR_A6

DDR_A7

DDR_A8

DDR_A9

DDR_A10

DDR_A11

DDR_A12

DDR_BA2 DDR_BA2

DDR_A13DDR_A13

GND_POWER

VDD_1V8

GND_POWER

VDD_1V8

GND_POWER

VDD_1V8

GND_POWER

VDD_1V8

GND_POWER

C94

100nF

C0402

R29 DNP R0402

C95

1nF

C0402

U8

W972GG6KB-25

bga84-32-1509e

A0

M8

A1

M3

A2

M7

A3

N2

A4

N8

A5

N3

A6

N7

A7

P2

A8

P8

A9

P3

A10

M2

A11

P7

A12

R2

A13

R8

BA0

L2

BA1

L3

BA2

L1

CKE

K2

CK_P

J8

CK_N

K8

RAS

K7

CAS

L7

WE

K3

CS

L8

DQ0

G8

DQ1

G2

DQ2

H7

DQ3

H3

DQ4

H1

DQ5

H9

DQ6

F1

DQ7

F9

DQ8

C8

DQ9

C2

DQ10

D7

DQ11

D3

DQ12

D1

DQ13

D9

DQ14

B1

DQ15

B9

LDQS_P

F7

NU/LDQS_N

E8

UDQS_P

B7

NU/UDQS_N

A8

LDM

F3

UDM

B3

ODT

K9

NC1

A2

NC2

E2

NC3

R3

NC4

R7

VDD1

A1

VDD2

E1

VDD3

J9

VDD4

M9

VDD5

R1

VDDQ1

A9

VDDQ2

C1

VDDQ3

C3

VDDQ4

C7

VDDQ5

C9

VDDQ6

E9

VDDQ7

G1

VDDQ8

G3

VDDQ9

G7

VDDQ10

G9

VDDL

J1

VREF

J2

VSS1

A3

VSS2

E3

VSS3

J3

VSS4

N1

VSS5

P9

VSSQ1

A7

VSSQ2

B2

VSSQ3

B8

VSSQ4

D2

VSSQ5

D8

VSSQ6

E7

VSSQ7

F2

VSSQ8

F8

VSSQ9

H2

VSSQ10

H8

VSSDL

J7

U7

W972GG6KB-25

bga84-32-1509e

A0

M8

A1

M3

A2

M7

A3

N2

A4

N8

A5

N3

A6

N7

A7

P2

A8

P8

A9

P3

A10

M2

A11

P7

A12

R2

A13

R8

BA0

L2

BA1

L3

BA2

L1

CKE

K2

CK_P

J8

CK_N

K8

RAS

K7

CAS

L7

WE

K3

CS

L8

DQ0

G8

DQ1

G2

DQ2

H7

DQ3

H3

DQ4

H1

DQ5

H9

DQ6

F1

DQ7

F9

DQ8

C8

DQ9

C2

DQ10

D7

DQ11

D3

DQ12

D1

DQ13

D9

DQ14

B1

DQ15

B9

LDQS_P

F7

NU/LDQS_N

E8

UDQS_P

B7

NU/UDQS_N

A8

LDM

F3

UDM

B3

ODT

K9

NC1

A2

NC2

E2

NC3

R3

NC4

R7

VDD1

A1

VDD2

E1

VDD3

J9

VDD4

M9

VDD5

R1

VDDQ1

A9

VDDQ2

C1

VDDQ3

C3

VDDQ4

C7

VDDQ5

C9

VDDQ6

E9

VDDQ7

G1

VDDQ8

G3

VDDQ9

G7

VDDQ10

G9

VDDL

J1

VREF

J2

VSS1

A3

VSS2

E3

VSS3

J3

VSS4

N1

VSS5

P9

VSSQ1

A7

VSSQ2

B2

VSSQ3

B8

VSSQ4

D2

VSSQ5

D8

VSSQ6

E7

VSSQ7

F2

VSSQ8

F8

VSSQ9

H2

VSSQ10

H8

VSSDL

J7

C72

100nF

C0402

R32 0R

R0402

C75

1nF

C0402

R31

DNP R0402

R30 0R

R0402

3.2.7.3 DDR_CAL Analog Input

One specific analog input, DDR_CAL, is used to calibrate all DDR I/Os.

Table 3-3.

Calibration Cell DDR_CAL Value

Memory Resistor value

LPDDR2/LPDDR3 24K

DDR3L 23K

DDR3 22K

DDR2/LPDDR1 21K

SAMA5D2-PTC-EK

Board Components

DS50002709A-page

16

Figure 3-15. DDR Signals and CAL Analog Input

DDR_D0

DDR_D1

DDR_D2

DDR_D3

DDR_D4

DDR_D5

DDR_D6

DDR_D7

DDR_D8

DDR_D9

DDR_D10

DDR_D11

DDR_D12

DDR_D13

DDR_D14

DDR_D15

DDR_D16

DDR_D17

DDR_D18

DDR_D19

DDR_D20

DDR_D21

DDR_D22

DDR_D23

DDR_D24

DDR_D25

DDR_D26

DDR_D27

DDR_D28

DDR_D29

DDR_D30

DDR_D31

DDR_DQM0

DDR_DQM1

DDR_DQM2

DDR_DQM3

DDR_DQS0+

DDR_DQS0-

DDR_DQS1+

DDR_DQS1-

DDR_DQS2+

DDR_DQS2-

DDR_DQS3+

DDR_DQS3-

DDR_A0

DDR_A1

DDR_A2

DDR_A3

DDR_A4

DDR_A5

DDR_A6

DDR_A7

DDR_A8

DDR_A9

DDR_A10

DDR_A11

DDR_A12

DDR_A13

DDR_BA0

DDR_BA1

DDR_RAS

DDR_CAS

DDR_BA2

DDR_CS

DDR_WE

DDR_VREF

DDR_RESETN

DDR_CLK+

DDR_CLK-

DDR_CKE

GND_POWER

VDDIODDR

R23

100K

R0402

R24

21K-1%

R0402

R25

100K

R0402

C64

22pF

C0402

ATSAMA5D27C-CN

U6E

bga289p8

DDR_A0

F12

DDR_A1

C17

DDR_A10

C15

DDR_A11

A16

DDR_A12

A17

DDR_A13

G11

DDR_A2

B17

DDR_A3

B16

DDR_A4

C16

DDR_A5

G14

DDR_A6

F14

DDR_A7

F11

DDR_A8

C14

DDR_A9

D13

DDR_BA0

H12

DDR_BA1

H13

DDR_BA2

F17

DDR_CAL

E13

DDR_CAS

G12

DDR_CKE

F16

DDR_CLK

E17

DDR_CLKN

D17

DDR_CS

G13

DDR_D0

B12

DDR_D1

A12

DDR_D10

H17

DDR_D11

K17

DDR_D12

K16

DDR_D13

J13

DDR_D14

K14

DDR_D15

K15

DDR_D16

B8

DDR_D17

B9

DDR_D18

C9

DDR_D19

A9

DDR_D2

C12

DDR_D20

A10

DDR_D21

D10

DDR_D22

B11

DDR_D23

A11

DDR_D24

J12

DDR_D25

H10

DDR_D26

J11

DDR_D27

K11

DDR_D28

L13

DDR_D29

L11

DDR_D3

A13

DDR_D30

L12

DDR_D31

M17

DDR_D4

A14

DDR_D5

C13

DDR_D6

A15

DDR_D7

B15

DDR_D8

G17

DDR_D9

G16

DDR_DQM0

C11

DDR_DQM1

G15

DDR_DQM2

C8

DDR_DQM3

H11

DDR_DQS0

B13

DDR_DQS1

J17

DDR_DQS2

C10

DDR_DQS3

L17

DDR_DQSN0

B14

DDR_DQSN1

J16

DDR_DQSN2

B10

DDR_DQSN3

L16

DDR_RAS

F13

DDR_RESETN

E16

DDR_VREFCM

D16

DDR_VREFB0

H16

DDR_WE

F15

C62

100nF

C0402

C63

100nF

C0402

3.2.7.4 NAND FLASH

The SAMA5D2-PTC-EK has native support for NAND Flash memory through its NAND Flash Controller.

The board implements one MT29F4G08ABA 4Gb x 16 NAND Flash connected to chip select three

(NCS3) of the microcontroller.

CAUTION

Caution: The NAND Flash interface is shared with the SDMMC1 and QSPI interfaces.

The figure below illustrates the NAND Flash memory implementation.

Figure 3-16. NAND Flash

NAND_WPn

3V3_NAND

VDD_3V3 3V3_NAND

3V3_NAND

NAND_CLE_PB1

NAND_ALE_PB0

NAND_REn_PB2

NAND_WEn_PA30

NAND_RDY_PC8

NAND_IO5_PA27

NAND_IO6_PA28

NAND_IO7_PA29

NAND_IO0_PA22

NAND_IO1_PA23

NAND_IO2_PA24

NAND_IO3_PA25

NAND_IO4_PA26

NAND_CS_PA31

R175

100K

MT29F4G08ABADAWP

U13

NC1

1

NC2

2

NC3

3

NC4

4

NC5

5

NC6

6

R/B#

7

CE#

9

NC7

10

VCC_1

12

VSS_1

13

NC9

14

NC10

15

CLE

16

ALE

17

NC21

47

VSS_4

48

RE#

8

NC8

11

WE#

18

WP#

19

DNU2

20

DNU1

21

NC11

22

NC12

23

NC13

24

VSS_2

25

NC14

26

NC15

27

NC16

28

DQ0

29

DQ1

30

DQ2

31

DQ3

32

NC17

33

VCC_2

34

DNU3

35

VSS_3

36

VCC_3

37

DNU4

38

VCC_4

39

NC18

40

DQ4

41

DQ5

42

DQ6

43

DQ7

44

NC19

45

NC20

46

R177

DNP

R174 0R

C113

100nF

R180

100K

C112

100nF

JP8

Header 1X2

1

2

C114

100nF

R179 0R

C115

100nF

R176

10K

SAMA5D2-PTC-EK

Board Components

DS50002709A-page

17

Table 3-4. NAND Flash Signal Descriptions

PIO Mnemonic Shared PIO Signal Description

PA22 NAND_D0 SDMMC1-QSPI Data 0

PA23 NAND_D1 QSPI Data 1

PA24 NAND_D2 QSPI Data 2

PA25 NAND_D3 QSPI Data 3

PA26 NAND_D4 QSPI Data 4

PA27 NAND_D5 QSPI Data 5

PA28 NAND_D6 SDMMC1 Data 6

PA29 NAND_D7 – Data 7

PA30 NANDWE SDMMC1 –

PA31 NCS3 – Chip Select

PB00 NANDALE – –

PB01 NANDCLE – –

PB02 NANDOE – –

PC08 NANRDY – –

3.2.7.5 NAND Flash CS Disable

On-board jumper JP8 controls the selection (CS#) of the NAND Flash memory.

3.2.8 Additional Memories

3.2.8.1 Serial Flash

The SAMA5D2 includes two high-speed Serial Peripheral Interface (SPI) controllers. The SPI is a full

duplex synchronous bus supporting a single master and multiple slave devices. The SPI bus consists of

the following items:

•

a serial clock line (generated by the master)

•

a data output line from the master

• a data input line to the master

• one or more active low chip select signals (output from the master)

One SPI port is used to interface with the on-board serial Flash.

The following figure illustrates the implementation of an SPI Flash memory.

Figure 3-17. Serial Flash

SPI0_CS0_PA17

GND_POWER

VDD_3V3

SPI0_MOSI_PA15

SPI0_MISO_PA16

SPI0_SPCK_PA14

C119

100nF

C0402

U16

SST26VF032B-104I/SM

soic8jg

HOLD

7

GND

4

VCC

8

CS

1

SCK

6

SI

5

SO

2

WP

3

SAMA5D2-PTC-EK

Board Components

DS50002709A-page

18

Note: The serial Flash is optional and not mounted on board.

3.2.8.2 QSPI Serial Flash

The SAMA5D2 provides two Quad Serial Peripheral Interfaces (QSPI).

A QSPI is a synchronous serial data link that provides communication with external devices in Master

mode.

The QSPI can be used in SPI mode to interface with serial peripherals (such as ADCs, DACs, LCD

controllers, CAN controllers and sensors), or in Serial Memory mode to interface with serial Flash

memories.

The QSPI allows the system to execute code directly from a serial Flash memory (XIP, or Execute In

place, technology) without code shadowing to RAM. The serial Flash memory mapping is seen in the

system as other memories (ROM, SRAM, DRAM, etc.).

With the support of the Quad SPI protocol, the QSPI allows the system to use high-performance serial

Flash memories which are small and inexpensive, instead of larger and more expensive parallel Flash

memories.

The figure below illustrates the implementation of a QSPI Flash memory.

Figure 3-18. QSPI Serial Flash

QSPI0_CS_PA23

VDD_3V3

GND_POWER

VDD_3V3

QSPI0_IO0_PA24

QSPI0_IO1_PA25

QSPI0_IO2_PA26

QSPI0_IO3_PA27 QSPI0_SCK_PA22

U14

SST26VF064B-104I/SM

soic8jg

SI/SIO0

5

SO/SIO1

2

SIO2

3

SIO3

7

SCLK

6

CS#

1

GND

4

VCC

8

C120

100nF

C0402

R186

10K

R0402

R187

10K

R0402

JP13

Header 1X2

1

2

R242

10K

A jumper (JP13) is used to disable the QSPI Flash.

Table 3-5. SPI and QSPI Signal Descriptions

PIO Mnemonic PIO Shared Signal Description

PA14 SPI0_SPCK _ SPI clock

PA15 SPI0_MOSI _ Master out - Slave in

PA16 SPI0_MISO _ Master in - Slave out

PA17 SPI0_NPCS0 _ Chip select

_ _ _ _

PA22 QSPI0_SCK SDMMC1-Nand Flash QSPI clock

PA23 QSPI0_CS Nand Flash Chip select

PA24 QSPI0_IO0 Nand Flash Data0

PA25 QSPI0_IO1 Nand Flash Data1

SAMA5D2-PTC-EK

Board Components

DS50002709A-page

19

PIO Mnemonic PIO Shared Signal Description

PA26 QSPI0_IO2 Nand Flash Data2

PA27 QSPI0_IO3 Nand Flash Data3

3.2.8.3 CS Disable

On-board push button PB2 controls the selection (CS#) of the bootable memory components (QSPI and

serial Flash) using a non-inverting 3-state buffer

.

Figure 3-19. CS Disable

BOOT_DIS

QSPI Flash CS

SPI Flash CS

QSPI0_CS_PA23

SPI0_CS0_PA17

GND_POWER

VDD_3V3

SPI0_NPCS0_PA17

QSPI0_NPCS_PA23

DISABLE_BOOT

C116

100nF

VCC

GND

U11

NL17SZ126DFT2G

1

2

3

4

5

VCC

GND

U12

NL17SZ126DFT2G

1

2

3

4

5

R184

10K

C117

100nF

R185

10K

R178

10K

The rule of operation is:

• PB2 (DISABLE_BOOT) and PB3 (RESET) pressed = booting from QSPI or optional serial Flash is

disabled.

Refer to the SAMA5D2 Series datasheet for more information on standard boot strategies and

sequencing.

3.2.8.4

Serial EEPROM with Unique MAC Address

The SAMA5D2-PTC-EK board embeds one Microchip 24AA02E48 I²C serial EEPROM connected on the

TWI1 interface.

The TWI interface is I

2

C-compatible and similarly uses only two lines, namely serial data (SDA) and serial

clock (SCL). According to the standard, the TWI clock rate is limited to 400 kHz in Fast mode and 100

kHz in Normal mode, but configurable baud rate generator permits the output data rate to be adapted to a

wide range of core clock frequencies. The TWI is used in Master mode.

The 24AA02E48 features 2048 bits of Serial Electrically-Erasable Programmable Read-Only Memory

(EEPROM) organized as 256 words of eight bits each and is accessed via an I

2

C-compatible (2-wire)

serial interface. In addition, the 24AA02E48 incorporates an easy and inexpensive method to obtain a

globally unique MAC or EUI address (EUI-48).

The EUI-48 addresses can be assigned as the actual physical address of a system hardware device or

node, or it can be assigned to a software instance. These addresses are factory-programmed by

Microchip and guaranteed unique. They are permanently write-protected in an extended memory block

located outside the standard 2-Kbit memory array.

CAUTION

Caution: The EEPROM device is used as a “software label” to store board information such as

chip type, manufacturer name and production date, using the last two 16-byte blocks in

memory. The information contained in these blocks should not be modified.

SAMA5D2-PTC-EK

Board Components

DS50002709A-page

20

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Microchip Technology SAMA5D2-PTC-EK User manual

Microchip Technology SAMA5D2-PTC-EK User manual

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