Microchip Technology KSZ8061MNX User manual

Brand: Microchip Technology

Model: KSZ8061MNX

Type: User manual

 2016 Microchip Technology Inc. DS50002449A

KSZ8061MNX

Evaluation Board

User’s Guide

 2016 Microchip Technology Inc. DS50002449A-page 2

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights unless otherwise stated.

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2009 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC

MCUs and dsPIC

DSCs, KEELOQ

code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

QUALITY MANAGEMENT S

YSTEM

CERTIFIED BY DNV

== ISO/TS 16949 ==

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,

FlashFlex, flexPWR, JukeBlox, K

EELOQ, KEELOQ logo, Kleer,

LANCheck, MediaLB, MOST, MOST logo, MPLAB,

OptoLyzer, PIC, PICSTART, PIC

logo, RightTouch, SpyNIC,

SST, SST Logo, SuperFlash and UNI/O are registered

trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

The Embedded Control Solutions Company and mTouch are

registered trademarks of Microchip Technology Incorporated

in the U.S.A.

Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo,

CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit

Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet,

KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB

Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,

Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,

PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O,

Total Endurance, TSHARC, USBCheck, VariSense,

ViewSpan, WiperLock, Wireless DNA, and ZENA are

trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

Silicon Storage Technology is a registered trademark of

Microchip Technology Inc. in other countries.

GestIC is a registered trademark of Microchip Technology

Germany II GmbH & Co. KG, a subsidiary of Microchip

Technology Inc., in other countries.

All other trademarks mentioned herein are property of their

respective companies.

ISBN: 978-1-5224-0359-3

 2016 Microchip Technology Inc. DS50002449A-page 3

Object of Declaration: KSZ8061MNX Evaluation Board

DS50002449A-page 4  2016 Microchip Technology Inc.

NOTES:

KSZ8061MNX EVALUATION

BOARD USER’S GUIDE

 2016 Microchip Technology Inc. DS50002449A-page 5

Table of Contents

Preface ...........................................................................................................................7

Introduction............................................................................................................ 7

Document Layout.................................................................................................. 7

Conventions Used in This Guide........................................................................... 8

Recommended Reading........................................................................................9

The Microchip Web Site........................................................................................ 9

Customer Support.................................................................................................9

Revision History .................................................................................................... 9

Chapter 1. Product Overview

1.1 Introduction ...................................................................................................11

Chapter 2. Configuration

2.1 Introduction ...................................................................................................13

2.2 Configuration Options ...................................................................................13

2.3 Configuration Instructions .............................................................................16

2.4 Power ........................................................................................................... 18

2.5 Clocking ........................................................................................................18

2.6 Line Interface Connector Options ................................................................. 19

2.7 MII Connector ...............................................................................................20

2.8 MII Management Interface (MDIO/MDC) .....................................................20

2.9 10-Pin Header (J7) ....................................................................................... 20

2.10 Status Indicator LEDs ................................................................................. 20

2.11 Reset Buttons .............................................................................................21

2.12 Jumpers ...................................................................................................... 21

2.13 KSZ8061MNX Strapping Options ...............................................................22

2.14 MDIO/MDC Software Utility and FTDI Cable .............................................22

Appendix A. Schematic and Layouts

A.1 Introduction ..................................................................................................25

Appendix B. Bill of Materials (BOM)

Worldwide Sales and Service ....................................................................................34

KSZ8061MNX Evaluation Board User’s Guide

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NOTES:

KSZ8061MNX EVALUATION

BOARD USER’S GUIDE

 2016 Microchip Technology Inc. DS50002449A-page 7

Preface

INTRODUCTION

This chapter contains general information that will be useful to know before using the

KSZ8061MNX Evaluation Board. Items discussed in this chapter include:

• Document Layout

• Conventions Used in This Guide

• Recommended Reading

• The Microchip Web Site

• Customer Support

• Revision History

DOCUMENT LAYOUT

This document describes how to use the KSZ8061MNX Evaluation Board as a devel-

opment tool. The document is organized as follows:

• Chapter 1. “Product Overview” – This chapter includes important information

about the KSZ8061MNX Evaluation Board.

• Chapter 2. “Configuration” – This chapter includes a detailed description of

each function of the evaluation board and instructions on how to begin using the

board.

• Appendix A. “Schematic and Layouts” – Refer to this appendix for board

schematics.

• Appendix B. “Bill of Materials (BOM)” – Refer to this appendix to view the bill of

materials.

NOTICE TO CUSTOMERS

All documentation becomes dated, and this manual is no exception. Microchip tools and

documentation are constantly evolving to meet customer needs, so some actual dialogs

and/or tool descriptions may differ from those in this document. Please refer to our web site

(www.microchip.com) to obtain the latest documentation available.

Documents are identified with a “DS” number. This number is located on the bottom of each

page, in front of the page number. The numbering convention for the DS number is

“DSXXXXXXXXA”, where “XXXXXXXX” is the document number and “A” is the revision level

of the document.

For the most up-to-date information on development tools, see the MPLAB

IDE online help.

Select the Help menu, and then Topics to open a list of available online help files.

KSZ8061MNX Evaluation Board User’s Guide

DS50002449A-page 8  2016 Microchip Technology Inc.

CONVENTIONS USED IN THIS GUIDE

This manual uses the following documentation conventions:

DOCUMENTATION CONVENTIONS

Description Represents Examples

Arial font:

Italic characters Referenced books MPLAB

IDE User’s Guide

Emphasized text ...is the only compiler...

Initial caps A window the Output window

A dialog the Settings dialog

A menu selection select Enable Programmer

Quotes A field name in a window or

dialog

“Save project before build”

Underlined, Italic text with

right angle bracket

A menu path File>Save

Bold characters A dialog button Click OK

A tab Click the Power tab

N‘Rnnnn A number in verilog format,

where N is the total number of

digits, R is the radix and n is a

digit.

4‘b0010, 2‘hF1

Text in angle brackets < > A key on the keyboard Press <Enter>, <F1>

Courier New font:

Plain Courier New Sample source code #define START

Filenames autoexec.bat

File paths c:\mcc18\h

Keywords _asm, _endasm, static

Command-line options -Opa+, -Opa-

Bit values 0, 1

Constants 0xFF, ‘A’

Italic Courier New A variable argument file.o, where file can be

any valid filename

Square brackets [ ] Optional arguments mcc18 [options] file

[options]

Curly brackets and pipe

character: { | }

Choice of mutually exclusive

arguments; an OR selection

errorlevel {0|1}

Ellipses... Replaces repeated text var_name [,

var_name...]

Represents code supplied by

user

void main (void)

{ ...

}

Preface

 2016 Microchip Technology Inc. DS50002449A-page 9

RECOMMENDED READING

This user's guide describes how to use KSZ8061MNX Evaluation Board. Other useful

documents are listed below. The following Microchip documents are available and

recommended as supplemental reference resources:

• KSZ8061MNX/KSZ8061MNG Data Sheet

This data sheet provides detailed information regarding the KSZ8061MNX device.

THE MICROCHIP WEB SITE

Microchip provides online support via our web site at www.microchip.com. This web

site is used as a means to make files and information easily available to customers.

Accessible by using your favorite Internet browser, the web site contains the following

information:

• Product Support – Data sheets and errata, application notes and sample

programs, design resources, user’s guides and hardware support documents,

latest software releases and archived software

• General Technical Support – Frequently Asked Questions (FAQs), technical

support requests, online discussion groups, Microchip consultant program

member listing

• Business of Microchip – Product selector and ordering guides, latest Microchip

press releases, listing of seminars and events, listings of Microchip sales offices,

distributors and factory representatives

CUSTOMER SUPPORT

Users of Microchip products can receive assistance through several channels:

• Distributor or Representative

• Local Sales Office

• Field Application Engineer (FAE)

• Technical Support

Customers should contact their distributor, representative or field application engineer

(FAE) for support. Local sales offices are also available to help customers. A listing of

sales offices and locations is included in the back of this document.

Technical support is available through the web site at:

http://www.microchip.com/support.

REVISION HISTORY

Revision A (March 2016)

• Original Microchip release of this document. This document replaces Micrel docu-

ment “KSZ8061MNX Evaluation Board User's Guide” version 1.1 (March 2015).

KSZ8061MNX Evaluation Board User’s Guide

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NOTES:

KSZ8061MNX EVALUATION

BOARD USER’S GUIDE

 2016 Microchip Technology Inc. DS50002449A-page 11

Chapter 1. Product Overview

1.1 INTRODUCTION

The KSZ8061MNX Evaluation Board is designed to enable functional and performance

testing of the KSZ8061MNX PHY. In addition to the KSZ8061 PHY, there is a second

PHY–a KSZ8081. The KSZ8081 is a standard 10/100 Ethernet PHY. It is used here to

provide a second line interface for simple full-duplex traffic through the KSZ8061. This

board is not intended for evaluation of the KSZ8081. A block diagram of the board is

shown in Figure 1-1. Figure 1-2 highlights the board components.

FIGURE 1-1: KSZ8061MNX EVALUATION BOARD BLOCK DIAGRAM

KSZ8061

Second PHY

(KSZ8081)

RJ-45

Line

Connector

(3 options)

MII Connector

10-Pin

Management

Header (J7)

R1-6

R21-26 R11-16

R221-226R211-216

DC Power

Connector

MII

Interrupt

Reset

MDIO/MDC

Signal Detect

Magnetics

KSZ8061 3.3V Reg

Select

KSZ8081 3.3V Reg

KSZ8061 Low V Reg

RXER Latch,

LED, Reset

Reset

25 MHz

Xtal

Clocking Options

KSZ8061MNX Evaluation Board User’s Guide

DS50002449A-page 12  2016 Microchip Technology Inc.

FIGURE 1-2: KSZ8061MNX EVALUATION BOARD COMPONENTS

KSZ8061MNX EVALUATION

BOARD USER’S GUIDE

 2016 Microchip Technology Inc. DS50002449A-page 13

Chapter 2. Configuration

2.1 INTRODUCTION

This chapter discusses the configuration of the KSZ8061MNX Evaluation Board.

Items discussed in this chapter include:

• Configuration Options

• Configuration Instructions

• Power

• Clocking

• Line Interface Connector Options

• MII Connector

• MII Management Interface (MDIO/MDC)

• 10-Pin Header (J7)

• Status Indicator LEDs

• Reset Buttons

• Jumpers

• KSZ8061MNX Strapping Options

• MDIO/MDC Software Utility and FTDI Cable

2.2 CONFIGURATION OPTIONS

The KSZ8061 line interface is designed to permit the installation of any one of three

different connectors. These are described further in a later section.

The KSZ8061 MII data path can be configured in three different ways. Below are

descriptions and photographs of the configuration options.

1. Two-PHY MII Back-to-Back

The evaluation board has two PHYs: a KSZ8061 (U1) and a KSZ8081 (U2). The

KSZ8081 is an ordinary 10/100 Ethernet PHY, and is on this board to support the

KSZ8061. Their MII buses can be connected together, which allows Ethernet

frames to be passed between the KSZ8061 line interface (J1, J2 or J3) and the

KSZ8081 line interface (J6). Unless otherwise indicated, this is the default board

configuration.

2. MII Loopback

In this configuration, the KSZ8061 receives Ethernet traffic from the line inter-

face. At the MII interface, RX traffic is looped back the TX MII interface, and the

KSZ8061 transmits it back to the line interface. The KSZ8081 PHY is not used.

Do not reference Figure 2-2 for resistor settings.

3. MII Connector

The MII edge connector (J5) allows the KSZ8061MNX Evaluation Board to be

connected to the MAC port of a Microchip switch evaluation board, or to any

other device with an Ethernet MAC interface. Full duplex traffic can pass

between the MII connector and the KSZ8061 line interface (J1, J2 or J3). The

KSZ8081 PHY is not used.

KSZ8061MNX Evaluation Board User’s Guide

DS50002449A-page 14  2016 Microchip Technology Inc.

FIGURE 2-1: KSZ8061MNX EVALUATION BOARD IN TWO-PHY MII BACK-TO-BACK MODE

Configuration

 2016 Microchip Technology Inc. DS50002449A-page 15

FIGURE 2-2: KSZ8061MNX EVALUATION BOARD IN MII LOOPBACK MODE WITH

USB-TO-MDIO/MDC CABLE ON J7

FIGURE 2-3: KSZ8061MNX EVALUATION BOARD IN MII CONNECTOR MODE, WITH

ETHERNET SWITCH

KSZ8061MNX Evaluation Board User’s Guide

DS50002449A-page 16  2016 Microchip Technology Inc.

2.3 CONFIGURATION INSTRUCTIONS

These instructions detail how to change between configurations. Figure 2-4 and

Figure 2-5 show the location of the components referenced in the instructions.

1. Two-PHY MII Back-to-Back Configuration. This is the default configuration, so

these steps are only necessary if switching the board back from another

configuration.

a) Place the KSZ8061 in MII Back-to-Back mode: install R40 and R41. Remove

R39.

b) Connect the MII interfaces of the KSZ8061 and KSZ8081: install R212-R216

and R222-226. Note that the MII clocks should not be connected between

the two devices, so do not install R211 and R221.

c) Both PHYs must be clocked from U3. Do not use crystal Y1, by removing

either Y1 or R91 and R92.

d) Remove R1-R6.

e) Power the KSZ8081: install jumper JP1.

f) Optionally, for optimal signal integrity, remove R11-R16 and R21-R26.

2. MII Loopback Configuration

a) Place the KSZ8061 in MII Back-to-Back mode: install R40 and R41. Remove

R39.

b) Install R1-R6.

c) Remove the KSZ8081 from the MII bus. There are three possible ways to do

this:

- Remove jumper JP1 to remove power from the KSZ8081.

- Remove R211-R216 and R221-R226.

- Put the KSZ8081 in Isolate mode: install R70.

d) The KSZ061 may be clocked by either the external clock (U3) or the crystal

(Y1). When changing between clock sources, the KSZ8061 does not require

any setting changes.

e) Optionally, for optimal signal integrity, remove R11-R16 and R21-R26.

3. MII Connector Configuration

a) Place the KSZ8061 in Normal mode: remove R39 and R41. Install R40 if

Auto-MDI/MDI-X is desired. Otherwise, remove R40.

b) Install R11-R16 and R21-R26.

c) Remove R1-R6.

d) Remove the KSZ8081 from the MII bus. There are three possible ways to do

this:

- Remove jumper JP1 to remove power from the KSZ8081.

- Remove R211-R216 and R221-R226

- Put the KSZ8081 in Isolate mode: install R70.

e) The KSZ061 may be clocked by either the external clock (U3) or the crystal

(Y1). When changing between clock sources, the KSZ8061 does not require

any setting changes.

f) Connect the KSZ8061 evaluation board to a compatible connector on a

Microchip switch evaluation board, and ensure that the port on the switch

board is configured for MAC interface.

Configuration

 2016 Microchip Technology Inc. DS50002449A-page 17

FIGURE 2-4: TOP SIDE COMPONENTS FOR CONFIGURTION CHANGES

FIGURE 2-5: BOTTOM SIDE COMPONENTS FOR CONFIGURATION

CHANGES

KSZ8061MNX Evaluation Board User’s Guide

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2.4 POWER

The evaluation board requires a DC supply at barrel connector J8. A jumper must be

installed on pins 2-3 of JP3. The voltage requirement is 4.5V to 14V. The current

requirement is 200 mA.

An alternate power connection is available at the 10-pin management header J7. This

is intended to allow the board to be powered from a USB cable such as the FTDI

C232HM-EDHSL-0. When supplying power via header J7, a jumper must be installed

on pins 1-2 of JP3 (labeled “5V_HDR”).

A noise filtering choke is provided on the J8 connector, but not on the J7 power pins.

Therefore, J8 is the preferred power connector when testing KSZ8061 performance.

2.5 CLOCKING

The KSZ8061 utilizes a 25 MHz reference clock. There are two options for supplying

this clock: crystal or external clock. If the second PHY (KSZ8081, U2) is used, then the

two PHYs must be synchronized and the only clocking option is to clock both PHYs

from the same external clock source.

1. External clock (default configuration). The external clock source is a Microchip

PL135-27 (U3), which drives the same 25 MHz clock to both PHYs. When using

this clock source, the KSZ8061 crystal (Y1) must not be connected from the

KSZ8061. This is done either by removing R91 and R92, or by removing Y1, refer

to Figure 2-6.

FIGURE 2-6: EXTERNAL CLOCK OPTION

2. Crystal. Crystal Y1 can be connected directly to the KSZ8061, which has an

on-chip oscillator. Install resistors R91 and R92, and remove resistor R62. To

fully turn off the external clock (U3), remove R63. This mode can be used only

when the KSZ8061 and KSZ8081 are not used in back-to-back configuration.

KSZ8061MNX (U1)

R91 / DNI

R92 / DNI

R62 / 0ȍ

PL135-27 (U3)

CLK1

KSZ8081MNX (U2)

CLK0

Configuration

 2016 Microchip Technology Inc. DS50002449A-page 19

FIGURE 2-7: CRYSTAL CLOCKING OPTION

2.6 LINE INTERFACE CONNECTOR OPTIONS

The KSZ8081 has a conventional RJ-45 UTP Ethernet connector, but there are three

connector options for the KSZ8061:

1. J1: Ethernet RJ-45

2. J2: TE MQS-4, part number 1379165-1 (Mating receptacle is 1379029-1)

3. J3: Sumitomo TS series 16-pin, part number 6098-6793 (Mating receptacle is

6098-4008)

Table 2- 1 lists the signal connections for each connector. Also refer to the schematic or

PCB layout file since connector pin numbering may not be standardized.

CAUTION

The silkscreen labels on the bottom of the board for R62, R91 and R92 are incorrect.

The middle resistor is R62. R91 is closer to C9, and R92 is closer to C10. The image

below shows the correct locations of R62, R91, and R92.

KSZ8061MNX (U1)

R91 / 0ȍ

R92 / 0ȍ

R62

DNI

PL135-27 (U3)

VDD

3.3V

R63 optional

KSZ8061MNX Evaluation Board User’s Guide

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TABLE 2-1: KSZ8061 CONNECTOR PIN ASSIGNMENTS

2.7 MII CONNECTOR

The MII edge connector J5 provides external access to the KSZ8061 MII bus and the

MII management interface (MDIO/MDC). This connector is typically used to connect

the KSZ8061 PHY to the MAC interface on a Microchip Ethernet switch evaluation

board. Test traffic can then be sent and received through another port on the switch.

This configuration is shown in Figure 2-3. Note that 5V power is not shared across this

connector, so each board must be powered separately.

To use this interface, it is necessary to have 0-ohm resistors R11-R16 and R21-R26

installed. The KSZ8081 also needs to be isolated from the MII bus. The simplest way

to do this is to remove power from the KSZ8081 by removing jumper JP1. Alternatively,

place the KSZ8081 into Isolate mode by installing R70, or remove resistors R211-R216

and R221-R226.

2.8 MII MANAGEMENT INTERFACE (MDIO/MDC)

The MII management interface (MDIO/MDC) can be accessed in two ways. The first is

via the MII connector J5, discussed above. This requires the installation of resistors

R31 and R33. Alternatively, these signals are accessible at the 10-pin header J7,

requiring the installation of resistors R27 and R28. These resistor options are provided

for signal integrity optimization. If signal integrity on this interface is not a problem, then

it is acceptable to leave all four resistors installed.

The default MII management addresses (a.k.a. PHY addresses) are b'001 for the

KSZ8061, and b'011 for the KSZ8081.

2.9 10-PIN HEADER (J7)

Header J7 is intended primarily for access to the MII management interface (MDIO and

MDC signals). The header pins are labeled with color codes for connection to the FTDI

C232HM-DDHSL-0 or C232HM-EDHSL-0 USB-to-MPSSE cable. The two pins labeled

“MDIO” are the same board signal. They are duplicated because the FTDI cable sep-

arates the serial data input and output signals.

As described in Section 2.4 “Power”, it is possible to power the board through header

J7 instead of the standard power connector J8. The C232HM-EDHSL-0 cable has 5V

available for this purpose. Note that the board cannot be powered from the

C232HM-DDHSL-0 cable which is 3.3V. See Section 2.4 “Power” for more details.

This header also provides access to the KSZ8061 reset input signal, and the interrupt

and signal detect output signals. The reset signal goes only to the KSZ8061, and not

to the KSZ8081 nor to the RXER latch and LED.

KSZ8061 Signal

Connector Pin Assignment

RJ-45 TE 1379165-1

Sumitomo

6098-6793

TXP1410

TXM239

RXP327

RXM616

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Microchip Technology KSZ8061MNX User manual

Microchip Technology KSZ8061MNX User manual

Microchip Technology KSZ8061MNX User manual

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