Silicon Labs EFR32xG21 Wireless Gecko Reference guide

EFR32xG21 Wireless Gecko

Reference Manual

The EFR32xG21 Wireless Gecko SoC is the first device in the Series 2 Wireless Gecko

Portfolio, and includes the EFR32MG21 Mighty Gecko and EFR32BG21 Blue Gecko.

The EFR32xG21 improves processing capability with a Cortex M33 core and has best in

class link budget while providing for lower active current for both the MCU and radio. The

dedicated security core (

Secure Element) provides improved cryptography and hardware

security that is isolated from the main application CPU. This high performance and se-

cure multi-protocol device supports Zigbee, Thread, and Bluetooth 5.0.

The single-die solution provides industry-leading energy efficiency, processing capability,

and RF performance in a small form factor for IoT connected applications.

KEY FEATURES

• 32-bit ARM® Cortex M33 core with 80

MHz maximum operating frequency

•

Scalable Memory and Radio configuration

options available in QFN packaging

• Peripheral Reflex System enabling

autonomous interaction of MCU

peripherals

• Autonomous Hardware Crypto Accelerator

and True Random Number Generator

• Multiple Integrated 2.4 GHz PAs with up to

20 dBm transmit power

Security

Secure Debug

Authentication

Timers and Triggers

32-bit bus

Peripheral Reflex System

Serial

Interfaces

I/O Ports Analog I/F

Lowest power mode with peripheral operational:

USART

I

2

C

External

Interrupts

General

Purpose I/O

Pin Reset

Pin Wakeup

IADC

Analog

Comparator

EM4—Shutoff

Energy

Management

Brown-Out

Detector

Voltage

Regulator

Power-On Reset

Clock Management

HF Crystal

Oscillator

LF Crystal

Oscillator

LF

RC Oscillator

HF

RC Oscillator

EM23 HF RC

Oscillator

Crypto Acceleration

Secure Element

Ultra LF RC

Oscillator

Core / Memory

ARM Cortex

TM

M33 processor

with DSP extensions,

FPU and TrustZone

ETM Secure Debug RAM Memory

LDMA

Controller

Flash Program

Memory

Real Time

Capture Counter

Timer/Counter

Low Energy Timer

Watchdog Timer

Protocol Timer

EM3—StopEM2—Deep SleepEM1—SleepEM0—Active

True Random

Number Generator

Fast Startup

RC Oscillator

Back-Up Real

Time Counter

Radio Transceiver

DEMOD

AGC

IFADC

CRC

BUFC

MOD

FRC

RAC

Frequency

Synth

PGA

RF Frontend

I

Q

PA

LNA

PA

EUI

Secure Boot with

Root of Trust and

Secure Loader

DPA

Countermeasures

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Table of Contents

1.

About This Document ...........................22

1.1 Introduction ...............................22

1.2 Conventions ...............................23

1.3 Related Documentation ...........................24

2. System Overview .............................25

2.1 Introduction ...............................26

2.2 Block Diagrams..............................27

2.3 MCU Features overview ...........................28

2.4 Security Features .............................29

2.4.1 Secure Boot with Root of Trust and Secure Loader (RTSL) .............29

2.4.2 Cryptographic Accelerator.........................30

2.4.3 True Random Number Generator ......................30

2.4.4 Secure Debug with Lock/Unlock.......................30

2.5 Oscillators and Clocks ...........................31

2.6 RF Frequency Synthesizer ..........................31

2.7 Modulation Modes .............................31

2.8 Transmit Mode ..............................32

2.9 Receive Mode ..............................32

2.10 Data Buffering ..............................32

2.11 Unbuffered Data Transfer ..........................32

2.12 Frame Format Support ...........................32

2.13 Hardware CRC Support ..........................33

2.14 Convolutional Encoding / Decoding ......................33

2.15 Binary Block Encoding / Decoding .......................33

2.16 Timers ................................34

2.17 RF Test Modes .............................34

3. System Processor ............................35

3.1 Introduction ...............................35

3.2 Features ................................36

3.3 Functional Description ...........................36

3.3.1 Interrupt Operation ...........................37

3.3.2 TrustZone ..............................37

3.3.3 Interrupt Request lines (IRQ) ........................38

4. Memory and Bus System ..........................40

4.1 Introduction ...............................40

4.2 Functional Description ...........................41

4.2.1 Bus Matrix ..............................42

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4.2.2 Flash ................................43

4.2.3 SRAM ...............................43

4.2.4 Peripherals ..............................43

5. Radio Transceiver ............................49

5.1 Introduction ...............................50

6. MSC - Memory System Controller ......................51

6.1 Introduction ...............................51

6.2 Features ................................52

6.3 Functional Description ...........................52

6.3.1 Ram Configuration ...........................52

6.3.2 Instruction Cache............................53

6.3.3 Device Information (DI) Page .......................53

6.3.4 User Data (UD) Page Description ......................53

6.3.5 Bootloader ..............................53

6.3.6 Post-reset Behavior ...........................53

6.3.7 Flash Startup .............................53

6.3.8 Wait-states ..............................54

6.3.9 Cortex-M33 If-Then Block Folding ......................54

6.3.10 Line Buffering (Prefetch) .........................54

6.3.11 Erase and Write Operations........................55

6.4 DEVINFO - Device Info Page .........................56

6.4.1 Register Map .............................57

6.4.2 Register Description...........................58

6.5 ICACHE - Instruction Cache .........................85

6.5.1 Cache Operation ............................85

6.5.2 Performance Measurement ........................86

6.5.3 Register Map .............................87

6.5.4 Register Description...........................88

6.6 SYSCFG - System Configuration ........................94

6.6.1 Ram Retention ............................94

6.6.2 ECC ................................95

6.6.3 RAM Wait-states ............................95

6.6.4 RAM Prefetch .............................95

6.6.5 RAM Cache .............................95

6.6.6 Software Interrupts ...........................95

6.6.7 Bus faults ..............................95

6.6.8 Register Map .............................96

6.6.9 Register Description...........................99

6.7 Register Map .............................111

6.8 Register Description ...........................113

6.8.1 MSC_IPVERSION - IP version ID .....................113

6.8.2 MSC_READCTRL - Read Control Register ..................114

6.8.3 MSC_WRITECTRL - Write Control Register..................115

6.8.4 MSC_WRITECMD - Write Command Register .................116

6.8.5 MSC_ADDRB - Page Erase/Write Address Buffer ................117

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6.8.6 MSC_WDATA - Write Data Register ....................117

6.8.7 MSC_STATUS - Status Register .....................118

6.8.8 MSC_IF - Interrupt Flag Register .....................119

6.8.9 MSC_IEN - Interrupt Enable Register ....................120

6.8.10 MSC_USERDATASIZE - user data regsion size ................120

6.8.11 MSC_CMD - Command Register .....................121

6.8.12 MSC_LOCK - Configuration Lock Register ..................121

6.8.13 MSC_MISCLOCKWORD - Mass erase and User data page lock word ........122

6.8.14 MSC_PAGELOCK0 - Main space page 0-31 lock word .............122

6.8.15 MSC_PAGELOCK1 - Main space page 32-63 lock word .............123

6.8.16 MSC_PAGELOCK2 - Main space page 64-95 lock word .............123

6.8.17 MSC_PAGELOCK3 - Main space page 96-127 lock word.............124

6.8.18

MSC_TESTCTRL - Flash test control register.................124

7. DBG - Debug Interface ...........................125

7.1 Introduction ..............................125

7.2 Features ...............................125

7.3 Functional Description ..........................126

7.3.1 Debug Pins.............................126

7.3.2 Embedded Trace Macrocell V3.5 (ETM) ...................126

7.3.3 Debug and EM2/EM3 .........................126

7.4 Register Map .............................127

7.5 Register Description ...........................127

7.5.1 DBG_DCIWDATA - Write Data ......................127

7.5.2 DBG_DCIRDATA - Read Data ......................127

7.5.3 DBG_DCISTATUS - Status .......................128

7.5.4 DBG_DCIID - Identification .......................128

7.5.5 DBG_SYSCOM0 - Communication Status ..................129

7.5.6 DBG_SYSCOM1 - Communication Status ..................130

7.5.7 DBG_SYSPWR0 - Power Status .....................131

7.5.8 DBG_SYSCLK0 - Clocking Status .....................133

7.5.9 DBG_SYSID - Identification .......................135

8. CMU - Clock Management Unit ........................136

8.1 Introduction ..............................136

8.2 Features ...............................136

8.3 Functional Description ..........................137

8.3.1 System Clocks ...........................139

8.3.2 Switching Clock Source ........................141

8.3.3 RC Oscillator Calibration ........................143

8.3.4 Energy Modes ...........................146

8.3.5 Clock Output on a Pin .........................146

8.3.6 Clock Input from a Pin .........................147

8.3.7 Clock Output on PRS .........................147

8.3.8 Interrupts .............................147

8.3.9 Protection .............................147

8.4 Register Map .............................148

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8.5 Register Description ...........................150

8.5.1 CMU_IPVERSION - IP version ID .....................150

8.5.2 CMU_STATUS - Status Register .....................151

8.5.3 CMU_LOCK - Configuration Lock Register ..................152

8.5.4 CMU_WDOGLOCK - WDOG Configuration Lock Register .............152

8.5.5 CMU_IF - Interrupt Flag Register .....................153

8.5.6 CMU_IEN - Interrupt Enable Register ....................153

8.5.7

CMU_CALCMD - Calibration Command Register ................154

8.5.8 CMU_CALCTRL - Calibration Control Register .................155

8.5.9 CMU_CALCNT - Calibration Result Counter Register ..............156

8.5.10 CMU_SYSCLKCTRL - System Clock Control .................157

8.5.11 CMU_TRACECLKCTRL - Debug Trace Clock Control ..............158

8.5.12 CMU_EXPORTCLKCTRL - Export Clock Control ...............159

8.5.13 CMU_DPLLREFCLKCTRL - Digital PLL Reference Clock Control ..........161

8.5.14 CMU_EM01GRPACLKCTRL - EM01 Peripheral Group A Clock Control ........162

8.5.15 CMU_EM23GRPACLKCTRL - EM23 Peripheral Group A Clock Control ........162

8.5.16 CMU_EM4GRPACLKCTRL - EM4 Peripheral Group A Clock Control .........163

8.5.17 CMU_IADCCLKCTRL - IADC Clock Control .................163

8.5.18 CMU_WDOG0CLKCTRL - Watchdog0 Clock Control ..............164

8.5.19 CMU_WDOG1CLKCTRL - Watchdog1 Clock Control ..............165

8.5.20 CMU_RTCCCLKCTRL - RTCC Clock Control.................165

8.5.21 CMU_RADIOCLKCTRL - Radio Clock Control ................166

9. Oscillators ...............................167

9.1 Introduction ..............................167

9.2 HFXO - High Frequency Crystal Oscillator ....................167

9.2.1 Introduction ............................167

9.2.2 Features .............................167

9.2.3 Functional Description .........................168

9.2.4 Register Map ............................171

9.2.5 Register Description ..........................172

9.3 HFRCO - High-Frequency RC Oscillator ....................182

9.3.1 Introduction ............................182

9.3.2 Features .............................182

9.3.3 Functional Description .........................182

9.3.4 Register Map ............................185

9.3.5 Register Description ..........................186

9.4 DPLL - Digital Phased Locked Loop ......................190

9.4.1 Introduction ............................190

9.4.2 Features .............................190

9.4.3 Functional Description .........................190

9.4.4 Register Map ............................192

9.4.5 Register Description ..........................193

9.5 LFXO - Low-Frequency Crystal Oscillator ....................198

9.5.1 Introduction ............................198

9.5.2 Features .............................198

9.5.3 Functional Description .........................198

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9.5.4 Register Map ............................200

9.5.5 Register Description ..........................201

9.6

LFRCO - Low-Frequency RC Oscillator ....................208

9.6.1 Introduction ............................208

9.6.2 Features .............................208

9.6.3 Functional Description .........................208

9.6.4 Register Map ............................210

9.6.5 Register Description ..........................211

9.7 FSRCO - Fast Start RCO .........................214

9.7.1 Introduction ............................214

9.7.2 Features .............................214

9.7.3 Functional Description .........................214

9.7.4 Register Map ............................214

9.7.5 Register Description ..........................215

9.8 ULFRCO - Ultra Low Frequency RC Oscillator ..................215

9.8.1 Introduction ............................215

9.8.2 Features .............................215

9.8.3 Functional Description .........................215

10. SMU - Security Management Unit ......................216

10.1 Introduction .............................216

10.2 Features ..............................216

10.3 Functional Description ..........................217

10.3.1 Bus Level Security ..........................217

10.3.2 Privileged Access Control .......................218

10.3.3 Secure Access Control ........................218

10.3.4 ARM TrustZone ...........................219

10.3.5 Configuring Masters .........................219

10.3.6 Configuring Peripherals ........................219

10.3.7 Configuring Memory .........................220

10.3.8 Cortex-M33 Integration ........................220

10.3.9 Exception Handling .........................221

10.3.10 SMU Lock ............................221

10.4 Register Map .............................222

10.5 Register Description ...........................224

10.5.1 SMU_IPVERSION - IP Version .....................224

10.5.2 SMU_STATUS - Status Register .....................225

10.5.3 SMU_LOCK - Lock Register ......................225

10.5.4 SMU_IF - Interrupt Flag Register .....................226

10.5.5 SMU_IEN - Interrupt Enable Register ...................227

10.5.6 SMU_M33CTRL - M33 Control Settings ..................228

10.5.7 SMU_PPUPATD0 - Privileged Access ...................229

10.5.8 SMU_PPUPATD1 - Privileged Access ...................231

10.5.9 SMU_PPUSATD0 - Secure Access ....................233

10.5.10 SMU_PPUSATD1 - Secure Access ....................235

10.5.11 SMU_PPUFS - Fault Status ......................236

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10.5.12 SMU_BMPUPATD0 - Privileged Attribute ..................237

10.5.13 SMU_BMPUSATD0 - Secure Attribute...................238

10.5.14

SMU_BMPUFS - Fault Status .....................239

10.5.15 SMU_BMPUFSADDR - Fault Status Address ................239

10.5.16 SMU_ESAURTYPES0 - Region Types 0 ..................240

10.5.17 SMU_ESAURTYPES1 - Region Types 1 ..................240

10.5.18 SMU_ESAUMRB01 - Movable Region Boundary ...............241

10.5.19 SMU_ESAUMRB12 - Movable Region Boundary ...............241

10.5.20 SMU_ESAUMRB45 - Movable Region Boundary ...............242

10.5.21 SMU_ESAUMRB56 - Movable Region Boundary ...............242

11. SE - Secure Element Subsystem ......................243

11.1 Introduction .............................243

11.2 Security Features ...........................243

11.2.1 Security Features Overview .......................243

11.2.2 Secure Boot with Root of Trust and Secure Loader (RTSL) ............244

11.2.3 Secure Debug ...........................244

11.2.4 Cryptographic Accelerator .......................244

11.2.5 True Random Number Generation ....................244

11.3 SE Mailbox .............................244

11.3.1 Sending Commands .........................245

11.3.2 Receiving Responses ........................245

11.3.3 Register Map ...........................245

11.3.4 Register Description .........................246

12. EMU - Energy Management Unit ......................252

12.1 Introduction..............................252

12.2 Features ..............................253

12.3 Functional Description ..........................254

12.3.1 Energy Modes ...........................255

12.3.2 Entering Low Energy Modes ......................259

12.3.3 Exiting a Low Energy Mode ......................260

12.3.4 Power Domains ...........................261

12.3.5 Brown Out Detector (BOD) .......................261

12.3.6 Reset Management Unit ........................262

12.3.7 Temperature Sensor .........................264

12.3.8 Register Resets ...........................264

12.3.9 Register Locks ...........................264

12.4 Register Map .............................265

12.5 Register Description ...........................267

12.5.1 EMU_DECBOD - DECOUPLE LVBOD Control register .............267

12.5.2 EMU_BOD3SENSE - BOD3SENSE Control register ..............268

12.5.3 EMU_LOCK - EMU Configuration lock register ................268

12.5.4 EMU_IF - Interrupt Flags ........................269

12.5.5 EMU_IEN - Interrupt Enables ......................270

12.5.6 EMU_EM4CTRL - EM4 Control .....................271

12.5.7 EMU_CMD - EMU Command register ...................272

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12.5.8 EMU_CTRL - EMU Control register ....................273

12.5.9 EMU_TEMPLIMITS - EMU Temperature thresholds ..............274

12.5.10 EMU_STATUS - EMU Status register ...................275

12.5.11 EMU_TEMP - Temperature ......................276

12.5.12 EMU_RSTCTRL - Reset Management Control register .............277

12.5.13 EMU_RSTCAUSE - Reset cause ....................279

12.5.14 EMU_DGIF - Interrupt Flags Debug ...................280

12.5.15 EMU_DGIEN - Interrupt Enables Debug ..................281

12.5.16 EMU_SEIF - Interrupt Flags Secure Element ................282

12.5.17 EMU_SEIEN - Interrupt Enables Secure Elements ..............282

13. PRS - Peripheral Reflex System .......................283

13.1 Introduction..............................283

13.2 Features ..............................283

13.3 Functional Description ..........................284

13.3.1 Asynchronous Channel Functions.....................284

13.3.2 Configurable Logic ..........................285

13.3.3 Producers .............................286

13.3.4 Consumers ............................291

13.4 Register Map .............................292

13.5 Register Description ...........................305

13.5.1 PRS_IPVERSION - IP version ID .....................305

13.5.2

PRS_ASYNC_SWPULSE - Software Pulse Register ..............306

13.5.3 PRS_ASYNC_SWLEVEL - Software Level Register ..............307

13.5.4 PRS_ASYNC_PEEK - Async Channel Values ................308

13.5.5 PRS_SYNC_PEEK - Sync Channel Values .................309

13.5.6 PRS_ASYNC_CHx_CTRL - Async Channel Control Register ...........310

13.5.7 PRS_SYNC_CHx_CTRL - Sync Channel Control Register ............311

13.5.8 PRS_CONSUMER_CMU_CALDN - CMU CALDN Consumer Selection ........312

13.5.9 PRS_CONSUMER_CMU_CALUP - CMU CALUP Consumer Selection ........312

13.5.10 PRS_CONSUMER_IADC0_SCANTRIGGER - IADC0 SCANTRIGGER Consumer Selection 313

13.5.11 PRS_CONSUMER_IADC0_SINGLETRIGGER - IADC0 SINGLETRIGGER Consumer

Selection .............................313

13.5.12 PRS_CONSUMER_LDMAXBAR_DMAREQ0 - DMAREQ0 Consumer Selection ....314

13.5.13 PRS_CONSUMER_LDMAXBAR_DMAREQ1 - DMAREQ1 Consumer Selection ....314

13.5.14 PRS_CONSUMER_LETIMER0_CLEAR - LETIMER CLEAR Consumer Selection ....315

13.5.15 PRS_CONSUMER_LETIMER0_START - LETIMER START Consumer Selection ....315

13.5.16 PRS_CONSUMER_LETIMER0_STOP - LETIMER STOP Consumer Selection .....316

13.5.17 PRS_CONSUMER_MODEM_DIN - MODEM DIN Consumer Selection........316

13.5.18 PRS_CONSUMER_RAC_CLR - RAC CLR Consumer Selection ..........317

13.5.19 PRS_CONSUMER_RAC_FORCETX - RAC FORCETX Consumer Selection .....317

13.5.20 PRS_CONSUMER_RAC_RXDIS - RAC RXDIS Consumer Selection ........318

13.5.21 PRS_CONSUMER_RAC_RXEN - RAC RXEN Consumer Selection .........318

13.5.22 PRS_CONSUMER_RAC_SEQ - RAC SEQ Consumer Selection ..........319

13.5.23 PRS_CONSUMER_RAC_TXEN - RAC TXEN Consumer Selection .........319

13.5.24 PRS_CONSUMER_RTCC_CC0 - RTCC CC0 Consumer Selection .........320

13.5.25 PRS_CONSUMER_RTCC_CC1 - RTCC CC1 Consumer Selection .........320

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13.5.26 PRS_CONSUMER_RTCC_CC2 - RTCC CC2 Consumer Selection .........321

13.5.27 PRS_CONSUMER_SE_TAMPERSRC0 - SE TAMPERSRC0 Consumer Selection ...321

13.5.28 PRS_CONSUMER_SE_TAMPERSRC1 - SE TAMPERSRC1 Consumer Selection ...322

13.5.29 PRS_CONSUMER_SE_TAMPERSRC2 - SE TAMPERSRC2 Consumer Selection ...322

13.5.30 PRS_CONSUMER_SE_TAMPERSRC3 - SE TAMPERSRC3 Consumer Selection ...323

13.5.31 PRS_CONSUMER_SE_TAMPERSRC4 - SE TAMPERSRC4 Consumer Selection ...323

13.5.32 PRS_CONSUMER_SE_TAMPERSRC5 - SE TAMPERSRC5 Consumer Selection ...324

13.5.33 PRS_CONSUMER_SE_TAMPERSRC6 - SE TAMPERSRC6 Consumer Selection ...324

13.5.34 PRS_CONSUMER_SE_TAMPERSRC7 - SE TAMPERSRC7 Consumer Selection ...325

13.5.35 PRS_CONSUMER_CORE_CTIIN0 - CTI0 Consumer Selection ..........325

13.5.36 PRS_CONSUMER_CORE_CTIIN1 - CTI1 Consumer Selection ..........326

13.5.37 PRS_CONSUMER_CORE_CTIIN2 - CTI2 Consumer Selection ..........326

13.5.38 PRS_CONSUMER_CORE_CTIIN3 - CTI3 Consumer Selection ..........327

13.5.39 PRS_CONSUMER_CORE_M33RXEV - M33 Consumer Selection .........327

13.5.40 PRS_CONSUMER_TIMER0_CC0 - TIMER0 CC0 Consumer Selection .......328

13.5.41 PRS_CONSUMER_TIMER0_CC1 - TIMER0 CC1 Consumer Selection .......328

13.5.42 PRS_CONSUMER_TIMER0_CC2 - TIMER0 CC2 Consumer Selection .......329

13.5.43 PRS_CONSUMER_TIMER0_DTI - TIMER0 DTI Consumer Selection ........329

13.5.44 PRS_CONSUMER_TIMER0_DTIFS1 - TIMER0 DTIFS1 Consumer Selection .....330

13.5.45 PRS_CONSUMER_TIMER0_DTIFS2 - TIMER0 DTIFS2 Consumer Selection .....330

13.5.46 PRS_CONSUMER_TIMER1_CC0 - TIMER1 CC0 Consumer Selection .......331

13.5.47 PRS_CONSUMER_TIMER1_CC1 - TIMER1 CC1 Consumer Selection .......331

13.5.48 PRS_CONSUMER_TIMER1_CC2 - TIMER1 CC2 Consumer Selection .......332

13.5.49 PRS_CONSUMER_TIMER1_DTI - TIMER1 DTI Consumer Selection ........332

13.5.50 PRS_CONSUMER_TIMER1_DTIFS1 - TIMER1 DTIFS1 Consumer Selection .....333

13.5.51 PRS_CONSUMER_TIMER1_DTIFS2 - TIMER1 DTIFS2 Consumer Selection .....333

13.5.52 PRS_CONSUMER_TIMER2_CC0 - TIMER2 CC0 Consumer Selection .......334

13.5.53 PRS_CONSUMER_TIMER2_CC1 - TIMER2 CC1 Consumer Selection .......334

13.5.54 PRS_CONSUMER_TIMER2_CC2 - TIMER2 CC2 Consumer Selection .......335

13.5.55 PRS_CONSUMER_TIMER2_DTI - TIMER2 DTI Consumer Selection ........335

13.5.56 PRS_CONSUMER_TIMER2_DTIFS1 - TIMER2 DTIFS1 Consumer Selection .....336

13.5.57 PRS_CONSUMER_TIMER2_DTIFS2 - TIMER2 DTIFS2 Consumer Selection .....336

13.5.58 PRS_CONSUMER_TIMER3_CC0 - TIMER3 CC0 Consumer Selection .......337

13.5.59 PRS_CONSUMER_TIMER3_CC1 - TIMER3 CC1 Consumer Selection .......337

13.5.60 PRS_CONSUMER_TIMER3_CC2 - TIMER3 CC2 Consumer Selection .......338

13.5.61 PRS_CONSUMER_TIMER3_DTI - TIMER3 DTI Consumer Selection ........338

13.5.62 PRS_CONSUMER_TIMER3_DTIFS1 - TIMER3 DTIFS1 Consumer Selection .....339

13.5.63 PRS_CONSUMER_TIMER3_DTIFS2 - TIMER3 DTIFS2 Consumer Selection .....339

13.5.64 PRS_CONSUMER_USART0_CLK - USART0 CLK Consumer Selection .......340

13.5.65 PRS_CONSUMER_USART0_IR - USART0 IR Consumer Selection ........340

13.5.66 PRS_CONSUMER_USART0_RX - USART0 RX Consumer Selection ........341

13.5.67 PRS_CONSUMER_USART0_TRIGGER - USART0 TRIGGER Consumer Selection ...341

13.5.68 PRS_CONSUMER_USART1_CLK - USART1 CLK Consumer Selection .......342

13.5.69 PRS_CONSUMER_USART1_IR - USART1 IR Consumer Selection ........342

13.5.70 PRS_CONSUMER_USART1_RX - USART1 RX Consumer Selection ........343

13.5.71 PRS_CONSUMER_USART1_TRIGGER - USART1 TRIGGER Consumer Selection ...343

13.5.72 PRS_CONSUMER_USART2_CLK - USART2 CLK Consumer Selection .......344

13.5.73 PRS_CONSUMER_USART2_IR - USART2 IR Consumer Selection ........344

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13.5.74 PRS_CONSUMER_USART2_RX - USART2 RX Consumer Selection ........345

13.5.75 PRS_CONSUMER_USART2_TRIGGER - USART2 TRIGGER Consumer Selection ...345

13.5.76 PRS_CONSUMER_WDOG0_SRC0 - WDOG0 SRC0 Consumer Selection ......346

13.5.77 PRS_CONSUMER_WDOG0_SRC1 - WDOG0 SRC1 Consumer Selection ......346

13.5.78

PRS_CONSUMER_WDOG1_SRC0 - WDOG1 SRC0 Consumer Selection ......347

13.5.79 PRS_CONSUMER_WDOG1_SRC1 - WDOG1 SRC1 Consumer Selection ......347

14. GPCRC - General Purpose Cyclic Redundancy Check ..............348

14.1 Introduction..............................348

14.2 Features ..............................348

14.3 Functional Description ..........................349

14.3.1 Polynomial Specification ........................350

14.3.2 Input and Output Specification ......................350

14.3.3 Initialization ............................350

14.3.4 DMA Usage ............................350

14.3.5 Byte-Level Bit Reversal and Byte Reordering .................351

14.4 Register Map .............................354

14.5 Register Description ...........................355

14.5.1 GPCRC_IPVERSION - IP Version ID ...................355

14.5.2 GPCRC_EN - CRC Enable .......................356

14.5.3 GPCRC_CTRL - Control Register .....................357

14.5.4 GPCRC_CMD - Command Register ....................358

14.5.5 GPCRC_INIT - CRC Init Value ......................358

14.5.6 GPCRC_POLY - CRC Polynomial Value ..................359

14.5.7 GPCRC_INPUTDATA - Input 32-bit Data Register ...............359

14.5.8 GPCRC_INPUTDATAHWORD - Input 16-bit Data Register ............360

14.5.9 GPCRC_INPUTDATABYTE - Input 8-bit Data Register .............360

14.5.10 GPCRC_DATA - CRC Data Register ...................361

14.5.11 GPCRC_DATAREV - CRC Data Reverse Register ..............361

14.5.12 GPCRC_DATABYTEREV - CRC Data Byte Reverse Register ...........362

15. RTCC - Real Time Clock with Capture.....................363

15.1 Introduction..............................363

15.2 Features ..............................363

15.3 Functional Description ..........................364

15.3.1 RTCC Counter ...........................365

15.3.2 Capture/Compare Channels ......................367

15.3.3 Interrupts and PRS Output .......................368

15.3.4 Register Lock ...........................369

15.3.5 Programmer's Model .........................369

15.3.6 Debug Features and Description .....................369

15.4 Register Map .............................370

15.5 Register Description ...........................372

15.5.1 RTCC_IPVERSION - IP VERSION ....................372

15.5.2 RTCC_EN - Module Enable Register ...................372

15.5.3 RTCC_CFG - Configuration Register ...................373

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15.5.4 RTCC_CMD - Command Register ....................374

15.5.5 RTCC_STATUS - Status register .....................375

15.5.6 RTCC_IF - RTCC Interrupt Flags .....................376

15.5.7 RTCC_IEN - Interrupt Enable Register ...................377

15.5.8 RTCC_PRECNT - Pre-Counter Value Register ................377

15.5.9 RTCC_CNT - Counter Value Register ...................378

15.5.10 RTCC_COMBCNT - Combined Pre-Counter and Counter Valu... ..........378

15.5.11 RTCC_SYNCBUSY - Synchronization Busy Register ..............379

15.5.12 RTCC_LOCK - Configuration Lock Register .................379

15.5.13 RTCC_CCx_CTRL - CC Channel Control Register ..............380

15.5.14 RTCC_CCx_OCVALUE - Output Compare Value Register ............381

15.5.15 RTCC_CCx_ICVALUE - Input Capture Value Register .............381

16. BURTC

- Back-Up Real Time Counter .....................382

16.1 Introduction..............................382

16.2 Features ..............................382

16.3 Functional Description ..........................383

16.3.1 Clock Selection ...........................383

16.3.2 Configuration ...........................383

16.3.3 Debug Features and Description .....................383

16.3.4 Counter .............................384

16.3.5 Compare Channel ..........................384

16.3.6 Interrupts .............................385

16.3.7 Register Lock ...........................385

16.4 Register Map .............................386

16.5 Register Description ...........................387

16.5.1 BURTC_IPVERSION - IP version ID ....................387

16.5.2 BURTC_EN - Module Enable Register ...................388

16.5.3 BURTC_CFG - Configuration Register ...................389

16.5.4 BURTC_CMD - Command Register ....................390

16.5.5 BURTC_STATUS - Status Register ....................391

16.5.6 BURTC_IF - Interrupt Flag Register ....................391

16.5.7 BURTC_IEN - Interrupt Enable Register ..................392

16.5.8 BURTC_PRECNT - Pre-Counter Value Register ................392

16.5.9 BURTC_CNT - Counter Value Register ...................393

16.5.10 BURTC_EM4WUEN - EM4 wakeup request Enable Register ...........393

16.5.11 BURTC_SYNCBUSY - Synchronization Busy Register .............394

16.5.12 BURTC_LOCK - Configuration Lock Register ................395

16.5.13 BURTC_COMP - Compare Value Register .................395

17. BURAM - Backup RAM ..........................396

17.1 Introduction..............................396

17.2 Functional Description ..........................396

17.3 Register Map .............................396

17.4 Register Description ...........................397

17.4.1 BURAM_RETx_REG - Retention Register ..................397

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18. LETIMER - Low Energy Timer ........................398

18.1 Introduction..............................398

18.2 Features ..............................398

18.3 Functional Description ..........................399

18.3.1 Internal Overview ..........................400

18.3.2 Free Running Mode .........................401

18.3.3 One-shot Mode ...........................402

18.3.4 Buffered Mode ...........................403

18.3.5 Double Mode ...........................404

18.4 Clock Frequency ............................405

18.5 PRS Input Triggers ...........................406

18.6

Debug ...............................406

18.7 Output Action .............................407

18.8 PRS Output .............................407

18.9 Interrupts ..............................407

18.10 Using the LETIMER in EM3 ........................407

18.11 Register access ............................407

18.12 Programmer's Model ..........................408

18.12.1 FREE Running Mode ........................409

18.12.2 One Shot Mode ..........................410

18.12.3 DOUBLE Mode ..........................410

18.12.4 BUFFERED Mode .........................411

18.12.5 Continuous Output Generation .....................412

18.12.6 PWM Output ...........................413

18.13 Register Map.............................414

18.14 Register Description ..........................416

18.14.1 LETIMER_IPVERSION - IP version....................416

18.14.2 LETIMER_EN - module en ......................416

18.14.3 LETIMER_CTRL - Control Register ....................417

18.14.4 LETIMER_CMD - Command Register ...................419

18.14.5 LETIMER_STATUS - Status Register ...................420

18.14.6 LETIMER_CNT - Counter Value Register..................420

18.14.7 LETIMER_COMP0 - Compare Value Register 0 ...............421

18.14.8 LETIMER_COMP1 - Compare Value Register 1 ...............421

18.14.9 LETIMER_TOP - Counter TOP Value Register ................422

18.14.10 LETIMER_TOPBUFF - Buffered Counter TOP Value .............422

18.14.11 LETIMER_REP0 - Repeat Counter Register 0................423

18.14.12 LETIMER_REP1 - Repeat Counter Register 1................423

18.14.13 LETIMER_IF - Interrupt Flag Register ..................424

18.14.14 LETIMER_IEN - Interrupt Enable Register .................425

18.14.15 LETIMER_SYNCBUSY - Synchronization Busy Register ............426

18.14.16 LETIMER_PRSMODE - PRS Input mode select Register ............427

19. TIMER - Timer/Counter ..........................429

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19.1 Introduction..............................429

19.2 Features ..............................430

19.3 Functional Description ..........................431

19.3.1 Register Access...........................431

19.3.2

Counter Modes ...........................432

19.3.3 Compare/Capture Channels ......................438

19.3.4 Dead-Time Insertion Unit .......................449

19.3.5 Debug Mode ............................453

19.3.6 Interrupts, DMA and PRS Output .....................453

19.3.7 GPIO Input/Output ..........................453

19.4 Register Map .............................454

19.5 Register Description ...........................457

19.5.1 TIMER_IPVERSION - IP version ID ....................457

19.5.2 TIMER_CFG - Configuration Register ...................458

19.5.3 TIMER_CTRL - Control Register .....................461

19.5.4 TIMER_CMD - Command Register ....................462

19.5.5 TIMER_STATUS - Status Register ....................463

19.5.6 TIMER_IF - Interrupt Flag Register ....................466

19.5.7 TIMER_IEN - Interrupt Enable Register ...................468

19.5.8 TIMER_TOP - Counter Top Value Register .................469

19.5.9 TIMER_TOPB - Counter Top Value Buffer Register ...............469

19.5.10 TIMER_CNT - Counter Value Register ..................470

19.5.11 TIMER_LOCK - TIMER Configuration Lock Register ..............470

19.5.12 TIMER_EN - module en .......................471

19.5.13 TIMER_CCx_CFG - CC Channel Configuration Register ............472

19.5.14 TIMER_CCx_CTRL - CC Channel Control Register ..............474

19.5.15 TIMER_CCx_OC - OC Channel Value Register ...............475

19.5.16 TIMER_CCx_OCB - OC Channel Value Buffer Register .............476

19.5.17 TIMER_CCx_ICF - IC Channel Value Register ................476

19.5.18 TIMER_CCx_ICOF - IC Channel Value Overflow Register ............476

19.5.19 TIMER_DTCFG - DTI Configuration Register ................477

19.5.20 TIMER_DTTIMECFG - DTI Time Configuration Register ............478

19.5.21 TIMER_DTFCFG - DTI Fault Configuration Register ..............479

19.5.22 TIMER_DTCTRL - DTI Control Register ..................480

19.5.23 TIMER_DTOGEN - DTI Output Generation Enable Register ...........481

19.5.24 TIMER_DTFAULT - DTI Fault Register ..................482

19.5.25 TIMER_DTFAULTC - DTI Fault Clear Register ................483

19.5.26 TIMER_DTLOCK - DTI Configuration Lock Register ..............484

20. USART - Universal Synchronous Asynchronous Receiver/Transmitter ........485

20.1 Introduction..............................485

20.2 Features ..............................486

20.3 Functional Description ..........................487

20.3.1 Modes of Operation .........................488

20.3.2 Asynchronous Operation ........................488

20.3.3 Synchronous Operation ........................504

20.3.4 Hardware Flow Control ........................510

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20.3.5 Debug Halt ............................510

20.3.6 PRS-triggered Transmissions ......................510

20.3.7 PRS RX Input ...........................510

20.3.8

PRS CLK Input ...........................511

20.3.9 DMA Support ...........................511

20.3.10 Timer ..............................512

20.3.11 Interrupts ............................517

20.3.12 IrDA Modulator/ Demodulator ......................518

20.4 Register Map .............................519

20.5 Register Description ...........................522

20.5.1 USART_IPVERSION - IPVERSION ....................522

20.5.2 USART_EN - USART Enable ......................522

20.5.3 USART_CTRL - Control Register .....................523

20.5.4 USART_FRAME - USART Frame Format Register ...............528

20.5.5 USART_TRIGCTRL - USART Trigger Control register ..............530

20.5.6 USART_CMD - Command Register ....................531

20.5.7 USART_STATUS - USART Status Register .................532

20.5.8 USART_CLKDIV - Clock Control Register ..................533

20.5.9 USART_RXDATAX - RX Buffer Data Extended Register .............534

20.5.10 USART_RXDATA - RX Buffer Data Register ................534

20.5.11 USART_RXDOUBLEX - RX Buffer Double Data Extended Register .........535

20.5.12 USART_RXDOUBLE - RX FIFO Double Data Register .............536

20.5.13 USART_RXDATAXP - RX Buffer Data Extended Peek Register ..........536

20.5.14 USART_RXDOUBLEXP - RX Buffer Double Data Extended Peek R... ........537

20.5.15 USART_TXDATAX - TX Buffer Data Extended Register .............538

20.5.16 USART_TXDATA - TX Buffer Data Register .................539

20.5.17 USART_TXDOUBLEX - TX Buffer Double Data Extended Register .........540

20.5.18 USART_TXDOUBLE - TX Buffer Double Data Register .............541

20.5.19 USART_IF - Interrupt Flag Register....................542

20.5.20 USART_IEN - Interrupt Enable Register ..................544

20.5.21 USART_IRCTRL - IrDA Control Register ..................546

20.5.22 USART_I2SCTRL - I2S Control Register ..................547

20.5.23 USART_TIMING - Timing Register ....................549

20.5.24 USART_CTRLX - Control Register Extended ................551

20.5.25 USART_TIMECMP0 - Used to generate interrupts and vario... ..........553

20.5.26 USART_TIMECMP1 - Used to generate interrupts and vario... ..........555

20.5.27 USART_TIMECMP2 - Used to generate interrupts and vario... ..........557

21. I2C - Inter-Integrated Circuit Interface .....................559

21.1 Introduction..............................559

21.2 Features ..............................559

21.3 Functional Description ..........................560

21.3.1 I2C-Bus Overview ..........................561

21.3.2 Enable and Reset ..........................565

21.3.3 Pin Configuration ..........................565

21.3.4 Safely Disabling and Changing Slave Configuration...............565

21.3.5 Clock Generation ..........................566

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21.3.6 Arbitration .............................566

21.3.7 Buffers ..............................566

21.3.8 Master Operation ..........................569

21.3.9

Bus States ............................577

21.3.10 Slave Operation ..........................577

21.3.11 Transfer Automation .........................581

21.3.12 Using 10-bit Addresses ........................582

21.3.13 Error Handling ...........................582

21.3.14 DMA Support ...........................584

21.3.15 Interrupts ............................584

21.3.16 Wake-up .............................584

21.4 Register Map .............................585

21.5 Register Description ...........................587

21.5.1 I2C_IPVERSION - IP VERSION Register ..................587

21.5.2 I2C_EN - Enable Register .......................587

21.5.3 I2C_CTRL - Control Register ......................588

21.5.4 I2C_CMD - Command Register .....................592

21.5.5 I2C_STATE - State Register ......................593

21.5.6 I2C_STATUS - Status Register .....................594

21.5.7 I2C_CLKDIV - Clock Division Register ...................595

21.5.8 I2C_SADDR - Slave Address Register ...................595

21.5.9 I2C_SADDRMASK - Slave Address Mask Register ...............596

21.5.10 I2C_RXDATA - Receive Buffer Data Register ................596

21.5.11 I2C_RXDOUBLE - Receive Buffer Double Data Register ............597

21.5.12 I2C_RXDATAP - Receive Buffer Data Peek Register ..............597

21.5.13 I2C_RXDOUBLEP - Receive Buffer Double Data Peek Register ..........598

21.5.14 I2C_TXDATA - Transmit Buffer Data Register ................598

21.5.15 I2C_TXDOUBLE - Transmit Buffer Double Data Register ............599

21.5.16 I2C_IF - Interrupt Flag Register .....................600

21.5.17 I2C_IEN - Interrupt Enable Register ...................602

22. ACMP - Analog Comparator ........................604

22.1 Introduction .............................604

22.2 Features ..............................604

22.3 Functional Description ..........................605

22.3.1 Configuration and Control .......................605

22.3.2 Warmup Time ...........................606

22.3.3 Response Time ...........................606

22.3.4 Hysteresis ............................606

22.3.5 VREFDIV Sources ..........................607

22.3.6 Supply Voltage Monitoring (VSENSE) ...................607

22.3.7 Input Range and Accuracy Settings ....................607

22.3.8 Capacitive Sense Mode ........................608

22.3.9 Interrupts and PRS Output .......................609

22.3.10 Output to GPIO ..........................609

22.4 Register Map .............................610

22.5 Register Description ...........................611

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22.5.1 ACMP_IPVERSION - IP version ID ....................611

22.5.2 ACMP_EN - ACMP enable .......................611

22.5.3 ACMP_CFG - Configuration register ....................612

22.5.4 ACMP_CTRL - Control Register .....................613

22.5.5 ACMP_INPUTCTRL - Input Control Register .................614

22.5.6 ACMP_STATUS - Status Register ....................619

22.5.7 ACMP_IF - Interrupt Flag Register ....................620

22.5.8

ACMP_IEN - Interrupt Enable Register ...................621

22.5.9 ACMP_SYNCBUSY - Syncbusy .....................621

23. IADC - Incremental Analog to Digital Converter .................622

23.1 Introduction..............................622

23.2 Features ..............................623

23.3 Functional Description ..........................624

23.3.1 Register Access...........................625

23.3.2 Clocking .............................626

23.3.3 Conversion Timing ..........................627

23.3.4 Reference Selection and Analog Gain ...................635

23.3.5 Input and Configuration Selection .....................635

23.3.6 Gain and Offset Correction .......................640

23.3.7 Output Data FIFOs ..........................644

23.3.8 Window Compare ..........................646

23.3.9 Interrupts .............................647

23.4 Register Map .............................648

23.5 Register Description ...........................651

23.5.1 IADC_IPVERSION - IPVERSION .....................651

23.5.2 IADC_EN - Enable ..........................651

23.5.3 IADC_CTRL - Control ........................652

23.5.4 IADC_CMD - Command ........................654

23.5.5 IADC_TIMER - Timer .........................655

23.5.6 IADC_STATUS - Status ........................656

23.5.7 IADC_MASKREQ - Mask Request ....................657

23.5.8 IADC_STMASK - Scan Table Mask ....................658

23.5.9 IADC_CMPTHR - Digital Window Comparator Threshold .............658

23.5.10 IADC_IF - Interrupt Flags .......................659

23.5.11 IADC_IEN - Interrupt Enable ......................661

23.5.12 IADC_TRIGGER - Trigger .......................663

23.5.13 IADC_CFGx - Configuration ......................666

23.5.14 IADC_SCALEx - Scaling .......................668

23.5.15 IADC_SCHEDx - Scheduling ......................668

23.5.16 IADC_SINGLEFIFOCFG - Single FIFO Configuration .............669

23.5.17 IADC_SINGLEFIFODATA - Single FIFO Read Data ..............670

23.5.18 IADC_SINGLEFIFOSTAT - Single FIFO Status ................670

23.5.19 IADC_SINGLEDATA - Single Data ....................671

23.5.20 IADC_SCANFIFOCFG - Scan FIFO Configuration ...............672

23.5.21 IADC_SCANFIFODATA - Scan FIFO Read Data ...............673

23.5.22 IADC_SCANFIFOSTAT - Scan FIFO Status .................673

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23.5.23 IADC_SCANDATA - Scan Data .....................674

23.5.24 IADC_SINGLE - Single Queue Port Selection ................675

23.5.25

IADC_SCANx - SCAN Entry ......................677

24. GPIO - General Purpose Input/Output .....................679

24.1 Introduction .............................679

24.2 Features ..............................680

24.3 Functional Description ..........................681

24.3.1 Pin Configuration ..........................682

24.3.2 Alternate Port Control ........................684

24.3.3 Slew Rate .............................684

24.3.4 Input Disable ............................684

24.3.5 Configuration Lock ..........................684

24.3.6 EM2 Functionality ..........................684

24.3.7 EM4 Functionality ..........................684

24.3.8 EM4 Wakeup ...........................685

24.3.9 Debug Connections .........................685

24.3.10 Interrupt Generation .........................686

24.3.11 Output to PRS ...........................687

24.3.12 Peripheral Resource Routing ......................687

24.4 Synchronization ............................692

24.5 Register Map .............................693

24.6 Register Description ...........................710

24.6.1 GPIO_PORTA_CTRL - Port control ....................710

24.6.2 GPIO_PORTA_MODEL - mode low ....................711

24.6.3 GPIO_PORTA_DOUT - data out .....................715

24.6.4 GPIO_PORTA_DIN - data in ......................715

24.6.5 GPIO_PORTB_CTRL - Port control ....................716

24.6.6 GPIO_PORTB_MODEL - mode low ....................717

24.6.7 GPIO_PORTB_DOUT - data out .....................718

24.6.8 GPIO_PORTB_DIN - data in ......................719

24.6.9 GPIO_PORTC_CTRL - Port control ....................720

24.6.10 GPIO_PORTC_MODEL - mode low ...................721

24.6.11 GPIO_PORTC_DOUT - data out ....................724

24.6.12 GPIO_PORTC_DIN - data in ......................725

24.6.13 GPIO_PORTD_CTRL - Port control ...................726

24.6.14 GPIO_PORTD_MODEL - mode low ...................727

24.6.15 GPIO_PORTD_DOUT - data out ....................730

24.6.16 GPIO_PORTD_DIN - data in ......................730

24.6.17 GPIO_LOCK - main .........................731

24.6.18 GPIO_GPIOLOCKSTATUS - Lock Status .................731

24.6.19 GPIO_ABUSALLOC - A Bus allocation ..................732

24.6.20 GPIO_BBUSALLOC - B Bus allocation ..................734

24.6.21 GPIO_CDBUSALLOC - CD Bus allocation .................736

24.6.22 GPIO_EXTIPSELL - External Interrupt Port Select Low .............738

24.6.23 GPIO_EXTIPINSELL - External Interrupt Pin Select Low ............741

24.6.24 GPIO_EXTIRISE - External Interrupt Rising Edge Trigger ............743

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24.6.25 GPIO_EXTIFALL - External Interrupt Falling Edge Trigger ............744

24.6.26 GPIO_IF - Interrupt Flag .......................744

24.6.27 GPIO_IEN - Interrupt Enable ......................745

24.6.28 GPIO_EM4WUEN - main .......................745

24.6.29 GPIO_EM4WUPOL - New Register....................746

24.6.30 GPIO_DBGROUTEPEN - Debugger Route Pin enable .............747

24.6.31 GPIO_TRACEROUTEPEN - Trace Route Pin Enable .............748

24.6.32 GPIO_ACMP0_ROUTEEN - ACMP0 pin enable ...............748

24.6.33 GPIO_ACMP0_ACMPOUTROUTE - ACMPOUT port/pin select ..........749

24.6.34 GPIO_ACMP1_ROUTEEN - ACMP1 pin enable ...............749

24.6.35

GPIO_ACMP1_ACMPOUTROUTE - ACMPOUT port/pin select ..........750

24.6.36 GPIO_CMU_ROUTEEN - CMU pin enable .................750

24.6.37 GPIO_CMU_CLKIN0ROUTE - CLKIN0 port/pin select .............751

24.6.38 GPIO_CMU_CLKOUT0ROUTE - CLKOUT0 port/pin select ...........751

24.6.39 GPIO_CMU_CLKOUT1ROUTE - CLKOUT1 port/pin select ...........752

24.6.40 GPIO_CMU_CLKOUT2ROUTE - CLKOUT2 port/pin select ...........752

24.6.41 GPIO_FRC_ROUTEEN - FRC pin enable .................753

24.6.42 GPIO_FRC_DCLKROUTE - DCLK port/pin select ...............753

24.6.43 GPIO_FRC_DFRAMEROUTE - DFRAME port/pin select ............754

24.6.44 GPIO_FRC_DOUTROUTE - DOUT port/pin select ..............754

24.6.45 GPIO_I2C0_ROUTEEN - I2C0 pin enable .................755

24.6.46 GPIO_I2C0_SCLROUTE - SCL port/pin select ................755

24.6.47 GPIO_I2C0_SDAROUTE - SDA port/pin select ................756

24.6.48 GPIO_I2C1_ROUTEEN - I2C1 pin enable .................756

24.6.49 GPIO_I2C1_SCLROUTE - SCL port/pin select ................757

24.6.50 GPIO_I2C1_SDAROUTE - SDA port/pin select ................757

24.6.51 GPIO_LETIMER0_ROUTEEN - LETIMER pin enable .............758

24.6.52 GPIO_LETIMER0_OUT0ROUTE - OUT0 port/pin select ............758

24.6.53 GPIO_LETIMER0_OUT1ROUTE - OUT1 port/pin select ............759

24.6.54 GPIO_MODEM_ROUTEEN - MODEM pin enable ...............759

24.6.55 GPIO_MODEM_ANT0ROUTE - ANT0 port/pin select .............760

24.6.56 GPIO_MODEM_ANT1ROUTE - ANT1 port/pin select .............760

24.6.57 GPIO_MODEM_DCLKROUTE - DCLK port/pin select .............761

24.6.58 GPIO_MODEM_DINROUTE - DIN port/pin select ...............761

24.6.59 GPIO_MODEM_DOUTROUTE - DOUT port/pin select .............762

24.6.60 GPIO_PRS0_ROUTEEN - PRS0 pin enable.................763

24.6.61 GPIO_PRS0_ASYNCH0ROUTE - ASYNCH0 port/pin select ...........764

24.6.62 GPIO_PRS0_ASYNCH1ROUTE - ASYNCH1 port/pin select ...........765

24.6.63 GPIO_PRS0_ASYNCH2ROUTE - ASYNCH2 port/pin select ...........765

24.6.64 GPIO_PRS0_ASYNCH3ROUTE - ASYNCH3 port/pin select ...........766

24.6.65 GPIO_PRS0_ASYNCH4ROUTE - ASYNCH4 port/pin select ...........766

24.6.66 GPIO_PRS0_ASYNCH5ROUTE - ASYNCH5 port/pin select ...........767

24.6.67 GPIO_PRS0_ASYNCH6ROUTE - ASYNCH6 port/pin select ...........767

24.6.68 GPIO_PRS0_ASYNCH7ROUTE - ASYNCH7 port/pin select ...........768

24.6.69 GPIO_PRS0_ASYNCH8ROUTE - ASYNCH8 port/pin select ...........768

24.6.70 GPIO_PRS0_ASYNCH9ROUTE - ASYNCH9 port/pin select ...........769

24.6.71 GPIO_PRS0_ASYNCH10ROUTE - ASYNCH10 port/pin select ..........769

24.6.72 GPIO_PRS0_ASYNCH11ROUTE - ASYNCH11 port/pin select ..........770

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24.6.73 GPIO_PRS0_SYNCH0ROUTE - SYNCH0 port/pin select ............770

24.6.74 GPIO_PRS0_SYNCH1ROUTE - SYNCH1 port/pin select ............771

24.6.75 GPIO_PRS0_SYNCH2ROUTE - SYNCH2 port/pin select ............771

24.6.76 GPIO_PRS0_SYNCH3ROUTE - SYNCH3 port/pin select ............772

24.6.77 GPIO_TIMER0_ROUTEEN - TIMER0 pin enable ...............773

24.6.78 GPIO_TIMER0_CC0ROUTE - CC0 port/pin select ..............774

24.6.79 GPIO_TIMER0_CC1ROUTE - CC1 port/pin select ..............774

24.6.80 GPIO_TIMER0_CC2ROUTE - CC2 port/pin select ..............775

24.6.81 GPIO_TIMER0_CDTI0ROUTE - CDTI0 port/pin select .............775

24.6.82 GPIO_TIMER0_CDTI1ROUTE - CDTI1 port/pin select .............776

24.6.83 GPIO_TIMER0_CDTI2ROUTE - CDTI2 port/pin select .............776

24.6.84 GPIO_TIMER1_ROUTEEN - TIMER1 pin enable ...............777

24.6.85 GPIO_TIMER1_CC0ROUTE - CC0 port/pin select ..............778

24.6.86 GPIO_TIMER1_CC1ROUTE - CC1 port/pin select ..............778

24.6.87 GPIO_TIMER1_CC2ROUTE - CC2 port/pin select ..............779

24.6.88 GPIO_TIMER1_CDTI0ROUTE - CDTI0 port/pin select .............779

24.6.89 GPIO_TIMER1_CDTI1ROUTE - CDTI1 port/pin select .............780

24.6.90 GPIO_TIMER1_CDTI2ROUTE - CDTI2 port/pin select .............780

24.6.91 GPIO_TIMER2_ROUTEEN - TIMER2 pin enable ...............781

24.6.92 GPIO_TIMER2_CC0ROUTE - CC0 port/pin select ..............782

24.6.93 GPIO_TIMER2_CC1ROUTE - CC1 port/pin select ..............782

24.6.94 GPIO_TIMER2_CC2ROUTE - CC2 port/pin select ..............783

24.6.95 GPIO_TIMER2_CDTI0ROUTE - CDTI0 port/pin select .............783

24.6.96 GPIO_TIMER2_CDTI1ROUTE - CDTI1 port/pin select .............784

24.6.97

GPIO_TIMER2_CDTI2ROUTE - CDTI2 port/pin select .............784

24.6.98 GPIO_TIMER3_ROUTEEN - TIMER3 pin enable ...............785

24.6.99 GPIO_TIMER3_CC0ROUTE - CC0 port/pin select ..............786

24.6.100 GPIO_TIMER3_CC1ROUTE - CC1 port/pin select ..............786

24.6.101 GPIO_TIMER3_CC2ROUTE - CC2 port/pin select ..............787

24.6.102 GPIO_TIMER3_CDTI0ROUTE - CDTI0 port/pin select .............787

24.6.103 GPIO_TIMER3_CDTI1ROUTE - CDTI1 port/pin select .............788

24.6.104 GPIO_TIMER3_CDTI2ROUTE - CDTI2 port/pin select .............788

24.6.105 GPIO_USART0_ROUTEEN - USART0 pin enable ..............789

24.6.106 GPIO_USART0_CSROUTE - CS port/pin select ...............789

24.6.107 GPIO_USART0_CTSROUTE - CTS port/pin select ..............790

24.6.108 GPIO_USART0_RTSROUTE - RTS port/pin select ..............790

24.6.109 GPIO_USART0_RXROUTE - RX port/pin select ...............791

24.6.110 GPIO_USART0_CLKROUTE - CLK port/pin select ..............791

24.6.111 GPIO_USART0_TXROUTE - TX port/pin select ...............792

24.6.112 GPIO_USART1_ROUTEEN - USART1 pin enable ..............792

24.6.113 GPIO_USART1_CSROUTE - CS port/pin select ...............793

24.6.114 GPIO_USART1_CTSROUTE - CTS port/pin select ..............793

24.6.115 GPIO_USART1_RTSROUTE - RTS port/pin select ..............794

24.6.116 GPIO_USART1_RXROUTE - RX port/pin select ...............794

24.6.117 GPIO_USART1_CLKROUTE - CLK port/pin select ..............795

24.6.118 GPIO_USART1_TXROUTE - TX port/pin select ...............795

24.6.119 GPIO_USART2_ROUTEEN - USART2 pin enable ..............796

24.6.120 GPIO_USART2_CSROUTE - CS port/pin select ...............796

silabs.com | Building a more connected world. Rev. 0.5 | 19

24.6.121 GPIO_USART2_CTSROUTE - CTS port/pin select ..............797

24.6.122 GPIO_USART2_RTSROUTE - RTS port/pin select ..............797

24.6.123 GPIO_USART2_RXROUTE - RX port/pin select ...............798

24.6.124 GPIO_USART2_CLKROUTE - CLK port/pin select ..............798

24.6.125 GPIO_USART2_TXROUTE - TX port/pin select ...............799

25. LDMA - Linked DMA ...........................800

25.1 Introduction..............................800

25.1.1 Features .............................801

25.2 Block Diagram.............................802

25.3 Functional Description ..........................803

25.3.1 Channel Descriptor .........................803

25.3.2 Channel Configuration ........................808

25.3.3 Channel Select Configuration ......................808

25.3.4 Starting a transfer ..........................808

25.3.5 Managing Transfer Errors .......................809

25.3.6

Arbitration .............................809

25.3.7 Channel descriptor data structure .....................811

25.3.8 Interaction with the EMU ........................814

25.3.9 Interrupts .............................815

25.3.10 Debugging ............................815

25.4 Examples ..............................815

25.4.1 Single Direct Register DMA Transfer ....................815

25.4.2 Descriptor Linked List .........................816

25.4.3 Single Descriptor Looped Transfer ....................818

25.4.4 Descriptor List with Looping .......................819

25.4.5 Simple Inter-Channel Synchronization ...................820

25.4.6 2D Copy .............................822

25.4.7 Ping-Pong ............................824

25.4.8 Scatter-Gather ...........................825

25.5 LDMA Source Selection Details .......................825

25.5.1 LDMA Source Selection Details .....................826

25.6 Register Map .............................828

25.7 Register Description ...........................831

25.7.1 LDMA_IPVERSION - DMA Channel Request Clear Register ...........831

25.7.2 LDMA_EN - DMA module enable disable Register ...............831

25.7.3 LDMA_CTRL - DMA Control Register ...................832

25.7.4 LDMA_STATUS - DMA Status Register...................833

25.7.5 LDMA_SYNCSWSET - DMA Sync Trig Sw Set Register .............834

25.7.6 LDMA_SYNCSWCLR - DMA Sync Trig Sw Clear register ............834

25.7.7 LDMA_SYNCHWEN - DMA Sync HW trigger enable register ...........835

25.7.8 LDMA_SYNCHWSEL - DMA Sync HW trigger selection register ..........836

25.7.9 LDMA_SYNCSTATUS - DMA Sync Trigger Status Register ............837

25.7.10 LDMA_CHEN - DMA Channel Enable Register ................837

25.7.11 LDMA_CHDIS - DMA Channel Disable Register ...............838

25.7.12 LDMA_CHSTATUS - DMA Channel Status Register ..............838

25.7.13 LDMA_CHBUSY - DMA Channel Busy Register ...............839

silabs.com | Building a more connected world. Rev. 0.5 | 20

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Silicon Labs EFR32xG21 Wireless Gecko Reference guide

Silicon Labs EFR32xG21 Wireless Gecko Reference guide

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