Epson S1D13708 User manual

S1D13708 Embedded Memory LCD Controller

S1D13708

TECHNICAL MANUAL

Document Number: X39A-Q-001-01

Information in this document is subject to change without notice. You may download and use this document, but only for your own use in

evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any

representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain

material protected under U.S. and/or International Patent laws.

EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.

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TECHNICAL MANUAL S1D13708

Issue Date: 01/10/09 X39A-Q-001-01

COMPREHENSIVE SUPPORT TOOLS

EPSON provides the designer and manufacturer a complete set of resources and tools for the development of LCD

Graphics Systems.

Documentation

• Technical manuals

• Evaluation/Demonstration board manual

Evaluation/Demonstration Board

• Assembled and fully tested Graphics Evaluation/Demonstration board

• Schematic of Evaluation/Demonstration board

• Parts List

• Installation Guide

• CPU Independent Software Utilities

• Evaluation Software

•Display Drivers

Application Engineering Support

EPSON offers the following services through their Sales and Marketing Network:

• Sales Technical Support

• Customer Training

• Design Assistance

Application Engineering Support

Engineering and Sales Support is provided by:

Japan

Seiko Epson Corporation

Electronic Devices Marketing Division

421-8, Hino, Hino-shi

Tokyo 191-8501, Japan

Tel: 042-587-5812

Fax: 042-587-5564

http://www.epson.co.jp/

Hong Kong

Epson Hong Kong Ltd.

20/F., Harbour Centre

25 Harbour Road

Wanchai, Hong Kong

Tel: 2585-4600

Fax: 2827-4346

http://www.epson.com.hk/

Taiwan

Epson Taiwan Technology

& Trading Ltd.

10F, No. 287

Nanking East Road

Sec. 3, Taipei, Taiwan

Tel: 02-2717-7360

Fax: 02-2712-9164

http://www.epson.com.tw/

Singapore

Epson Singapore Pte., Ltd.

No. 1

Temasek Avenue #36-00

Millenia Tower

Singapore, 039192

Tel: 337-7911

Fax: 334-2716

http://www.epson.com.sg/

Europe

Epson Europe Electronics GmbH

Riesstrasse 15

80992 Munich, Germany

Tel: 089-14005-0

Fax: 089-14005-110

http://www.epson-electronics.de/

North America

Epson Electronics America, Inc.

150 River Oaks Parkway

San Jose, CA 95134, USA

Tel: (408) 922-0200

Fax: (408) 922-0238

http://www.eea.epson.com/

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X39A-C-001-01 1

GRAPHICS

S1D13708

ENERGY

SAVING

EPSON

S1D13708 Embedded Memory LCD Controller

July 2001

The S1D13708 is a color/monochrome LCD graphics controller with an embedded memory / display

buffer. Targeted at PDA and Cell Phone applications, the S1D13708 ‘directly’ interfaces to numerous

TFT panels and incorporates a minimum pin-count CPU interface thereby making it an ideal solution for

an LCD Module.

This high level of integration combined with a 1.8V Core, provides a low cost, low power, single chip

solution to meet the demands of embedded markets such as Mobile Communications devices and

Palm-size PCs, where board size and battery life are major concerns.

The embedded display buffer greatly improves overall system performance as the S1D13708 handles

all of the display functions directly with very little interaction from the processor.

The S1D13708 provides very flexible display features, from our patented SwivelView

TM

technology

which provides hardware rotation of the displayed image, to our Ink Layer with transparency, to our

“Picture-in-Picture Plus” feature which allows two active variable size display ‘windows’.

The S1D13708 provides impressive support for Mobile Communication devices and Palm OS



handhelds, however its impartiality to CPU type or operating system makes it an ideal display solution

for a wide variety of applications.

■

FEATURES

■

SYSTEM BLOCK DIAGRAM

•

Embedded Display Buffer.

•

Low Operating Voltage.

•

Low-latency CPU interface.

•

Direct support for the multiple CPU types.

•

Programmable Resolutions and Color depths.

•

STN LCD support.

•

Active Matrix LCD support.

•

Reflective Active Matrix support.

•

SwivelView

TM

(hardware rotation of displayed image)

.

• (Patent # 5,734,875 - Patent # 5,956,049)

•

“Picture-in-Picture Plus”.

•

Ink Layer.

•

Software Initiated Power Save Mode.

•

Hardware or Software Video Invert.

•

120-pin PFBGA package.

S1D13708

Flat Panel

Data and

CPU

Control Signals

Digital Out

X39A-C-001-01 2

GRAPHICS

S1D13708

■

DESCRIPTION

Memory Interface

• Embedded 80K byte SRAM display buffer.

CPU Interface

• ‘Fixed’ low-latency CPU access times.

• Direct support for:

Hitachi SH-4 / SH-3.

Motorola M68xxx

(DragonBall, ColdFire,REDCAP2)

.

MPU bus interface with programmable READY.

• InDirect Interface

provides a minimum 15-pin interface (as compared to

42-pin max implementation).

Display Support

• 4/8-bit monochrome LCD interface.

• 4/8/16-bit color STN LCD interface.

• Single-panel, single-drive passive displays.

• 9/12/18-bit Active matrix TFT interface.

• ‘Direct’ support for multiple TFT interfaces (Epson, Sharp,

Type 2,3,4 external timing control IC not required).

• Typical resolutions supported (Ink Layer disabled):

- 320x240 @ 8bpp

- 160x160 @ 16bpp

- 160x240 @ 16bpp

Power Down Modes

• Software Initiated Power Save Mode.

• BCLK can be switched off while maintaining LCD refresh.

Display Modes

• 1/2/4/8/16 bit-per-pixel (bpp) support.

• Up to 64 gray shades using FRM and dithering on

monochrome passive LCD panels.

• Up to 64K colors on passive STN panels.

• Up to 64K colors on active matrix panels.

• SwivelView: direct hardware rotation of display image

by 90°, 180°, 270°.

• “Picture-in-Picture Plus”: displays a variable size

window overlaid over background image.

• Ink Layer.

• Partial Display Support (available on Type 3 TFT).

• Double Buffering/multi-pages: provides smooth

animation and instantaneous screen update.

Clock Source

• Two clock inputs (single clock possible).

• Clock source can be internally divided down for a

higher frequency clock input.

• 12MHz Crystal Input.

Operating Voltage

•CORE

VDD

1.8 to 2.2 volts.

•IO

VDD

3.0 to 3.6volts.

Package

• 120-pin PFBGA.

CONTACT YOUR SALES REPRESENTATIVE FOR THESE COMPREHENSIVE DESIGN TOOLS

• S1D13708 Technical

Manual

•Palm OS



Hardware

Abstraction Layer

• S5U13708 Evaluation Boards • Windows



CE Display Driver

• CPU Independent Software

Utilities

•VXWorks



Tornado

TM

Display

Driver

Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/

EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document are

accurate or current. The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws.

EPSON is a registered trademark of Seiko Epson Corporation. Palm Computing is a registered trademark and the Palm OS platform Platinum logo is a trademark

of Palm Computing, Inc., 3Com or its subsidiaries. Microsoft, Windows, and the Windows Embedded Partner Logo are registered trademarks of Microsoft Corpo-

ration. All other trademarks are the property of their respective owners.

Japan

Seiko Epson Corporation

Electronic Devices Marketing Division

421-8, Hino, Hino-shi

Tokyo 191-8501, Japan

Tel: 042-587-5812

Fax: 042-587-5564

http://www.epson.co.jp

Hong Kong

Epson Hong Kong Ltd.

20/F., Harbour Centre

25 Harbour Road

Wanchai, Hong Kong

Tel: 2585-4600

Fax: 2827-4346

http://www.epson.com.hk/

Taiwan

Epson Taiwan Technology & Trading Ltd.

10F, No. 287

Nanking East Road

Sec. 3, Taipei, Taiwan

Tel: 02-2717-7360

Fax: 02-2712-9164

http://www.epson.com.tw/

Singapore

Epson Singapore Pte., Ltd.

No. 1

Temasek Avenue #36-00

Millenia Tower

Singapore, 039192

Tel: 337-7911

Fax: 334-2716

http://www.epson.com.sg/

Europe

Epson Europe Electronics GmbH

Riesstrasse 15

80992 Munich, Germany

Tel: 089-14005-0

Fax: 089-14005-110

http://www.epson-electronics.de

North America

Epson Electronics America, Inc.

150 River Oaks Parkway

San Jose, CA 95134, USA

Tel: (408) 922-0200

Fax: (408) 922-0238

http://www.eea.epson.com

S1D13708 Embedded Memory LCD Controller

Hardware Functional Specification

Document Number: X39A-A-001-02

Information in this document is subject to change without notice. You may download and use this document, but only for your own use in

evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any

representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain

material protected under U.S. and/or International Patent laws.

EPSON is a registered trademark of Seiko Epson Corporation. All other Trademarks are the property of their respective owners

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Table of Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

1.1 Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

1.2 Overview Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.1 Integrated Frame Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.2 CPU Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.3 Display Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.4 Display Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.5 Display Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.6 Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.7 Operating Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.8 Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3 Typical System Implementation Diagrams . . . . . . . . . . . . . . . . . . . . . . 19

4 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.1 Pinout Diagram - PFBGA - 120pin . . . . . . . . . . . . . . . . . . . . . . 27

4.2 Pinout Diagram - Die Form . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.3 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.3.1 Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.3.2 LCD Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.3.3 Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

4.3.4 Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

4.3.5 Power And Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

4.4 Summary of Configuration Options . . . . . . . . . . . . . . . . . . . . . . 38

4.5 Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . 39

4.6 LCD Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . 40

5 D.C. Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

6 A.C. Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

6.1 Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

6.1.1 Input Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

6.1.2 Internal Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

6.2 CPU Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

6.2.1 Generic #1 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

6.2.2 Generic #2 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

6.2.3 Hitachi SH-4 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

6.2.4 Hitachi SH-3 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

6.2.5 Motorola MC68K #1 Interface Timing (e.g. MC68000) . . . . . . . . . . . . . . . 52

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6.2.6 Motorola MC68K #2 Interface Timing (e.g. MC68030) . . . . . . . . . . . . . . . 54

6.2.7 Motorola REDCAP2 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . 56

6.2.8 Motorola DragonBall Interface Timing with DTACK

(e.g. MC68EZ328/MC68VZ328) . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

6.2.9 Motorola DragonBall Interface Timing w/o DTACK

(e.g. MC68EZ328/MC68VZ328) . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

6.2.10 Indirect Interface Timing (Mode 68) . . . . . . . . . . . . . . . . . . . . . . . . . 62

6.2.11 Indirect Interface Timing (Mode 80) . . . . . . . . . . . . . . . . . . . . . . . . . 64

6.3 LCD Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . .66

6.3.1 Passive/TFT Power-On Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

6.3.2 Passive/TFT Power-Off Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

6.4 Display Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

6.4.1 Generic STN Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

6.4.2 Single Monochrome 4-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . 72

6.4.3 Single Monochrome 8-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . 74

6.4.4 Single Color 4-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

6.4.5 Single Color 8-Bit Panel Timing (Format 1) . . . . . . . . . . . . . . . . . . . . . 78

6.4.6 Single Color 8-Bit Panel Timing (Format 2) . . . . . . . . . . . . . . . . . . . . . 80

6.4.7 Single Color 16-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

6.4.8 Generic TFT Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

6.4.9 9/12/18-Bit TFT Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

6.4.10 160x160 Sharp ‘Direct’ HR-TFT Panel Timing (e.g. LQ031B1DDxx) . . . . . . . 88

6.4.11 320x240 Sharp ‘Direct’ HR-TFT Panel Timing (e.g. LQ039Q2DS01) . . . . . . . . 92

6.4.12 160x240 Epson D-TFD Panel Timing (e.g. LF26SCR) . . . . . . . . . . . . . . . . 94

6.4.13 320x240 Epson D-TFD Panel Timing (e.g. LF37SQR) . . . . . . . . . . . . . . . . 98

6.4.14 TFT Type 2 Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102

6.4.15 TFT Type 3 Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105

6.4.16 TFT Type 4 Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109

7 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

7.1 Clock Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

7.1.1 BCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112

7.1.2 MCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112

7.1.3 PCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113

7.1.4 PWMCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115

7.2 Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

7.3 Clocks versus Functions . . . . . . . . . . . . . . . . . . . . . . . . . . 117

8 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

8.1 Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

8.2 Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

8.3 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

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8.3.1 Read-Only Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . .121

8.3.2 Clock Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .122

8.3.3 Look-Up Table Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

8.3.4 Panel Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126

8.3.5 Display Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133

8.3.6 Picture-in-Picture Plus Registers . . . . . . . . . . . . . . . . . . . . . . . . . . .138

8.3.7 Miscellaneous Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143

8.3.8 General IO Pins Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145

8.3.9 Pulse Width Modulation (PWM) Clock and Contrast Voltage (CV)

Pulse Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150

8.3.10 Extended Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154

9 Frame Rate Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

10 Display Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

11 Look-Up Table Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

11.1 Monochrome Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . .173

11.2 Color Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175

12 SwivelView™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

12.1 Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179

12.2 90° SwivelView™ . . . . . . . . . . . . . . . . . . . . . . . . . . . .179

12.2.1 Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180

12.3 180° SwivelView™ . . . . . . . . . . . . . . . . . . . . . . . . . . . .181

12.3.1 Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181

12.4 270° SwivelView™ . . . . . . . . . . . . . . . . . . . . . . . . . . . .182

12.4.1 Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183

13 Picture-in-Picture Plus (PIP+) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

13.1 Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184

13.2 With SwivelView Enabled . . . . . . . . . . . . . . . . . . . . . . . . .185

13.2.1 SwivelView 90° . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185

13.2.2 SwivelView 180° . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185

13.2.3 SwivelView 270° . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186

14 Ink Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

14.1 Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187

14.2 Controlling the Ink Layer . . . . . . . . . . . . . . . . . . . . . . . . . .187

14.3 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188

15 Indirect Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

15.1 Mode 68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190

15.2 Mode 80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200

15.3 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209

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16 Embedded Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

16.1 Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

17 Big-Endian Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

17.1 Byte Swapping Bus Data . . . . . . . . . . . . . . . . . . . . . . . . . . 211

17.1.1 16 Bpp Color Depth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212

17.1.2 1/2/4/8 Bpp Color Depth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213

18 Power Save Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

19 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

20 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

21 Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

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List of Tables

Table 4-1: PFBGA 120-pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 4-2: S1D13708 Pad Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 4-3: Host Interface Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 4-4: LCD Interface Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 4-5: Clock Input Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 4-6: Miscellaneous Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 4-7: Power And Ground Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 4-8: Summary of Power-On/Reset Options . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 4-9: Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 4-10: LCD Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 5-1: Absolute Maximum Ratings (Preliminary - Subject to Change). . . . . . . . . . . . . . 41

Table 5-2: Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 5-3: Electrical Characteristics for VDD = 3.3V typical. . . . . . . . . . . . . . . . . . . . . 41

Table 6-1: Clock Input Requirements for CLKI when CLKI to BCLK divide > 1 . . . . . . . . . . 42

Table 6-2: Clock Input Requirements for CLKI when CLKI to BCLK divide = 1 . . . . . . . . . . 43

Table 6-3: Clock Input Requirements for CLKI2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 6-4: Internal Clock Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 6-5: Generic #1 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 6-6: Generic #2 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 6-7: Hitachi SH-4 Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 6-8: Hitachi SH-3 Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 6-9: Motorola MC68K #1 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 6-10: Motorola MC68K #2 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 6-11: Motorola REDCAP2 Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 6-12: Motorola DragonBall Interface with DTACK Timing. . . . . . . . . . . . . . . . . . . 59

Table 6-13: Motorola DragonBall Interface without DTACK Timing . . . . . . . . . . . . . . . . . 61

Table 6-14: Indirect Interface Timing (Mode 68). . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 6-15: Indirect Interface Timing (Mode 80). . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 6-16: Passive/TFT Power-On Sequence Timing . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 6-17: Passive/TFT Power-Off Sequence Timing. . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 6-18: Panel Timing Parameter Definition and Register Summary . . . . . . . . . . . . . . . . 69

Table 6-19: Single Monochrome 4-Bit Panel A.C. Timing. . . . . . . . . . . . . . . . . . . . . . . 73

Table 6-20: Single Monochrome 8-Bit Panel A.C. Timing. . . . . . . . . . . . . . . . . . . . . . . 75

Table 6-21: Single Color 4-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Table 6-22: Single Color 8-Bit Panel A.C. Timing (Format 1) . . . . . . . . . . . . . . . . . . . . . 79

Table 6-23: Single Color 8-Bit Panel A.C. Timing (Format 2) . . . . . . . . . . . . . . . . . . . . . 81

Table 6-24: Single Color 16-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 83

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Table 6-25: TFT A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Table 6-26: 160x160 Sharp ‘Direct’ HR-TFT Horizontal Timing . . . . . . . . . . . . . . . . . . . 89

Table 6-27: 160x160 Sharp ‘Direct’ HR-TFT Panel Vertical Timing . . . . . . . . . . . . . . . . . 91

Table 6-28: 320x240 Sharp ‘Direct’ HR-TFT Panel Horizontal Timing . . . . . . . . . . . . . . . . 93

Table 6-29: 320x240 Sharp ‘Direct’ HR-TFT Panel Vertical Timing . . . . . . . . . . . . . . . . . 93

Table 6-30: 160x240 Epson D-TFD Panel Horizontal Timing . . . . . . . . . . . . . . . . . . . . . 95

Table 6-31: 160x240 Epson D-TFD Panel GCP Horizontal Timing . . . . . . . . . . . . . . . . . . 96

Table 6-32: 160x240 Epson D-TFD Panel Vertical Timing . . . . . . . . . . . . . . . . . . . . . . 97

Table 6-33: 320x240 Epson D-TFD Panel Horizontal Timing . . . . . . . . . . . . . . . . . . . . . 99

Table 6-34: 320x240 Epson D-TFD Panel GCP Horizontal Timing . . . . . . . . . . . . . . . . . .100

Table 6-35: 320x240 Epson D-TFD Panel Vertical Timing . . . . . . . . . . . . . . . . . . . . . .101

Table 6-36: TFT Type 2 Horizontal Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103

Table 6-37: TFT Type 2 Vertical Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104

Table 6-38: TFT Type 3 Horizontal Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106

Table 6-39: TFT Type 3 Vertical Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108

Table 6-40: TFT Type 4 A.C. Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111

Table 7-1: BCLK Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112

Table 7-2: MCLK Clock Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113

Table 7-3: PCLK Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113

Table 7-4: Relationship between MCLK and PCLK. . . . . . . . . . . . . . . . . . . . . . . . . .115

Table 7-5: PWMCLK Clock Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115

Table 7-6: S1D13708 Internal Clock Requirements . . . . . . . . . . . . . . . . . . . . . . . . . .117

Table 8-1: S1D13708 Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119

Table 8-2: MCLK Divide Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122

Table 8-3: PCLK Divide Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122

Table 8-4: PCLK Source Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123

Table 8-5: Panel Data Width Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126

Table 8-6: HRTFT/D-TFD Panel Resolution Selection . . . . . . . . . . . . . . . . . . . . . . . .126

Table 8-7: LCD Panel Type Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127

Table 8-8: Inverse Video Mode Select Options . . . . . . . . . . . . . . . . . . . . . . . . . . . .134

Table 8-9: LCD Bit-per-pixel Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135

Table 8-10: SwivelViewTM Mode Select Options . . . . . . . . . . . . . . . . . . . . . . . . . . .136

Table 8-11: 32-bit Address Increments for Color Depth . . . . . . . . . . . . . . . . . . . . . . . .139

Table 8-12: 32-bit Address Increments for Color Depth . . . . . . . . . . . . . . . . . . . . . . . .140

Table 8-13: 32-bit Address Increments for Color Depth . . . . . . . . . . . . . . . . . . . . . . . .141

Table 8-14: 32-bit Address Increments for Color Depth . . . . . . . . . . . . . . . . . . . . . . . .142

Table 8-15: PWM Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150

Table 8-16: CV Pulse Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151

Table 8-17: PWM Clock Divide Select Options . . . . . . . . . . . . . . . . . . . . . . . . . . . .152

Table 8-18: CV Pulse Divide Select Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152

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Table 8-19: PWMOUT Duty Cycle Select Options. . . . . . . . . . . . . . . . . . . . . . . . . . .153

Table 8-20: Extended Panel Type Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155

Table 8-21: VCLK Hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159

Table 8-22: VCLK Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159

Table 8-23: AP Pulse Width. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160

Table 8-24: AP Rising Position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160

Table 8-25: GPO2 PCLK2 Divide Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164

Table 8-26: GPO1 PCLK1 Divide Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164

Table 8-27: Number of Source Driver ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170

Table 18-1: Power Save Mode Function Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .214

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Epson Research and Development Page 11

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Issue Date: 02/03/07 X39A-A-001-02

List of Figures

Figure 3-1 Typical System Diagram (Generic #1 Bus) . . . . . . . . . . . . . . . . . . . . . . . .19

Figure 3-2 Typical System Diagram (Generic #2 Bus) . . . . . . . . . . . . . . . . . . . . . . . .19

Figure 3-3 Typical System Diagram (Hitachi SH-4 Bus) . . . . . . . . . . . . . . . . . . . . . . .20

Figure 3-4 Typical System Diagram (Hitachi SH-3 Bus) . . . . . . . . . . . . . . . . . . . . . . .21

Figure 3-5 Typical System Diagram (MC68K # 1, Motorola 16-Bit 68000) . . . . . . . . . . . . .22

Figure 3-6 Typical System Diagram (MC68K #2, Motorola 32-Bit 68030). . . . . . . . . . . . . .23

Figure 3-7 Typical System Diagram (Motorola REDCAP2 Bus) . . . . . . . . . . . . . . . . . . .24

Figure 3-8 Typical System Diagram (Motorola MC68EZ328/MC68VZ328 “DragonBall” Bus). . .25

Figure 3-9 Typical System Diagram (Indirect Interface, Mode 68) . . . . . . . . . . . . . . . . . .25

Figure 3-10 Typical System Diagram (Indirect Interface, Mode 80) . . . . . . . . . . . . . . . . . .26

Figure 4-1 Pinout Diagram - PFBGA 120-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Figure 6-1 Clock Input Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Figure 6-2 Generic #1 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Figure 6-3 Generic #2 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

Figure 6-4 Hitachi SH-4 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Figure 6-5 Hitachi SH-3 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Figure 6-6 Motorola MC68K #1 Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . .52

Figure 6-7 Motorola MC68K #2 Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . .54

Figure 6-8 Motorola REDCAP2 Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . .56

Figure 6-9 Motorola DragonBall Interface with DTACK Timing . . . . . . . . . . . . . . . . . . .58

Figure 6-10 Motorola DragonBall Interface without DTACK# Timing . . . . . . . . . . . . . . . .60

Figure 6-11 Indirect Interface Timing (Mode 68) . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

Figure 6-12 Indirect Interface Timing (Mode 80) . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

Figure 6-13 Passive/TFT Power-On Sequence Timing . . . . . . . . . . . . . . . . . . . . . . . . .66

Figure 6-14 Passive/TFT Power-Off Sequence Timing . . . . . . . . . . . . . . . . . . . . . . . . .67

Figure 6-15 Panel Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

Figure 6-16 Generic STN Panel Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

Figure 6-17 Single Monochrome 4-Bit Panel Timing. . . . . . . . . . . . . . . . . . . . . . . . . .72

Figure 6-18 Single Monochrome 4-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . .73

Figure 6-19 Single Monochrome 8-Bit Panel Timing. . . . . . . . . . . . . . . . . . . . . . . . . .74

Figure 6-20 Single Monochrome 8-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . .75

Figure 6-21 Single Color 4-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

Figure 6-22 Single Color 4-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . .77

Figure 6-23 Single Color 8-Bit Panel Timing (Format 1) . . . . . . . . . . . . . . . . . . . . . . . .78

Figure 6-24 Single Color 8-Bit Panel A.C. Timing (Format 1) . . . . . . . . . . . . . . . . . . . . .79

Figure 6-25 Single Color 8-Bit Panel Timing (Format 2) . . . . . . . . . . . . . . . . . . . . . . . .80

Figure 6-26 Single Color 8-Bit Panel A.C. Timing (Format 2) . . . . . . . . . . . . . . . . . . . . .81

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Figure 6-27 Single Color 16-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82

Figure 6-28 Single Color 16-Bit Panel A.C. Timing. . . . . . . . . . . . . . . . . . . . . . . . . . .83

Figure 6-29 Generic TFT Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

Figure 6-30 18-Bit TFT Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85

Figure 6-31 TFT A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

Figure 6-32 160x160 Sharp ‘Direct’ HR-TFT Panel Horizontal Timing . . . . . . . . . . . . . . . .88

Figure 6-33 160x160 Sharp ‘Direct’ HR-TFT Panel Vertical Timing. . . . . . . . . . . . . . . . . .90

Figure 6-34 320x240 Sharp ‘Direct’ HR-TFT Panel Horizontal Timing . . . . . . . . . . . . . . . .92

Figure 6-35 320x240 Sharp ‘Direct’ HR-TFT Panel Vertical Timing. . . . . . . . . . . . . . . . . .93

Figure 6-36 160x240 Epson D-TFD Panel Horizontal Timing . . . . . . . . . . . . . . . . . . . . .94

Figure 6-37 160x240 Epson D-TFD Panel GCP Horizontal Timing . . . . . . . . . . . . . . . . . .96

Figure 6-38 160x240 Epson D-TFD Panel Vertical Timing. . . . . . . . . . . . . . . . . . . . . . .97

Figure 6-39 320x240 Epson D-TFD Panel Horizontal Timing . . . . . . . . . . . . . . . . . . . . .98

Figure 6-40 320x240 Epson D-TFD Panel GCP Horizontal Timing . . . . . . . . . . . . . . . . . 100

Figure 6-41 320x240 Epson D-TFD Panel Vertical Timing. . . . . . . . . . . . . . . . . . . . . . 101

Figure 6-42 TFT Type 2 Horizontal Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Figure 6-43 TFT Type 2 Vertical Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Figure 6-44 TFT Type 3 Horizontal Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Figure 6-45 TFT Type 3 Vertical Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Figure 6-46 TFT Type 4 Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Figure 6-47 TFT Type 4 A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Figure 7-1 Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Figure 8-1 Display Data Byte/Word Swap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Figure 8-2 PWM Clock/CV Pulse Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 150

Figure 10-1 4/8/16 Bit-Per-Pixel Display Data Memory Organization . . . . . . . . . . . . . . . . 172

Figure 11-1 1 Bit-per-pixel Monochrome Mode Data Output Path . . . . . . . . . . . . . . . . . . 173

Figure 11-2 2 Bit-per-pixel Monochrome Mode Data Output Path . . . . . . . . . . . . . . . . . . 173

Figure 11-3 4 Bit-per-pixel Monochrome Mode Data Output Path . . . . . . . . . . . . . . . . . . 174

Figure 11-4 8 Bit-per-pixel Monochrome Mode Data Output Path . . . . . . . . . . . . . . . . . . 174

Figure 11-5 1 Bit-Per-Pixel Color Mode Data Output Path . . . . . . . . . . . . . . . . . . . . . . 175

Figure 11-6 2 Bit-Per-Pixel Color Mode Data Output Path . . . . . . . . . . . . . . . . . . . . . . 176

Figure 11-7 4 Bit-Per-Pixel Color Mode Data Output Path . . . . . . . . . . . . . . . . . . . . . . 177

Figure 11-8 8 Bit-per-pixel Color Mode Data Output Path . . . . . . . . . . . . . . . . . . . . . . 178

Figure 12-1 Relationship Between The Screen Image and the Image Refreshed in 90× SwivelView.179

Figure 12-2 Relationship Between The Screen Image and the Image Refreshed in 180× SwivelView.181

Figure 12-3 Relationship Between The Screen Image and the Image Refreshed in 270× SwivelView.182

Figure 13-1 Picture-in-Picture Plus with SwivelView disabled . . . . . . . . . . . . . . . . . . . . 184

Figure 13-2 Picture-in-Picture Plus with SwivelView 90° enabled . . . . . . . . . . . . . . . . . . 185

Figure 13-3 Picture-in-Picture Plus with SwivelView 180° enabled . . . . . . . . . . . . . . . . . 185

Figure 13-4 Picture-in-Picture Plus with SwivelView 270° enabled . . . . . . . . . . . . . . . . . 186

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Figure 14-1 Memory Mapping for Ink Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

Figure 14-2 Transparent Color Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

Figure 15-1 Sample timing of “register write” with Mode 68. . . . . . . . . . . . . . . . . . . . . 190

Figure 15-2 Sample timing of “register read” with Mode 68 . . . . . . . . . . . . . . . . . . . . . 191

Figure 15-3 Sample timing of “memory write” with Mode 68, Big Endian . . . . . . . . . . . . . 192

Figure 15-4 Sample timing of “memory read” with Mode 68, Big Endian . . . . . . . . . . . . . . 194

Figure 15-5 Sample timing of “register write” for Mode 68 when Memory Access Select Enabled . 196

Figure 15-6 Sample timing of “register read” for Mode 68 when Memory Access Select Enabled . 198

Figure 15-7 Sample timing of “register write” with Mode 80. . . . . . . . . . . . . . . . . . . . . 200

Figure 15-8 Sample timing of “register read” with Mode 80 . . . . . . . . . . . . . . . . . . . . . 201

Figure 15-9 Sample timing of “memory write” with mode 80, little endian . . . . . . . . . . . . . 202

Figure 15-10Sample timing of “memory read” with mode 80, Little endian . . . . . . . . . . . . . 204

Figure 15-11Sample timing of “memory write” for Mode 80 when Memory Access Select Enabled 206

Figure 15-12Sample timing of “memory read” for Mode 80 when Memory Access Select Enabled . 208

Figure 16-1 Recommended Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . 210

Figure 17-1 Byte-swapping for 16 Bpp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

Figure 17-2 Byte-swapping for 1/2/4/8 Bpp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

Figure 19-1 Mechanical Data PFBGA 120-pin Package . . . . . . . . . . . . . . . . . . . . . . . 215

Page 14 Epson Research and Development

Vancouver Design Center

S1D13708 Hardware Functional Specification

X39A-A-001-02 Issue Date: 02/03/07

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